Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 1 | /*
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| 2 | * Driver for the Conexant CX25821 PCIe bridge
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| 3 | *
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| 4 | * Copyright (C) 2009 Conexant Systems Inc.
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| 5 | * Authors <hiep.huynh@conexant.com>, <shu.lin@conexant.com>
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| 6 | *
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| 7 | * This program is free software; you can redistribute it and/or modify
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| 8 | * it under the terms of the GNU General Public License as published by
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| 9 | * the Free Software Foundation; either version 2 of the License, or
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| 10 | * (at your option) any later version.
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| 11 | *
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| 12 | * This program is distributed in the hope that it will be useful,
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| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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| 15 | *
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| 16 | * GNU General Public License for more details.
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| 17 | *
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| 18 | * You should have received a copy of the GNU General Public License
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| 19 | * along with this program; if not, write to the Free Software
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| 20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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| 21 | */
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| 22 |
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| 23 |
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| 24 | #include "cx25821-video.h"
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| 25 | #include "cx25821-video-upstream.h"
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| 26 |
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| 27 | #include <linux/fs.h>
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| 28 | #include <linux/errno.h>
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| 29 | #include <linux/kernel.h>
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| 30 | #include <linux/init.h>
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| 31 | #include <linux/module.h>
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| 32 | #include <linux/syscalls.h>
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| 33 | #include <linux/file.h>
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| 34 | #include <linux/fcntl.h>
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| 35 | #include <asm/uaccess.h>
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| 36 |
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| 37 |
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| 38 | MODULE_DESCRIPTION("v4l2 driver module for cx25821 based TV cards");
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| 39 | MODULE_AUTHOR("Hiep Huynh <hiep.huynh@conexant.com>");
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| 40 | MODULE_LICENSE("GPL");
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| 41 |
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| 42 |
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| 43 | static int _intr_msk = FLD_VID_SRC_RISC1 | FLD_VID_SRC_UF | FLD_VID_SRC_SYNC | FLD_VID_SRC_OPC_ERR;
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| 44 |
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| 45 | int cx25821_sram_channel_setup_upstream(struct cx25821_dev *dev,
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Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 46 | struct sram_channel *ch,
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| 47 | unsigned int bpl, u32 risc)
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Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 48 | {
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| 49 | unsigned int i, lines;
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| 50 | u32 cdt;
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| 51 |
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| 52 |
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| 53 | if (ch->cmds_start == 0) {
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Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 54 | cx_write(ch->ptr1_reg, 0);
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| 55 | cx_write(ch->ptr2_reg, 0);
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| 56 | cx_write(ch->cnt2_reg, 0);
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| 57 | cx_write(ch->cnt1_reg, 0);
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| 58 | return 0;
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Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 59 | }
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| 60 |
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| 61 | bpl = (bpl + 7) & ~7; /* alignment */
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| 62 | cdt = ch->cdt;
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| 63 | lines = ch->fifo_size / bpl;
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| 64 |
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| 65 | if (lines > 4)
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| 66 | {
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Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 67 | lines = 4;
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Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 68 | }
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| 69 |
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| 70 | BUG_ON(lines < 2);
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| 71 |
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| 72 |
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| 73 | /* write CDT */
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| 74 | for (i = 0; i < lines; i++) {
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Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 75 | cx_write(cdt + 16*i, ch->fifo_start + bpl*i);
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| 76 | cx_write(cdt + 16*i + 4, 0);
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| 77 | cx_write(cdt + 16*i + 8, 0);
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| 78 | cx_write(cdt + 16*i + 12, 0);
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Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 79 | }
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| 80 |
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| 81 | /* write CMDS */
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| 82 | cx_write(ch->cmds_start + 0, risc);
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| 83 |
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| 84 | cx_write(ch->cmds_start + 4, 0);
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| 85 | cx_write(ch->cmds_start + 8, cdt);
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| 86 | cx_write(ch->cmds_start + 12, (lines*16) >> 3);
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| 87 | cx_write(ch->cmds_start + 16, ch->ctrl_start);
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Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 88 |
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Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 89 |
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| 90 | cx_write(ch->cmds_start + 20, VID_IQ_SIZE_DW);
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| 91 |
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| 92 | for (i = 24; i < 80; i += 4)
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Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 93 | cx_write(ch->cmds_start + i, 0);
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Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 94 |
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| 95 | /* fill registers */
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| 96 | cx_write(ch->ptr1_reg, ch->fifo_start);
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| 97 | cx_write(ch->ptr2_reg, cdt);
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| 98 | cx_write(ch->cnt2_reg, (lines*16) >> 3);
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| 99 | cx_write(ch->cnt1_reg, (bpl >> 3) - 1);
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| 100 |
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| 101 | return 0;
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| 102 | }
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| 103 |
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| 104 | static __le32 *cx25821_update_riscprogram( struct cx25821_dev *dev,
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Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 105 | __le32 *rp, unsigned int offset, unsigned int bpl,
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| 106 | u32 sync_line, unsigned int lines, int fifo_enable, int field_type)
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Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 107 | {
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| 108 | unsigned int line, i;
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| 109 | int dist_betwn_starts = bpl * 2;
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| 110 |
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| 111 |
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| 112 | *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
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| 113 |
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| 114 |
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| 115 | if( USE_RISC_NOOP_VIDEO )
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| 116 | {
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Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 117 | for( i = 0; i < NUM_NO_OPS; i++ )
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| 118 | {
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| 119 | *(rp++) = cpu_to_le32(RISC_NOOP);
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| 120 | }
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Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 121 | }
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| 122 |
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| 123 | /* scan lines */
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| 124 | for (line = 0; line < lines; line++)
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| 125 | {
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Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 126 | *(rp++) = cpu_to_le32(RISC_READ|RISC_SOL|RISC_EOL|bpl);
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| 127 | *(rp++) = cpu_to_le32(dev->_data_buf_phys_addr+offset);
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| 128 | *(rp++) = cpu_to_le32(0); /* bits 63-32 */
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| 129 |
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| 130 | if ( (lines <= NTSC_FIELD_HEIGHT) || (line < (NTSC_FIELD_HEIGHT-1)) || !(dev->_isNTSC) )
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| 131 | {
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| 132 | offset += dist_betwn_starts;
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| 133 | }
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Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 134 | }
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| 135 |
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| 136 | return rp;
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| 137 | }
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| 138 |
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| 139 | static __le32 *cx25821_risc_field_upstream( struct cx25821_dev *dev, __le32 *rp,
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Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 140 | dma_addr_t databuf_phys_addr,
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| 141 | unsigned int offset, u32 sync_line,
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| 142 | unsigned int bpl, unsigned int lines, int fifo_enable, int field_type)
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Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 143 | {
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| 144 | unsigned int line, i;
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| 145 | struct sram_channel *sram_ch = &dev->sram_channels[dev->_channel_upstream_select];
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| 146 | int dist_betwn_starts = bpl * 2;
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| 147 |
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Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 148 |
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Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 149 | /* sync instruction */
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| 150 | if (sync_line != NO_SYNC_LINE)
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| 151 | {
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Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 152 | *(rp++) = cpu_to_le32(RISC_RESYNC | sync_line);
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Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 153 | }
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| 154 |
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| 155 |
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| 156 | if( USE_RISC_NOOP_VIDEO )
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| 157 | {
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Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 158 | for( i = 0; i < NUM_NO_OPS; i++ )
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| 159 | {
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| 160 | *(rp++) = cpu_to_le32(RISC_NOOP);
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| 161 | }
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Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 162 | }
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| 163 |
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| 164 | /* scan lines */
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| 165 | for (line = 0; line < lines; line++)
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| 166 | {
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Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 167 | *(rp++) = cpu_to_le32(RISC_READ|RISC_SOL|RISC_EOL|bpl);
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| 168 | *(rp++) = cpu_to_le32(databuf_phys_addr+offset);
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| 169 | *(rp++) = cpu_to_le32(0); /* bits 63-32 */
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| 170 |
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| 171 |
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| 172 | if ( (lines <= NTSC_FIELD_HEIGHT) || (line < (NTSC_FIELD_HEIGHT-1)) || !(dev->_isNTSC) )
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| 173 | {
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| 174 | offset += dist_betwn_starts; //to skip the other field line
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| 175 | }
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| 176 |
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Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 177 |
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Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 178 | // check if we need to enable the FIFO after the first 4 lines
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| 179 | // For the upstream video channel, the risc engine will enable the FIFO.
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| 180 | if ( fifo_enable && line == 3 )
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| 181 | {
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| 182 | *(rp++) = RISC_WRITECR;
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| 183 | *(rp++) = sram_ch->dma_ctl;
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| 184 | *(rp++) = FLD_VID_FIFO_EN;
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| 185 | *(rp++) = 0x00000001;
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| 186 | }
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Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 187 | }
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Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 188 |
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Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 189 | return rp;
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| 190 | }
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| 191 |
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| 192 | int cx25821_risc_buffer_upstream( struct cx25821_dev *dev,
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Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 193 | struct pci_dev *pci,
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| 194 | unsigned int top_offset,
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| 195 | unsigned int bpl, unsigned int lines)
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Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 196 | {
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| 197 | __le32 *rp;
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| 198 | int fifo_enable = 0;
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| 199 | int singlefield_lines = lines >> 1; //get line count for single field
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| 200 | int odd_num_lines = singlefield_lines;
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| 201 | int frame = 0;
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| 202 | int frame_size = 0;
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| 203 | int databuf_offset = 0;
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| 204 | int risc_program_size = 0;
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| 205 | int risc_flag = RISC_CNT_RESET;
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| 206 | unsigned int bottom_offset = bpl;
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| 207 | dma_addr_t risc_phys_jump_addr;
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Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 208 |
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Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 209 | if( dev->_isNTSC )
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| 210 | {
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Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 211 | odd_num_lines = singlefield_lines + 1;
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| 212 | risc_program_size = FRAME1_VID_PROG_SIZE;
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| 213 | frame_size = (bpl == Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 : FRAME_SIZE_NTSC_Y422;
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Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 214 | }
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| 215 | else
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| 216 | {
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Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 217 | risc_program_size = PAL_VID_PROG_SIZE;
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| 218 | frame_size = (bpl == Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
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Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 219 | }
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| 220 |
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Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 221 |
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Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 222 | /* Virtual address of Risc buffer program */
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| 223 | rp = dev->_dma_virt_addr;
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| 224 |
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| 225 | for( frame = 0; frame < NUM_FRAMES; frame++ )
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| 226 | {
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Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 227 | databuf_offset = frame_size * frame;
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| 228 |
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| 229 | if (UNSET != top_offset)
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| 230 | {
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| 231 | fifo_enable = (frame == 0) ? FIFO_ENABLE : FIFO_DISABLE;
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| 232 | rp = cx25821_risc_field_upstream(dev, rp, dev->_data_buf_phys_addr+databuf_offset, top_offset, 0, bpl, odd_num_lines, fifo_enable, ODD_FIELD);
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| 233 | }
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Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 234 |
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Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 235 |
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| 236 | fifo_enable = FIFO_DISABLE;
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| 237 |
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| 238 |
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| 239 | //Even Field
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| 240 | rp = cx25821_risc_field_upstream(dev, rp, dev->_data_buf_phys_addr+databuf_offset, bottom_offset, 0x200, bpl, singlefield_lines, fifo_enable, EVEN_FIELD);
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Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 241 |
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Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 242 |
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| 243 | if( frame == 0 )
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| 244 | {
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| 245 | risc_flag = RISC_CNT_RESET;
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| 246 | risc_phys_jump_addr = dev->_dma_phys_start_addr + risc_program_size;
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| 247 | }
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| 248 | else
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| 249 | {
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| 250 | risc_phys_jump_addr = dev->_dma_phys_start_addr;
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| 251 | risc_flag = RISC_CNT_INC;
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| 252 | }
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| 253 |
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Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 254 |
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Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 255 | // Loop to 2ndFrameRISC or to Start of Risc program & generate IRQ
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| 256 | *(rp++) = cpu_to_le32(RISC_JUMP|RISC_IRQ1|risc_flag);
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| 257 | *(rp++) = cpu_to_le32(risc_phys_jump_addr);
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| 258 | *(rp++) = cpu_to_le32(0);
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Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 259 | }
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| 260 |
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| 261 | return 0;
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| 262 | }
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| 263 |
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| 264 |
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| 265 | void cx25821_stop_upstream_video_ch1(struct cx25821_dev *dev)
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| 266 | {
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| 267 | struct sram_channel *sram_ch = &dev->sram_channels[VID_UPSTREAM_SRAM_CHANNEL_I];
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| 268 | u32 tmp = 0;
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| 269 |
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| 270 | if( !dev->_is_running )
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| 271 | {
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Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 272 | printk("cx25821: No video file is currently running so return!\n");
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| 273 | return;
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Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 274 | }
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Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 275 |
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Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 276 | //Disable RISC interrupts
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| 277 | tmp = cx_read( sram_ch->int_msk );
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| 278 | cx_write( sram_ch->int_msk, tmp & ~_intr_msk);
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| 279 |
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| 280 | //Turn OFF risc and fifo enable
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| 281 | tmp = cx_read( sram_ch->dma_ctl );
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| 282 | cx_write( sram_ch->dma_ctl, tmp & ~(FLD_VID_FIFO_EN | FLD_VID_RISC_EN) );
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| 283 |
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| 284 | //Clear data buffer memory
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| 285 | if( dev->_data_buf_virt_addr )
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Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 286 | memset( dev->_data_buf_virt_addr, 0, dev->_data_buf_size );
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| 287 |
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Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 288 | dev->_is_running = 0;
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| 289 | dev->_is_first_frame = 0;
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| 290 | dev->_frame_count = 0;
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| 291 | dev->_file_status = END_OF_FILE;
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| 292 |
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| 293 | if( dev->_irq_queues )
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| 294 | {
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Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 295 | kfree(dev->_irq_queues);
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| 296 | dev->_irq_queues = NULL;
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Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 297 | }
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| 298 |
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| 299 | if( dev->_filename != NULL )
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Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 300 | kfree(dev->_filename);
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Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 301 |
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| 302 | tmp = cx_read( VID_CH_MODE_SEL );
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| 303 | cx_write( VID_CH_MODE_SEL, tmp & 0xFFFFFE00);
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| 304 | }
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| 305 |
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| 306 | void cx25821_free_mem_upstream_ch1(struct cx25821_dev *dev)
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| 307 | {
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| 308 | if( dev->_is_running )
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| 309 | {
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Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 310 | cx25821_stop_upstream_video_ch1(dev);
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Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 311 | }
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| 312 |
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| 313 | if (dev->_dma_virt_addr)
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| 314 | {
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Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 315 | pci_free_consistent(dev->pci, dev->_risc_size, dev->_dma_virt_addr, dev->_dma_phys_addr);
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| 316 | dev->_dma_virt_addr = NULL;
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Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 317 | }
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| 318 |
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| 319 | if (dev->_data_buf_virt_addr)
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| 320 | {
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Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 321 | pci_free_consistent(dev->pci, dev->_data_buf_size, dev->_data_buf_virt_addr, dev->_data_buf_phys_addr);
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| 322 | dev->_data_buf_virt_addr = NULL;
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Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 323 | }
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| 324 | }
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| 325 |
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| 326 |
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| 327 | int cx25821_get_frame(struct cx25821_dev *dev, struct sram_channel *sram_ch )
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| 328 | {
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| 329 | struct file * myfile;
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| 330 | int frame_index_temp = dev->_frame_index;
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| 331 | int i = 0;
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| 332 | int line_size = (dev->_pixel_format == PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
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| 333 | int frame_size = 0;
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| 334 | int frame_offset = 0;
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| 335 | ssize_t vfs_read_retval = 0;
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| 336 | char mybuf[line_size];
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| 337 | loff_t file_offset;
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| 338 | loff_t pos;
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| 339 | mm_segment_t old_fs;
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 340 |
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 341 |
|
| 342 | if( dev->_file_status == END_OF_FILE )
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 343 | return 0;
|
| 344 |
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 345 | if( dev->_isNTSC )
|
| 346 | {
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 347 | frame_size = (line_size == Y411_LINE_SZ) ? FRAME_SIZE_NTSC_Y411 : FRAME_SIZE_NTSC_Y422;
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 348 | }
|
| 349 | else
|
| 350 | {
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 351 | frame_size = (line_size == Y411_LINE_SZ) ? FRAME_SIZE_PAL_Y411 : FRAME_SIZE_PAL_Y422;
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 352 | }
|
| 353 |
|
| 354 | frame_offset = (frame_index_temp > 0) ? frame_size : 0;
|
| 355 | file_offset = dev->_frame_count * frame_size;
|
| 356 |
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 357 |
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 358 | myfile = filp_open( dev->_filename, O_RDONLY | O_LARGEFILE, 0 );
|
| 359 |
|
| 360 |
|
| 361 | if (IS_ERR(myfile))
|
| 362 | {
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 363 | const int open_errno = -PTR_ERR(myfile);
|
| 364 | printk("%s(): ERROR opening file(%s) with errno = %d! \n", __func__, dev->_filename, open_errno);
|
| 365 | return PTR_ERR(myfile);
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 366 | }
|
| 367 | else
|
| 368 | {
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 369 | if( !(myfile->f_op) )
|
| 370 | {
|
| 371 | printk("%s: File has no file operations registered!", __func__);
|
| 372 | filp_close(myfile, NULL);
|
| 373 | return -EIO;
|
| 374 | }
|
| 375 |
|
| 376 |
|
| 377 | if( !myfile->f_op->read )
|
| 378 | {
|
| 379 | printk("%s: File has no READ operations registered!", __func__);
|
| 380 | filp_close(myfile, NULL);
|
| 381 | return -EIO;
|
| 382 | }
|
| 383 |
|
| 384 | pos = myfile->f_pos;
|
| 385 | old_fs = get_fs();
|
| 386 | set_fs(KERNEL_DS);
|
| 387 |
|
| 388 |
|
| 389 | for( i = 0; i < dev->_lines_count; i++ )
|
| 390 | {
|
| 391 | pos = file_offset;
|
| 392 |
|
| 393 | vfs_read_retval = vfs_read(myfile, mybuf, line_size, &pos);
|
| 394 |
|
| 395 | if( vfs_read_retval > 0 && vfs_read_retval == line_size && dev->_data_buf_virt_addr != NULL )
|
| 396 | {
|
| 397 | memcpy( (void*)(dev->_data_buf_virt_addr+frame_offset/4), mybuf, vfs_read_retval);
|
| 398 | }
|
| 399 |
|
| 400 | file_offset += vfs_read_retval;
|
| 401 | frame_offset += vfs_read_retval;
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 402 |
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 403 | if( vfs_read_retval < line_size )
|
| 404 | {
|
| 405 | printk(KERN_INFO "Done: exit %s() since no more bytes to read from Video file.\n", __func__ );
|
| 406 | break;
|
| 407 | }
|
| 408 | }
|
| 409 |
|
| 410 | if( i > 0 )
|
| 411 | dev->_frame_count++;
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 412 |
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 413 | dev->_file_status = (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 414 |
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 415 |
|
| 416 | set_fs(old_fs);
|
| 417 | filp_close(myfile, NULL);
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 418 | }
|
| 419 |
|
| 420 | return 0;
|
| 421 | }
|
| 422 |
|
| 423 | static void cx25821_vidups_handler(struct work_struct *work)
|
| 424 | {
|
| 425 | struct cx25821_dev *dev = container_of(work, struct cx25821_dev, _irq_work_entry);
|
| 426 |
|
| 427 | if( !dev )
|
| 428 | {
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 429 | printk("ERROR %s(): since container_of(work_struct) FAILED! \n", __func__ );
|
| 430 | return;
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 431 | }
|
| 432 |
|
| 433 | cx25821_get_frame( dev, &dev->sram_channels[dev->_channel_upstream_select] );
|
| 434 | }
|
| 435 |
|
| 436 |
|
| 437 | int cx25821_openfile(struct cx25821_dev *dev, struct sram_channel *sram_ch)
|
| 438 | {
|
| 439 | struct file * myfile;
|
| 440 | int i = 0, j = 0;
|
| 441 | int line_size = (dev->_pixel_format == PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
|
| 442 | ssize_t vfs_read_retval = 0;
|
| 443 | char mybuf[line_size];
|
| 444 | loff_t pos;
|
| 445 | loff_t offset = (unsigned long)0;
|
| 446 | mm_segment_t old_fs;
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 447 |
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 448 |
|
| 449 | myfile = filp_open( dev->_filename, O_RDONLY | O_LARGEFILE, 0 );
|
| 450 |
|
| 451 |
|
| 452 | if (IS_ERR(myfile))
|
| 453 | {
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 454 | const int open_errno = -PTR_ERR(myfile);
|
| 455 | printk("%s(): ERROR opening file(%s) with errno = %d! \n", __func__, dev->_filename, open_errno);
|
| 456 | return PTR_ERR(myfile);
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 457 | }
|
| 458 | else
|
| 459 | {
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 460 | if( !(myfile->f_op) )
|
| 461 | {
|
| 462 | printk("%s: File has no file operations registered!", __func__);
|
| 463 | filp_close(myfile, NULL);
|
| 464 | return -EIO;
|
| 465 | }
|
| 466 |
|
| 467 |
|
| 468 | if( !myfile->f_op->read )
|
| 469 | {
|
| 470 | printk("%s: File has no READ operations registered! Returning.", __func__);
|
| 471 | filp_close(myfile, NULL);
|
| 472 | return -EIO;
|
| 473 | }
|
| 474 |
|
| 475 | pos = myfile->f_pos;
|
| 476 | old_fs = get_fs();
|
| 477 | set_fs(KERNEL_DS);
|
| 478 |
|
| 479 |
|
| 480 | for( j = 0; j < NUM_FRAMES; j++ )
|
| 481 | {
|
| 482 | for( i = 0; i < dev->_lines_count; i++ )
|
| 483 | {
|
| 484 | pos = offset;
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 485 |
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 486 | vfs_read_retval = vfs_read(myfile, mybuf, line_size, &pos);
|
| 487 |
|
| 488 | if( vfs_read_retval > 0 && vfs_read_retval == line_size && dev->_data_buf_virt_addr != NULL )
|
| 489 | {
|
| 490 | memcpy( (void*)(dev->_data_buf_virt_addr+offset/4), mybuf, vfs_read_retval);
|
| 491 | }
|
| 492 |
|
| 493 |
|
| 494 | offset += vfs_read_retval;
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 495 |
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 496 | if( vfs_read_retval < line_size )
|
| 497 | {
|
| 498 | printk(KERN_INFO "Done: exit %s() since no more bytes to read from Video file.\n", __func__ );
|
| 499 | break;
|
| 500 | }
|
| 501 | }
|
| 502 |
|
| 503 | if( i > 0 )
|
| 504 | dev->_frame_count++;
|
| 505 |
|
| 506 | if( vfs_read_retval < line_size )
|
| 507 | {
|
| 508 | break;
|
| 509 | }
|
| 510 | }
|
| 511 |
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 512 |
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 513 | dev->_file_status = (vfs_read_retval == line_size) ? IN_PROGRESS : END_OF_FILE;
|
| 514 |
|
| 515 | set_fs(old_fs);
|
| 516 | myfile->f_pos = 0;
|
| 517 | filp_close(myfile, NULL);
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 518 | }
|
| 519 |
|
| 520 | return 0;
|
| 521 | }
|
| 522 |
|
| 523 |
|
| 524 | int cx25821_upstream_buffer_prepare(struct cx25821_dev *dev,
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 525 | struct sram_channel *sram_ch,
|
| 526 | int bpl)
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 527 | {
|
| 528 | int ret = 0;
|
| 529 | dma_addr_t dma_addr;
|
| 530 | dma_addr_t data_dma_addr;
|
| 531 |
|
| 532 | if( dev->_dma_virt_addr != NULL )
|
| 533 | {
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 534 | pci_free_consistent(dev->pci, dev->upstream_riscbuf_size, dev->_dma_virt_addr, dev->_dma_phys_addr);
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 535 | }
|
| 536 |
|
| 537 |
|
| 538 | dev->_dma_virt_addr = pci_alloc_consistent(dev->pci, dev->upstream_riscbuf_size, &dma_addr);
|
| 539 | dev->_dma_virt_start_addr = dev->_dma_virt_addr;
|
| 540 | dev->_dma_phys_start_addr = dma_addr;
|
| 541 | dev->_dma_phys_addr = dma_addr;
|
| 542 | dev->_risc_size = dev->upstream_riscbuf_size;
|
| 543 |
|
| 544 |
|
| 545 | if (!dev->_dma_virt_addr)
|
| 546 | {
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 547 | printk("cx25821: FAILED to allocate memory for Risc buffer! Returning.\n");
|
| 548 | return -ENOMEM;
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 549 | }
|
| 550 |
|
| 551 |
|
| 552 | //Clear memory at address
|
| 553 | memset( dev->_dma_virt_addr, 0, dev->_risc_size );
|
| 554 |
|
| 555 |
|
| 556 | if( dev->_data_buf_virt_addr != NULL )
|
| 557 | {
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 558 | pci_free_consistent(dev->pci, dev->upstream_databuf_size, dev->_data_buf_virt_addr, dev->_data_buf_phys_addr);
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 559 | }
|
| 560 |
|
| 561 | //For Video Data buffer allocation
|
| 562 | dev->_data_buf_virt_addr = pci_alloc_consistent(dev->pci, dev->upstream_databuf_size, &data_dma_addr);
|
| 563 | dev->_data_buf_phys_addr = data_dma_addr;
|
| 564 | dev->_data_buf_size = dev->upstream_databuf_size;
|
| 565 |
|
| 566 | if (!dev->_data_buf_virt_addr)
|
| 567 | {
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 568 | printk("cx25821: FAILED to allocate memory for data buffer! Returning.\n");
|
| 569 | return -ENOMEM;
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 570 | }
|
| 571 |
|
| 572 |
|
| 573 | //Clear memory at address
|
| 574 | memset( dev->_data_buf_virt_addr, 0, dev->_data_buf_size );
|
| 575 |
|
| 576 |
|
| 577 | ret = cx25821_openfile(dev, sram_ch);
|
| 578 | if( ret < 0 )
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 579 | return ret;
|
| 580 |
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 581 |
|
| 582 | //Create RISC programs
|
| 583 | ret = cx25821_risc_buffer_upstream(dev, dev->pci, 0, bpl, dev->_lines_count );
|
| 584 | if (ret < 0)
|
| 585 | {
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 586 | printk(KERN_INFO "cx25821: Failed creating Video Upstream Risc programs! \n");
|
| 587 | goto error;
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 588 | }
|
| 589 |
|
| 590 | return 0;
|
| 591 |
|
| 592 | error:
|
| 593 | return ret;
|
| 594 | }
|
| 595 |
|
| 596 | int cx25821_video_upstream_irq(struct cx25821_dev *dev, int chan_num, u32 status)
|
| 597 | {
|
| 598 | u32 int_msk_tmp;
|
| 599 | struct sram_channel *channel = &dev->sram_channels[chan_num];
|
| 600 | int singlefield_lines = NTSC_FIELD_HEIGHT;
|
| 601 | int line_size_in_bytes = Y422_LINE_SZ;
|
| 602 | int odd_risc_prog_size = 0;
|
| 603 | dma_addr_t risc_phys_jump_addr;
|
| 604 | __le32 * rp;
|
| 605 |
|
| 606 |
|
| 607 |
|
| 608 | if (status & FLD_VID_SRC_RISC1)
|
| 609 | {
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 610 | // We should only process one program per call
|
| 611 | u32 prog_cnt = cx_read( channel->gpcnt );
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 612 |
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 613 | //Since we've identified our IRQ, clear our bits from the interrupt mask and interrupt status registers
|
| 614 | int_msk_tmp = cx_read(channel->int_msk);
|
| 615 | cx_write(channel->int_msk, int_msk_tmp & ~_intr_msk);
|
| 616 | cx_write( channel->int_stat, _intr_msk );
|
| 617 |
|
| 618 | spin_lock(&dev->slock);
|
| 619 |
|
| 620 | dev->_frame_index = prog_cnt;
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 621 |
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 622 | queue_work(dev->_irq_queues, &dev->_irq_work_entry);
|
| 623 |
|
| 624 |
|
| 625 | if ( dev->_is_first_frame )
|
| 626 | {
|
| 627 | dev->_is_first_frame = 0;
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 628 |
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 629 | if( dev->_isNTSC )
|
| 630 | {
|
| 631 | singlefield_lines += 1;
|
| 632 | odd_risc_prog_size = ODD_FLD_NTSC_PROG_SIZE;
|
| 633 | }
|
| 634 | else
|
| 635 | {
|
| 636 | singlefield_lines = PAL_FIELD_HEIGHT;
|
| 637 | odd_risc_prog_size = ODD_FLD_PAL_PROG_SIZE;
|
| 638 | }
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 639 |
|
| 640 |
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 641 | if( dev->_dma_virt_start_addr != NULL )
|
| 642 | {
|
| 643 | line_size_in_bytes = (dev->_pixel_format == PIXEL_FRMT_411) ? Y411_LINE_SZ : Y422_LINE_SZ;
|
| 644 | risc_phys_jump_addr = dev->_dma_phys_start_addr + odd_risc_prog_size;
|
| 645 |
|
| 646 | rp = cx25821_update_riscprogram(dev, dev->_dma_virt_start_addr, TOP_OFFSET, line_size_in_bytes, 0x0, singlefield_lines, FIFO_DISABLE, ODD_FIELD);
|
| 647 |
|
| 648 | // Jump to Even Risc program of 1st Frame
|
| 649 | *(rp++) = cpu_to_le32(RISC_JUMP);
|
| 650 | *(rp++) = cpu_to_le32(risc_phys_jump_addr);
|
| 651 | *(rp++) = cpu_to_le32(0);
|
| 652 | }
|
| 653 | }
|
| 654 |
|
| 655 | spin_unlock(&dev->slock);
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 656 | }
|
| 657 | else
|
| 658 | {
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 659 | if(status & FLD_VID_SRC_UF)
|
| 660 | printk("%s: Video Received Underflow Error Interrupt!\n", __func__);
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 661 |
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 662 | if(status & FLD_VID_SRC_SYNC)
|
| 663 | printk("%s: Video Received Sync Error Interrupt!\n", __func__);
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 664 |
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 665 | if(status & FLD_VID_SRC_OPC_ERR)
|
| 666 | printk("%s: Video Received OpCode Error Interrupt!\n", __func__);
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 667 | }
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 668 |
|
| 669 |
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 670 | if( dev->_file_status == END_OF_FILE )
|
| 671 | {
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 672 | printk("cx25821: EOF Channel 1 Framecount = %d\n", dev->_frame_count );
|
| 673 | return -1;
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 674 | }
|
| 675 |
|
| 676 | //ElSE, set the interrupt mask register, re-enable irq.
|
| 677 | int_msk_tmp = cx_read( channel->int_msk );
|
| 678 | cx_write( channel->int_msk, int_msk_tmp |= _intr_msk );
|
| 679 |
|
| 680 | return 0;
|
| 681 | }
|
| 682 |
|
| 683 | static irqreturn_t cx25821_upstream_irq(int irq, void *dev_id)
|
| 684 | {
|
| 685 | struct cx25821_dev *dev = dev_id;
|
| 686 | u32 msk_stat, vid_status;
|
| 687 | int handled = 0;
|
| 688 | int channel_num = 0;
|
| 689 | struct sram_channel *sram_ch;
|
| 690 |
|
| 691 |
|
| 692 | if( !dev )
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 693 | return -1;
|
| 694 |
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 695 | channel_num = VID_UPSTREAM_SRAM_CHANNEL_I;
|
| 696 |
|
| 697 | sram_ch = &dev->sram_channels[channel_num];
|
| 698 |
|
| 699 | msk_stat = cx_read(sram_ch->int_mstat);
|
| 700 | vid_status = cx_read(sram_ch->int_stat);
|
| 701 |
|
| 702 | // Only deal with our interrupt
|
| 703 | if(vid_status)
|
| 704 | {
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 705 | handled = cx25821_video_upstream_irq(dev, channel_num, vid_status);
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 706 | }
|
| 707 |
|
| 708 | if( handled < 0 )
|
| 709 | {
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 710 | cx25821_stop_upstream_video_ch1(dev);
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 711 | }
|
| 712 | else
|
| 713 | {
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 714 | handled += handled;
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 715 | }
|
| 716 |
|
| 717 | return IRQ_RETVAL(handled);
|
| 718 | }
|
| 719 |
|
| 720 |
|
| 721 | void cx25821_set_pixelengine(struct cx25821_dev *dev, struct sram_channel *ch, int pix_format)
|
| 722 | {
|
| 723 | int width = WIDTH_D1;
|
| 724 | int height = dev->_lines_count;
|
| 725 | int num_lines, odd_num_lines;
|
| 726 | u32 value;
|
| 727 | int vip_mode = OUTPUT_FRMT_656;
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 728 |
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 729 |
|
| 730 | value = ( (pix_format & 0x3) << 12 ) | ( vip_mode & 0x7 );
|
| 731 | value &= 0xFFFFFFEF;
|
| 732 | value |= dev->_isNTSC ? 0 : 0x10;
|
| 733 | cx_write( ch->vid_fmt_ctl, value );
|
| 734 |
|
| 735 |
|
| 736 | // set number of active pixels in each line. Default is 720 pixels in both NTSC and PAL format
|
| 737 | cx_write( ch->vid_active_ctl1, width );
|
| 738 |
|
| 739 | num_lines = (height / 2) & 0x3FF;
|
| 740 | odd_num_lines = num_lines;
|
| 741 |
|
| 742 | if(dev->_isNTSC)
|
| 743 | {
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 744 | odd_num_lines += 1;
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 745 | }
|
| 746 |
|
| 747 | value = (num_lines << 16) | odd_num_lines;
|
| 748 |
|
| 749 | // set number of active lines in field 0 (top) and field 1 (bottom)
|
| 750 | cx_write( ch->vid_active_ctl2, value );
|
| 751 |
|
| 752 | cx_write( ch->vid_cdt_size, VID_CDT_SIZE >> 3 );
|
| 753 | }
|
| 754 |
|
| 755 |
|
| 756 | int cx25821_start_video_dma_upstream(struct cx25821_dev *dev,
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 757 | struct sram_channel *sram_ch)
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 758 | {
|
| 759 | u32 tmp = 0;
|
| 760 | int err = 0;
|
| 761 |
|
| 762 |
|
| 763 | // 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for channel A-C
|
| 764 | tmp = cx_read( VID_CH_MODE_SEL );
|
| 765 | cx_write( VID_CH_MODE_SEL, tmp | 0x1B0001FF);
|
| 766 |
|
| 767 |
|
| 768 | // Set the physical start address of the RISC program in the initial program counter(IPC) member of the cmds.
|
| 769 | cx_write(sram_ch->cmds_start + 0, dev->_dma_phys_addr);
|
| 770 | cx_write(sram_ch->cmds_start + 4, 0); /* Risc IPC High 64 bits 63-32 */
|
| 771 |
|
| 772 | /* reset counter */
|
| 773 | cx_write(sram_ch->gpcnt_ctl, 3);
|
| 774 |
|
| 775 | // Clear our bits from the interrupt status register.
|
| 776 | cx_write( sram_ch->int_stat, _intr_msk );
|
| 777 |
|
| 778 |
|
| 779 | //Set the interrupt mask register, enable irq.
|
| 780 | cx_set(PCI_INT_MSK, cx_read(PCI_INT_MSK) | (1 << sram_ch->irq_bit));
|
| 781 | tmp = cx_read( sram_ch->int_msk );
|
| 782 | cx_write( sram_ch->int_msk, tmp |= _intr_msk );
|
| 783 |
|
| 784 |
|
| 785 | err = request_irq(dev->pci->irq, cx25821_upstream_irq, IRQF_SHARED | IRQF_DISABLED, dev->name, dev);
|
| 786 | if (err < 0)
|
| 787 | {
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 788 | printk(KERN_ERR "%s: can't get upstream IRQ %d\n", dev->name, dev->pci->irq);
|
| 789 | goto fail_irq;
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 790 | }
|
| 791 |
|
| 792 |
|
| 793 | // Start the DMA engine
|
| 794 | tmp = cx_read( sram_ch->dma_ctl );
|
| 795 | cx_set( sram_ch->dma_ctl, tmp | FLD_VID_RISC_EN );
|
| 796 |
|
| 797 | dev->_is_running = 1;
|
| 798 | dev->_is_first_frame = 1;
|
| 799 |
|
| 800 | return 0;
|
| 801 |
|
| 802 | fail_irq:
|
| 803 | cx25821_dev_unregister(dev);
|
| 804 | return err;
|
| 805 | }
|
| 806 |
|
| 807 |
|
| 808 | int cx25821_vidupstream_init_ch1(struct cx25821_dev *dev, int channel_select, int pixel_format)
|
| 809 | {
|
| 810 | struct sram_channel *sram_ch;
|
| 811 | u32 tmp;
|
| 812 | int retval = 0;
|
| 813 | int err = 0;
|
| 814 | int data_frame_size = 0;
|
| 815 | int risc_buffer_size = 0;
|
| 816 | int str_length = 0;
|
| 817 |
|
| 818 |
|
| 819 | if( dev->_is_running )
|
| 820 | {
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 821 | printk("Video Channel is still running so return!\n");
|
| 822 | return 0;
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 823 | }
|
| 824 |
|
| 825 |
|
| 826 | dev->_channel_upstream_select = channel_select;
|
| 827 | sram_ch = &dev->sram_channels[channel_select];
|
| 828 |
|
| 829 |
|
| 830 | INIT_WORK(&dev->_irq_work_entry, cx25821_vidups_handler);
|
| 831 | dev->_irq_queues = create_singlethread_workqueue("cx25821_workqueue");
|
| 832 |
|
| 833 | if(!dev->_irq_queues)
|
| 834 | {
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 835 | printk("cx25821: create_singlethread_workqueue() for Video FAILED!\n");
|
| 836 | return -ENOMEM;
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 837 | }
|
| 838 |
|
| 839 | // 656/VIP SRC Upstream Channel I & J and 7 - Host Bus Interface for channel A-C
|
| 840 | tmp = cx_read( VID_CH_MODE_SEL );
|
| 841 | cx_write( VID_CH_MODE_SEL, tmp | 0x1B0001FF);
|
| 842 |
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 843 |
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 844 | dev->_is_running = 0;
|
| 845 | dev->_frame_count = 0;
|
| 846 | dev->_file_status = RESET_STATUS;
|
| 847 | dev->_lines_count = dev->_isNTSC ? 480 : 576;
|
| 848 | dev->_pixel_format = pixel_format;
|
| 849 | dev->_line_size = (dev->_pixel_format == PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
|
| 850 | data_frame_size = dev->_isNTSC ? NTSC_DATA_BUF_SZ : PAL_DATA_BUF_SZ;
|
| 851 | risc_buffer_size = dev->_isNTSC ? NTSC_RISC_BUF_SIZE : PAL_RISC_BUF_SIZE;
|
| 852 |
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 853 |
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 854 | if( dev->input_filename )
|
| 855 | {
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 856 | str_length = strlen(dev->input_filename);
|
| 857 | dev->_filename = (char *) kmalloc(str_length + 1, GFP_KERNEL);
|
| 858 |
|
| 859 | if( !dev->_filename )
|
| 860 | goto error;
|
| 861 |
|
| 862 | memcpy(dev->_filename, dev->input_filename, str_length + 1);
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 863 | }
|
| 864 | else
|
| 865 | {
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 866 | str_length = strlen(dev->_defaultname);
|
| 867 | dev->_filename = (char *) kmalloc(str_length + 1, GFP_KERNEL);
|
| 868 |
|
| 869 | if( !dev->_filename )
|
| 870 | goto error;
|
| 871 |
|
| 872 | memcpy(dev->_filename, dev->_defaultname, str_length + 1);
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 873 | }
|
| 874 |
|
| 875 |
|
| 876 | //Default if filename is empty string
|
| 877 | if( strcmp(dev->input_filename,"") == 0)
|
| 878 | {
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 879 | if( dev->_isNTSC )
|
| 880 | {
|
| 881 | dev->_filename = (dev->_pixel_format == PIXEL_FRMT_411) ? "/root/vid411.yuv" : "/root/vidtest.yuv";
|
| 882 | }
|
| 883 | else
|
| 884 | {
|
| 885 | dev->_filename = (dev->_pixel_format == PIXEL_FRMT_411) ? "/root/pal411.yuv" : "/root/pal422.yuv";
|
| 886 | }
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 887 | }
|
| 888 |
|
| 889 | dev->_is_running = 0;
|
| 890 | dev->_frame_count = 0;
|
| 891 | dev->_file_status = RESET_STATUS;
|
| 892 | dev->_lines_count = dev->_isNTSC ? 480 : 576;
|
| 893 | dev->_pixel_format = pixel_format;
|
| 894 | dev->_line_size = (dev->_pixel_format == PIXEL_FRMT_422) ? (WIDTH_D1 * 2) : (WIDTH_D1 * 3) / 2;
|
| 895 |
|
| 896 | retval = cx25821_sram_channel_setup_upstream(dev, sram_ch, dev->_line_size, 0);
|
| 897 |
|
| 898 | /* setup fifo + format */
|
| 899 | cx25821_set_pixelengine(dev, sram_ch, dev->_pixel_format);
|
| 900 |
|
| 901 | dev->upstream_riscbuf_size = risc_buffer_size * 2;
|
| 902 | dev->upstream_databuf_size = data_frame_size * 2;
|
| 903 |
|
| 904 |
|
| 905 | //Allocating buffers and prepare RISC program
|
| 906 | retval = cx25821_upstream_buffer_prepare(dev, sram_ch, dev->_line_size);
|
| 907 | if (retval < 0)
|
| 908 | {
|
Mauro Carvalho Chehab | bb4c9a7 | 2009-09-13 11:25:45 -0300 | [diff] [blame^] | 909 | printk(KERN_ERR "%s: Failed to set up Video upstream buffers!\n", dev->name);
|
| 910 | goto error;
|
Mauro Carvalho Chehab | 02b20b0 | 2009-09-15 11:33:54 -0300 | [diff] [blame] | 911 | }
|
| 912 |
|
| 913 |
|
| 914 | cx25821_start_video_dma_upstream(dev, sram_ch);
|
| 915 |
|
| 916 | return 0;
|
| 917 |
|
| 918 | error:
|
| 919 | cx25821_dev_unregister(dev);
|
| 920 |
|
| 921 | return err;
|
| 922 | }
|
| 923 |
|