| /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ |
| /* |
| * Copyright (C) 2026 Amlogic, Inc. All rights reserved. |
| */ |
| |
| #ifndef __AMLOGIC_A9_PERIPHERALS_CLKC_H |
| #define __AMLOGIC_A9_PERIPHERALS_CLKC_H |
| |
| #define CLKID_SYS_AM_AXI 0 |
| #define CLKID_SYS_DOS 1 |
| #define CLKID_SYS_MIPI_DSI0 2 |
| #define CLKID_SYS_ETH_PHY 3 |
| #define CLKID_SYS_AMFC 4 |
| #define CLKID_SYS_MALI 5 |
| #define CLKID_SYS_NNA 6 |
| #define CLKID_SYS_ETH_AXI 7 |
| #define CLKID_SYS_DP_APB 8 |
| #define CLKID_SYS_EDPTX_APB 9 |
| #define CLKID_SYS_U3HSG 10 |
| #define CLKID_SYS_AUCPU 11 |
| #define CLKID_SYS_GLB 12 |
| #define CLKID_SYS_COMBO_DPHY_APB 13 |
| #define CLKID_SYS_HDMIRX_APB 14 |
| #define CLKID_SYS_HDMIRX_PCLK 15 |
| #define CLKID_SYS_MIPI_DSI0_PHY 16 |
| #define CLKID_SYS_CAN0 17 |
| #define CLKID_SYS_CAN1 18 |
| #define CLKID_SYS_SD_EMMC_A 19 |
| #define CLKID_SYS_SD_EMMC_B 20 |
| #define CLKID_SYS_SD_EMMC_C 21 |
| #define CLKID_SYS_SC 22 |
| #define CLKID_SYS_ACODEC 23 |
| #define CLKID_SYS_MIPI_ISP 24 |
| #define CLKID_SYS_MSR 25 |
| #define CLKID_SYS_AUDIO 26 |
| #define CLKID_SYS_MIPI_DSI1 27 |
| #define CLKID_SYS_MIPI_DSI1_PHY 28 |
| #define CLKID_SYS_ETH 29 |
| #define CLKID_SYS_ETH_1G_MAC 30 |
| #define CLKID_SYS_UART_A 31 |
| #define CLKID_SYS_UART_F 32 |
| #define CLKID_SYS_TS_A55 33 |
| #define CLKID_SYS_ETH_1G_AXI 34 |
| #define CLKID_SYS_TS_DOS 35 |
| #define CLKID_SYS_U3DRD_B 36 |
| #define CLKID_SYS_TS_CORE 37 |
| #define CLKID_SYS_TS_PLL 38 |
| #define CLKID_SYS_CSI_DIG_CLKIN 39 |
| #define CLKID_SYS_CVE 40 |
| #define CLKID_SYS_GE2D 41 |
| #define CLKID_SYS_SPISG 42 |
| #define CLKID_SYS_U2H 43 |
| #define CLKID_SYS_PCIE_MAC_A 44 |
| #define CLKID_SYS_U3DRD_A 45 |
| #define CLKID_SYS_U2DRD 46 |
| #define CLKID_SYS_PCIE_PHY 47 |
| #define CLKID_SYS_PCIE_MAC_B 48 |
| #define CLKID_SYS_PERIPH 49 |
| #define CLKID_SYS_PIO 50 |
| #define CLKID_SYS_I3C 51 |
| #define CLKID_SYS_I2C_M_E 52 |
| #define CLKID_SYS_I2C_M_F 53 |
| #define CLKID_SYS_HDMITX_APB 54 |
| #define CLKID_SYS_I2C_M_I 55 |
| #define CLKID_SYS_I2C_M_G 56 |
| #define CLKID_SYS_I2C_M_H 57 |
| #define CLKID_SYS_HDMI20_AES 58 |
| #define CLKID_SYS_CSI2_HOST 59 |
| #define CLKID_SYS_CSI2_ADAPT 60 |
| #define CLKID_SYS_DSPA 61 |
| #define CLKID_SYS_PP_DMA 62 |
| #define CLKID_SYS_PP_WRAPPER 63 |
| #define CLKID_SYS_VPU_INTR 64 |
| #define CLKID_SYS_CSI2_PHY 65 |
| #define CLKID_SYS_SARADC 66 |
| #define CLKID_SYS_PWM_J 67 |
| #define CLKID_SYS_PWM_I 68 |
| #define CLKID_SYS_PWM_H 69 |
| #define CLKID_SYS_PWM_N 70 |
| #define CLKID_SYS_PWM_M 71 |
| #define CLKID_SYS_PWM_L 72 |
| #define CLKID_SYS_PWM_K 73 |
| #define CLKID_SD_EMMC_A_SEL 74 |
| #define CLKID_SD_EMMC_A_DIV 75 |
| #define CLKID_SD_EMMC_A 76 |
| #define CLKID_SD_EMMC_B_SEL 77 |
| #define CLKID_SD_EMMC_B_DIV 78 |
| #define CLKID_SD_EMMC_B 79 |
| #define CLKID_SD_EMMC_C_SEL 80 |
| #define CLKID_SD_EMMC_C_DIV 81 |
| #define CLKID_SD_EMMC_C 82 |
| #define CLKID_PWM_H_SEL 83 |
| #define CLKID_PWM_H_DIV 84 |
| #define CLKID_PWM_H 85 |
| #define CLKID_PWM_I_SEL 86 |
| #define CLKID_PWM_I_DIV 87 |
| #define CLKID_PWM_I 88 |
| #define CLKID_PWM_J_SEL 89 |
| #define CLKID_PWM_J_DIV 90 |
| #define CLKID_PWM_J 91 |
| #define CLKID_PWM_K_SEL 92 |
| #define CLKID_PWM_K_DIV 93 |
| #define CLKID_PWM_K 94 |
| #define CLKID_PWM_L_SEL 95 |
| #define CLKID_PWM_L_DIV 96 |
| #define CLKID_PWM_L 97 |
| #define CLKID_PWM_M_SEL 98 |
| #define CLKID_PWM_M_DIV 99 |
| #define CLKID_PWM_M 100 |
| #define CLKID_PWM_N_SEL 101 |
| #define CLKID_PWM_N_DIV 102 |
| #define CLKID_PWM_N 103 |
| #define CLKID_SPISG0_SEL 104 |
| #define CLKID_SPISG0_DIV 105 |
| #define CLKID_SPISG0 106 |
| #define CLKID_SPISG1_SEL 107 |
| #define CLKID_SPISG1_DIV 108 |
| #define CLKID_SPISG1 109 |
| #define CLKID_SPISG2_SEL 110 |
| #define CLKID_SPISG2_DIV 111 |
| #define CLKID_SPISG2 112 |
| #define CLKID_SARADC_SEL 113 |
| #define CLKID_SARADC_DIV 114 |
| #define CLKID_SARADC 115 |
| #define CLKID_AMFC_SEL 116 |
| #define CLKID_AMFC_DIV 117 |
| #define CLKID_AMFC 118 |
| #define CLKID_NNA_SEL 119 |
| #define CLKID_NNA_DIV 120 |
| #define CLKID_NNA 121 |
| #define CLKID_USB_250M_SEL 122 |
| #define CLKID_USB_250M_DIV 123 |
| #define CLKID_USB_250M 124 |
| #define CLKID_USB_48M_PRE_SEL 125 |
| #define CLKID_USB_48M_PRE_DIV 126 |
| #define CLKID_USB_48M_PRE 127 |
| #define CLKID_PCIE0_TL_SEL 128 |
| #define CLKID_PCIE0_TL_DIV 129 |
| #define CLKID_PCIE0_TL 130 |
| #define CLKID_PCIE1_TL_SEL 131 |
| #define CLKID_PCIE1_TL_DIV 132 |
| #define CLKID_PCIE1_TL 133 |
| #define CLKID_CMPR_SEL 134 |
| #define CLKID_CMPR_DIV 135 |
| #define CLKID_CMPR 136 |
| #define CLKID_DEWARPA_SEL 137 |
| #define CLKID_DEWARPA_DIV 138 |
| #define CLKID_DEWARPA 139 |
| #define CLKID_SC_PRE_SEL 140 |
| #define CLKID_SC_PRE_DIV 141 |
| #define CLKID_SC_PRE 142 |
| #define CLKID_SC 143 |
| #define CLKID_DPTX_APB2_SEL 144 |
| #define CLKID_DPTX_APB2_DIV 145 |
| #define CLKID_DPTX_APB2 146 |
| #define CLKID_DPTX_AUD_SEL 147 |
| #define CLKID_DPTX_AUD_DIV 148 |
| #define CLKID_DPTX_AUD 149 |
| #define CLKID_ISP_SEL 150 |
| #define CLKID_ISP_DIV 151 |
| #define CLKID_ISP 152 |
| #define CLKID_CVE_SEL 153 |
| #define CLKID_CVE_DIV 154 |
| #define CLKID_CVE 155 |
| #define CLKID_VGE_SEL 156 |
| #define CLKID_VGE_DIV 157 |
| #define CLKID_VGE 158 |
| #define CLKID_PP_SEL 159 |
| #define CLKID_PP_DIV 160 |
| #define CLKID_PP 161 |
| #define CLKID_GLB_SEL 162 |
| #define CLKID_GLB_DIV 163 |
| #define CLKID_GLB 164 |
| #define CLKID_USB_48M_DUALDIV_IN 165 |
| #define CLKID_USB_48M_DUALDIV_DIV 166 |
| #define CLKID_USB_48M_DUALDIV_SEL 167 |
| #define CLKID_USB_48M_DUALDIV 168 |
| #define CLKID_USB_48M 169 |
| #define CLKID_CAN0_PE_SEL 170 |
| #define CLKID_CAN0_PE_DIV 171 |
| #define CLKID_CAN0_PE 172 |
| #define CLKID_CAN1_PE_SEL 173 |
| #define CLKID_CAN1_PE_DIV 174 |
| #define CLKID_CAN1_PE 175 |
| #define CLKID_CAN0_FILTER_SEL 176 |
| #define CLKID_CAN0_FILTER_DIV 177 |
| #define CLKID_CAN0_FILTER 178 |
| #define CLKID_CAN1_FILTER_SEL 179 |
| #define CLKID_CAN1_FILTER_DIV 180 |
| #define CLKID_CAN1_FILTER 181 |
| #define CLKID_I3C_SEL 182 |
| #define CLKID_I3C_DIV 183 |
| #define CLKID_I3C 184 |
| #define CLKID_TS_DIV 185 |
| #define CLKID_TS 186 |
| #define CLKID_ETH_125M_DIV 187 |
| #define CLKID_ETH_125M 188 |
| #define CLKID_ETH_RMII_SEL 189 |
| #define CLKID_ETH_RMII_DIV 190 |
| #define CLKID_ETH_RMII 191 |
| #define CLKID_GEN_SEL 192 |
| #define CLKID_GEN_DIV 193 |
| #define CLKID_GEN 194 |
| #define CLKID_CLK24M_IN 195 |
| #define CLKID_CLK12_24M 196 |
| #define CLKID_MALI_0_SEL 197 |
| #define CLKID_MALI_0_DIV 198 |
| #define CLKID_MALI_0 199 |
| #define CLKID_MALI_1_SEL 200 |
| #define CLKID_MALI_1_DIV 201 |
| #define CLKID_MALI_1 202 |
| #define CLKID_MALI 203 |
| #define CLKID_MALI_STACK_0_SEL 204 |
| #define CLKID_MALI_STACK_0_DIV 205 |
| #define CLKID_MALI_STACK_0 206 |
| #define CLKID_MALI_STACK_1_SEL 207 |
| #define CLKID_MALI_STACK_1_DIV 208 |
| #define CLKID_MALI_STACK_1 209 |
| #define CLKID_MALI_STACK 210 |
| #define CLKID_DSPA_0_SEL 211 |
| #define CLKID_DSPA_0_DIV 212 |
| #define CLKID_DSPA_0 213 |
| #define CLKID_DSPA_1_SEL 214 |
| #define CLKID_DSPA_1_DIV 215 |
| #define CLKID_DSPA_1 216 |
| #define CLKID_DSPA 217 |
| #define CLKID_HEVCF_0_SEL 218 |
| #define CLKID_HEVCF_0_DIV 219 |
| #define CLKID_HEVCF_0 220 |
| #define CLKID_HEVCF_1_SEL 221 |
| #define CLKID_HEVCF_1_DIV 222 |
| #define CLKID_HEVCF_1 223 |
| #define CLKID_HEVCF 224 |
| #define CLKID_HCODEC_0_SEL 225 |
| #define CLKID_HCODEC_0_DIV 226 |
| #define CLKID_HCODEC_0 227 |
| #define CLKID_HCODEC_1_SEL 228 |
| #define CLKID_HCODEC_1_DIV 229 |
| #define CLKID_HCODEC_1 230 |
| #define CLKID_HCODEC 231 |
| #define CLKID_VPU_0_SEL 232 |
| #define CLKID_VPU_0_DIV 233 |
| #define CLKID_VPU_0 234 |
| #define CLKID_VPU_1_SEL 235 |
| #define CLKID_VPU_1_DIV 236 |
| #define CLKID_VPU_1 237 |
| #define CLKID_VPU 238 |
| #define CLKID_VAPB_0_SEL 239 |
| #define CLKID_VAPB_0_DIV 240 |
| #define CLKID_VAPB_0 241 |
| #define CLKID_VAPB_1_SEL 242 |
| #define CLKID_VAPB_1_DIV 243 |
| #define CLKID_VAPB_1 244 |
| #define CLKID_VAPB 245 |
| #define CLKID_GE2D 246 |
| #define CLKID_VPU_CLKB_TMP_SEL 247 |
| #define CLKID_VPU_CLKB_TMP_DIV 248 |
| #define CLKID_VPU_CLKB_TMP 249 |
| #define CLKID_VPU_CLKB_DIV 250 |
| #define CLKID_VPU_CLKB 251 |
| #define CLKID_HDMITX_SYS_SEL 252 |
| #define CLKID_HDMITX_SYS_DIV 253 |
| #define CLKID_HDMITX_SYS 254 |
| #define CLKID_HDMITX_PRIF_SEL 255 |
| #define CLKID_HDMITX_PRIF_DIV 256 |
| #define CLKID_HDMITX_PRIF 257 |
| #define CLKID_HDMITX_200M_SEL 258 |
| #define CLKID_HDMITX_200M_DIV 259 |
| #define CLKID_HDMITX_200M 260 |
| #define CLKID_HDMITX_AUD_SEL 261 |
| #define CLKID_HDMITX_AUD_DIV 262 |
| #define CLKID_HDMITX_AUD 263 |
| #define CLKID_HDMIRX_5M_SEL 264 |
| #define CLKID_HDMIRX_5M_DIV 265 |
| #define CLKID_HDMIRX_5M 266 |
| #define CLKID_HDMIRX_2M_SEL 267 |
| #define CLKID_HDMIRX_2M_DIV 268 |
| #define CLKID_HDMIRX_2M 269 |
| #define CLKID_HDMIRX_CFG_SEL 270 |
| #define CLKID_HDMIRX_CFG_DIV 271 |
| #define CLKID_HDMIRX_CFG 272 |
| #define CLKID_HDMIRX_HDCP2X_SEL 273 |
| #define CLKID_HDMIRX_HDCP2X_DIV 274 |
| #define CLKID_HDMIRX_HDCP2X 275 |
| #define CLKID_HDMIRX_ACR_REF_SEL 276 |
| #define CLKID_HDMIRX_ACR_REF_DIV 277 |
| #define CLKID_HDMIRX_ACR_REF 278 |
| #define CLKID_HDMIRX_METER_SEL 279 |
| #define CLKID_HDMIRX_METER_DIV 280 |
| #define CLKID_HDMIRX_METER 281 |
| #define CLKID_VID_LOCK_SEL 282 |
| #define CLKID_VID_LOCK_DIV 283 |
| #define CLKID_VID_LOCK 284 |
| #define CLKID_VDIN_MEAS_SEL 285 |
| #define CLKID_VDIN_MEAS_DIV 286 |
| #define CLKID_VDIN_MEAS 287 |
| #define CLKID_VID_PLL_DIV 288 |
| #define CLKID_VID_PLL_SEL 289 |
| #define CLKID_VID_PLL 290 |
| #define CLKID_VID_PLL_VCLK 291 |
| #define CLKID_VCLK0_SEL 292 |
| #define CLKID_VCLK0_IN 293 |
| #define CLKID_VCLK0_DIV 294 |
| #define CLKID_VCLK0 295 |
| #define CLKID_VCLK0_DIV1_EN 296 |
| #define CLKID_VCLK0_DIV2_EN 297 |
| #define CLKID_VCLK0_DIV2 298 |
| #define CLKID_VCLK0_DIV4_EN 299 |
| #define CLKID_VCLK0_DIV4 300 |
| #define CLKID_VCLK0_DIV6_EN 301 |
| #define CLKID_VCLK0_DIV6 302 |
| #define CLKID_VCLK0_DIV12_EN 303 |
| #define CLKID_VCLK0_DIV12 304 |
| #define CLKID_VCLK1_SEL 305 |
| #define CLKID_VCLK1_IN 306 |
| #define CLKID_VCLK1_DIV 307 |
| #define CLKID_VCLK1 308 |
| #define CLKID_VCLK1_DIV1_EN 309 |
| #define CLKID_VCLK1_DIV2_EN 310 |
| #define CLKID_VCLK1_DIV2 311 |
| #define CLKID_VCLK1_DIV4_EN 312 |
| #define CLKID_VCLK1_DIV4 313 |
| #define CLKID_VCLK1_DIV6_EN 314 |
| #define CLKID_VCLK1_DIV6 315 |
| #define CLKID_VCLK1_DIV12_EN 316 |
| #define CLKID_VCLK1_DIV12 317 |
| #define CLKID_VDAC_SEL 318 |
| #define CLKID_VDAC 319 |
| #define CLKID_ENCODER0_SEL 320 |
| #define CLKID_ENCODER0 321 |
| #define CLKID_ENCODER1_SEL 322 |
| #define CLKID_ENCODER1 323 |
| #define CLKID_HDMITX0_PIXEL_SEL 324 |
| #define CLKID_HDMITX0_PIXEL 325 |
| #define CLKID_HDMITX0_FE_SEL 326 |
| #define CLKID_HDMITX0_FE 327 |
| #define CLKID_HDMITX1_PIXEL_SEL 328 |
| #define CLKID_HDMITX1_PIXEL 329 |
| #define CLKID_HDMITX1_FE_SEL 330 |
| #define CLKID_HDMITX1_FE 331 |
| #define CLKID_CSI_PHY_SEL 332 |
| #define CLKID_CSI_PHY_DIV 333 |
| #define CLKID_CSI_PHY 334 |
| #define CLKID_DSI0_MEAS_SEL 335 |
| #define CLKID_DSI0_MEAS_DIV 336 |
| #define CLKID_DSI0_MEAS 337 |
| #define CLKID_DSI1_MEAS_SEL 338 |
| #define CLKID_DSI1_MEAS_DIV 339 |
| #define CLKID_DSI1_MEAS 340 |
| |
| #endif /* __AMLOGIC_A9_PERIPHERALS_CLKC_H */ |
