Documentation/devicetree/bindings/clock/mediatek,mt8173-mfgtop.yaml

# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---

$id: http://devicetree.org/schemas/clock/mediatek,mt8173-mfgtop.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MediaTek MT8173 MFG TOP controller

maintainers:
  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

description:
  The MFG TOP glue layer controls various signals going to the MFG (GPU)
  block on the MT8173.

properties:
  compatible:
    const: mediatek,mt8173-mfgtop

  reg:
    maxItems: 1

  clocks:
    maxItems: 4

  clock-names:
    items:
      - const: sys
      - const: mem
      - const: core
      - const: clk26m

  power-domains:
    maxItems: 1

  '#clock-cells':
    const: 1

  '#power-domain-cells':
    const: 0

required:
  - compatible
  - reg
  - clocks
  - clock-names
  - power-domains
  - '#clock-cells'
  - '#power-domain-cells'

additionalProperties: false

examples:
  - |
        #include <dt-bindings/clock/mt8173-clk.h>
        #include <dt-bindings/power/mt8173-power.h>

        clock-controller@13fff000 {
            compatible = "mediatek,mt8173-mfgtop";
            reg = <0x13fff000 0x1000>;
            clocks = <&topckgen CLK_TOP_AXI_MFG_IN_SEL>,
                     <&topckgen CLK_TOP_MEM_MFG_IN_SEL>,
                     <&topckgen CLK_TOP_MFG_SEL>,
                     <&clk26m>;
            clock-names = "sys", "mem", "core", "clk26m";
            power-domains = <&spm MT8173_POWER_DOMAIN_MFG>;
            #clock-cells = <1>;
            #power-domain-cells = <0>;
        };