| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Copyright (c) 2016 Andreas Färber |
| * |
| * Copyright (c) 2016 BayLibre, SAS. |
| * Author: Neil Armstrong <narmstrong@baylibre.com> |
| * |
| * Copyright (c) 2016 Endless Computers, Inc. |
| * Author: Carlo Caione <carlo@endlessm.com> |
| */ |
| |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| |
| / { |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| /* 16 MiB reserved for Hardware ROM Firmware */ |
| hwrom_reserved: hwrom@0 { |
| reg = <0x0 0x0 0x0 0x1000000>; |
| no-map; |
| }; |
| |
| /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ |
| secmon_reserved: secmon@10000000 { |
| reg = <0x0 0x10000000 0x0 0x200000>; |
| no-map; |
| }; |
| |
| linux,cma { |
| compatible = "shared-dma-pool"; |
| reusable; |
| size = <0x0 0xbc00000>; |
| alignment = <0x0 0x400000>; |
| linux,cma-default; |
| }; |
| }; |
| |
| cpus { |
| #address-cells = <0x2>; |
| #size-cells = <0x0>; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| reg = <0x0 0x0>; |
| enable-method = "psci"; |
| next-level-cache = <&l2>; |
| clocks = <&scpi_dvfs 0>; |
| }; |
| |
| cpu1: cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| reg = <0x0 0x1>; |
| enable-method = "psci"; |
| next-level-cache = <&l2>; |
| clocks = <&scpi_dvfs 0>; |
| }; |
| |
| cpu2: cpu@2 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| reg = <0x0 0x2>; |
| enable-method = "psci"; |
| next-level-cache = <&l2>; |
| clocks = <&scpi_dvfs 0>; |
| }; |
| |
| cpu3: cpu@3 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| reg = <0x0 0x3>; |
| enable-method = "psci"; |
| next-level-cache = <&l2>; |
| clocks = <&scpi_dvfs 0>; |
| }; |
| |
| l2: l2-cache0 { |
| compatible = "cache"; |
| }; |
| }; |
| |
| arm-pmu { |
| compatible = "arm,cortex-a53-pmu"; |
| interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; |
| }; |
| |
| psci { |
| compatible = "arm,psci-0.2"; |
| method = "smc"; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 |
| (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 14 |
| (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 11 |
| (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 10 |
| (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; |
| }; |
| |
| xtal: xtal-clk { |
| compatible = "fixed-clock"; |
| clock-frequency = <24000000>; |
| clock-output-names = "xtal"; |
| #clock-cells = <0>; |
| }; |
| |
| firmware { |
| sm: secure-monitor { |
| compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm"; |
| }; |
| }; |
| |
| efuse: efuse { |
| compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| read-only; |
| |
| sn: sn@14 { |
| reg = <0x14 0x10>; |
| }; |
| |
| eth_mac: eth_mac@34 { |
| reg = <0x34 0x10>; |
| }; |
| |
| bid: bid@46 { |
| reg = <0x46 0x30>; |
| }; |
| }; |
| |
| scpi { |
| compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0"; |
| mboxes = <&mailbox 1 &mailbox 2>; |
| shmem = <&cpu_scp_lpri &cpu_scp_hpri>; |
| |
| scpi_clocks: clocks { |
| compatible = "arm,scpi-clocks"; |
| |
| scpi_dvfs: scpi_clocks@0 { |
| compatible = "arm,scpi-dvfs-clocks"; |
| #clock-cells = <1>; |
| clock-indices = <0>; |
| clock-output-names = "vcpu"; |
| }; |
| }; |
| |
| scpi_sensors: sensors { |
| compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors"; |
| #thermal-sensor-cells = <1>; |
| }; |
| }; |
| |
| soc { |
| compatible = "simple-bus"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| cbus: bus@c1100000 { |
| compatible = "simple-bus"; |
| reg = <0x0 0xc1100000 0x0 0x100000>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>; |
| |
| gpio_intc: interrupt-controller@9880 { |
| compatible = "amlogic,meson-gpio-intc"; |
| reg = <0x0 0x9880 0x0 0x10>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; |
| status = "disabled"; |
| }; |
| |
| reset: reset-controller@4404 { |
| compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset"; |
| reg = <0x0 0x04404 0x0 0x9c>; |
| #reset-cells = <1>; |
| }; |
| |
| uart_A: serial@84c0 { |
| compatible = "amlogic,meson-gx-uart"; |
| reg = <0x0 0x84c0 0x0 0x18>; |
| interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; |
| status = "disabled"; |
| }; |
| |
| uart_B: serial@84dc { |
| compatible = "amlogic,meson-gx-uart"; |
| reg = <0x0 0x84dc 0x0 0x18>; |
| interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; |
| status = "disabled"; |
| }; |
| |
| i2c_A: i2c@8500 { |
| compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c"; |
| reg = <0x0 0x08500 0x0 0x20>; |
| interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| pwm_ab: pwm@8550 { |
| compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; |
| reg = <0x0 0x08550 0x0 0x10>; |
| #pwm-cells = <3>; |
| status = "disabled"; |
| }; |
| |
| pwm_cd: pwm@8650 { |
| compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; |
| reg = <0x0 0x08650 0x0 0x10>; |
| #pwm-cells = <3>; |
| status = "disabled"; |
| }; |
| |
| saradc: adc@8680 { |
| compatible = "amlogic,meson-saradc"; |
| reg = <0x0 0x8680 0x0 0x34>; |
| #io-channel-cells = <1>; |
| interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; |
| status = "disabled"; |
| }; |
| |
| pwm_ef: pwm@86c0 { |
| compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm"; |
| reg = <0x0 0x086c0 0x0 0x10>; |
| #pwm-cells = <3>; |
| status = "disabled"; |
| }; |
| |
| uart_C: serial@8700 { |
| compatible = "amlogic,meson-gx-uart"; |
| reg = <0x0 0x8700 0x0 0x18>; |
| interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; |
| status = "disabled"; |
| }; |
| |
| i2c_B: i2c@87c0 { |
| compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c"; |
| reg = <0x0 0x087c0 0x0 0x20>; |
| interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c_C: i2c@87e0 { |
| compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c"; |
| reg = <0x0 0x087e0 0x0 0x20>; |
| interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spicc: spi@8d80 { |
| compatible = "amlogic,meson-gx-spicc"; |
| reg = <0x0 0x08d80 0x0 0x80>; |
| interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spifc: spi@8c80 { |
| compatible = "amlogic,meson-gx-spifc", "amlogic,meson-gxbb-spifc"; |
| reg = <0x0 0x08c80 0x0 0x80>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| watchdog@98d0 { |
| compatible = "amlogic,meson-gx-wdt", "amlogic,meson-gxbb-wdt"; |
| reg = <0x0 0x098d0 0x0 0x10>; |
| clocks = <&xtal>; |
| }; |
| }; |
| |
| gic: interrupt-controller@c4301000 { |
| compatible = "arm,gic-400"; |
| reg = <0x0 0xc4301000 0 0x1000>, |
| <0x0 0xc4302000 0 0x2000>, |
| <0x0 0xc4304000 0 0x2000>, |
| <0x0 0xc4306000 0 0x2000>; |
| interrupt-controller; |
| interrupts = <GIC_PPI 9 |
| (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; |
| #interrupt-cells = <3>; |
| #address-cells = <0>; |
| }; |
| |
| sram: sram@c8000000 { |
| compatible = "amlogic,meson-gx-sram", "amlogic,meson-gxbb-sram", "mmio-sram"; |
| reg = <0x0 0xc8000000 0x0 0x14000>; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0x0 0xc8000000 0x14000>; |
| |
| cpu_scp_lpri: scp-shmem@0 { |
| compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem"; |
| reg = <0x13000 0x400>; |
| }; |
| |
| cpu_scp_hpri: scp-shmem@200 { |
| compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem"; |
| reg = <0x13400 0x400>; |
| }; |
| }; |
| |
| aobus: bus@c8100000 { |
| compatible = "simple-bus"; |
| reg = <0x0 0xc8100000 0x0 0x100000>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>; |
| |
| sysctrl_AO: sys-ctrl@0 { |
| compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd"; |
| reg = <0x0 0x0 0x0 0x100>; |
| |
| pwrc_vpu: power-controller-vpu { |
| compatible = "amlogic,meson-gx-pwrc-vpu"; |
| #power-domain-cells = <0>; |
| amlogic,hhi-sysctrl = <&sysctrl>; |
| }; |
| |
| clkc_AO: clock-controller { |
| compatible = "amlogic,meson-gx-aoclkc"; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| }; |
| |
| cec_AO: cec@100 { |
| compatible = "amlogic,meson-gx-ao-cec"; |
| reg = <0x0 0x00100 0x0 0x14>; |
| interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; |
| }; |
| |
| sec_AO: ao-secure@140 { |
| compatible = "amlogic,meson-gx-ao-secure", "syscon"; |
| reg = <0x0 0x140 0x0 0x140>; |
| amlogic,has-chip-id; |
| }; |
| |
| uart_AO: serial@4c0 { |
| compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; |
| reg = <0x0 0x004c0 0x0 0x18>; |
| interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; |
| status = "disabled"; |
| }; |
| |
| uart_AO_B: serial@4e0 { |
| compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; |
| reg = <0x0 0x004e0 0x0 0x18>; |
| interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; |
| status = "disabled"; |
| }; |
| |
| i2c_AO: i2c@500 { |
| compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c"; |
| reg = <0x0 0x500 0x0 0x20>; |
| interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| pwm_AO_ab: pwm@550 { |
| compatible = "amlogic,meson-gx-ao-pwm", "amlogic,meson-gxbb-ao-pwm"; |
| reg = <0x0 0x00550 0x0 0x10>; |
| #pwm-cells = <3>; |
| status = "disabled"; |
| }; |
| |
| ir: ir@580 { |
| compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir"; |
| reg = <0x0 0x00580 0x0 0x40>; |
| interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; |
| status = "disabled"; |
| }; |
| }; |
| |
| periphs: periphs@c8834000 { |
| compatible = "simple-bus"; |
| reg = <0x0 0xc8834000 0x0 0x2000>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>; |
| |
| hwrng: rng { |
| compatible = "amlogic,meson-rng"; |
| reg = <0x0 0x0 0x0 0x4>; |
| }; |
| }; |
| |
| hiubus: bus@c883c000 { |
| compatible = "simple-bus"; |
| reg = <0x0 0xc883c000 0x0 0x2000>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>; |
| |
| sysctrl: system-controller@0 { |
| compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd"; |
| reg = <0 0 0 0x400>; |
| }; |
| |
| mailbox: mailbox@404 { |
| compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; |
| reg = <0 0x404 0 0x4c>; |
| interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; |
| #mbox-cells = <1>; |
| }; |
| }; |
| |
| ethmac: ethernet@c9410000 { |
| compatible = "amlogic,meson-gx-dwmac", "amlogic,meson-gxbb-dwmac", "snps,dwmac"; |
| reg = <0x0 0xc9410000 0x0 0x10000 |
| 0x0 0xc8834540 0x0 0x4>; |
| interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "macirq"; |
| status = "disabled"; |
| }; |
| |
| apb: apb@d0000000 { |
| compatible = "simple-bus"; |
| reg = <0x0 0xd0000000 0x0 0x200000>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>; |
| |
| sd_emmc_a: mmc@70000 { |
| compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; |
| reg = <0x0 0x70000 0x0 0x2000>; |
| interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>; |
| status = "disabled"; |
| }; |
| |
| sd_emmc_b: mmc@72000 { |
| compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; |
| reg = <0x0 0x72000 0x0 0x2000>; |
| interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>; |
| status = "disabled"; |
| }; |
| |
| sd_emmc_c: mmc@74000 { |
| compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc"; |
| reg = <0x0 0x74000 0x0 0x2000>; |
| interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>; |
| status = "disabled"; |
| }; |
| }; |
| |
| vpu: vpu@d0100000 { |
| compatible = "amlogic,meson-gx-vpu"; |
| reg = <0x0 0xd0100000 0x0 0x100000>, |
| <0x0 0xc883c000 0x0 0x1000>, |
| <0x0 0xc8838000 0x0 0x1000>; |
| reg-names = "vpu", "hhi", "dmc"; |
| interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| /* CVBS VDAC output port */ |
| cvbs_vdac_port: port@0 { |
| reg = <0>; |
| }; |
| |
| /* HDMI-TX output port */ |
| hdmi_tx_port: port@1 { |
| reg = <1>; |
| |
| hdmi_tx_out: endpoint { |
| remote-endpoint = <&hdmi_tx_in>; |
| }; |
| }; |
| }; |
| |
| hdmi_tx: hdmi-tx@c883a000 { |
| compatible = "amlogic,meson-gx-dw-hdmi"; |
| reg = <0x0 0xc883a000 0x0 0x1c>; |
| interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| |
| /* VPU VENC Input */ |
| hdmi_tx_venc_port: port@0 { |
| reg = <0>; |
| |
| hdmi_tx_in: endpoint { |
| remote-endpoint = <&hdmi_tx_out>; |
| }; |
| }; |
| |
| /* TMDS Output */ |
| hdmi_tx_tmds_port: port@1 { |
| reg = <1>; |
| }; |
| }; |
| }; |
| }; |
