blob: 13e91074308aeaf51fa3b69ec498655c19f1e5c2 [file] [log] [blame]
Krzysztof Kozlowski28a196f2017-12-25 20:54:33 +01001// SPDX-License-Identifier: GPL-2.0
2//
3// Copyright (c) 2011 Samsung Electronics Co., Ltd.
4// http://www.samsung.com
5//
6// Copyright 2008 Openmoko, Inc.
7// Copyright 2008 Simtec Electronics
8// Ben Dooks <ben@simtec.co.uk>
9// http://armlinux.simtec.co.uk/
10//
11// Common Codes for S3C64XX machines
Kukjin Kimb024043b2011-12-22 23:27:42 +010012
Tomasz Figac836c902013-08-26 02:37:34 +090013/*
14 * NOTE: Code in this file is not used when booting with Device Tree support.
15 */
16
Kukjin Kimb024043b2011-12-22 23:27:42 +010017#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/module.h>
20#include <linux/interrupt.h>
21#include <linux/ioport.h>
Kukjin Kimb024043b2011-12-22 23:27:42 +010022#include <linux/serial_core.h>
Tushar Behera334a1c72014-02-14 10:32:45 +090023#include <linux/serial_s3c.h>
Kukjin Kimb024043b2011-12-22 23:27:42 +010024#include <linux/platform_device.h>
Robin Holt7b6d8642013-07-08 16:01:40 -070025#include <linux/reboot.h>
Kukjin Kimb024043b2011-12-22 23:27:42 +010026#include <linux/io.h>
27#include <linux/dma-mapping.h>
28#include <linux/irq.h>
29#include <linux/gpio.h>
Rob Herring9e47b8b2013-01-07 09:45:59 -060030#include <linux/irqchip/arm-vic.h>
Tomasz Figa1c161fd2013-04-12 21:17:22 +020031#include <clocksource/samsung_pwm.h>
Kukjin Kimb024043b2011-12-22 23:27:42 +010032
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
David Howells9f97da72012-03-28 18:30:01 +010035#include <asm/system_misc.h>
Kukjin Kimb024043b2011-12-22 23:27:42 +010036
37#include <mach/map.h>
Arnd Bergmannba279042015-02-27 22:06:58 +010038#include <mach/irqs.h>
Kukjin Kimb024043b2011-12-22 23:27:42 +010039#include <mach/hardware.h>
40#include <mach/regs-gpio.h>
Linus Walleijb0161ca2014-01-14 14:24:24 +010041#include <mach/gpio-samsung.h>
Kukjin Kimb024043b2011-12-22 23:27:42 +010042
43#include <plat/cpu.h>
Kukjin Kimb024043b2011-12-22 23:27:42 +010044#include <plat/devs.h>
45#include <plat/pm.h>
46#include <plat/gpio-cfg.h>
Tomasz Figa1c161fd2013-04-12 21:17:22 +020047#include <plat/pwm-core.h>
Kukjin Kimb024043b2011-12-22 23:27:42 +010048#include <plat/regs-irqtype.h>
Kukjin Kimb024043b2011-12-22 23:27:42 +010049
50#include "common.h"
Kukjin Kim876ba9b2015-07-30 02:00:38 +090051#include "irq-uart.h"
Kukjin Kim96bc0242015-07-30 02:00:52 +090052#include "watchdog-reset.h"
Kukjin Kimb024043b2011-12-22 23:27:42 +010053
Tomasz Figab69f4602013-08-26 02:00:38 +090054/* External clock frequency */
Krzysztof Kozlowski552146b2016-12-10 15:47:35 +020055static unsigned long xtal_f __ro_after_init = 12000000;
56static unsigned long xusbxti_f __ro_after_init = 48000000;
Tomasz Figab69f4602013-08-26 02:00:38 +090057
58void __init s3c64xx_set_xtal_freq(unsigned long freq)
59{
60 xtal_f = freq;
61}
62
63void __init s3c64xx_set_xusbxti_freq(unsigned long freq)
64{
65 xusbxti_f = freq;
66}
67
Kukjin Kimb024043b2011-12-22 23:27:42 +010068/* uart registration process */
69
Mark Brownb7c97052012-01-27 14:41:20 +090070static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
Kukjin Kimb024043b2011-12-22 23:27:42 +010071{
72 s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
73}
74
75/* table of supported CPUs */
76
77static const char name_s3c6400[] = "S3C6400";
78static const char name_s3c6410[] = "S3C6410";
79
80static struct cpu_table cpu_ids[] __initdata = {
81 {
82 .idcode = S3C6400_CPU_ID,
83 .idmask = S3C64XX_CPU_MASK,
84 .map_io = s3c6400_map_io,
Kukjin Kimb024043b2011-12-22 23:27:42 +010085 .init_uarts = s3c64xx_init_uarts,
86 .init = s3c6400_init,
87 .name = name_s3c6400,
88 }, {
89 .idcode = S3C6410_CPU_ID,
90 .idmask = S3C64XX_CPU_MASK,
91 .map_io = s3c6410_map_io,
Kukjin Kimb024043b2011-12-22 23:27:42 +010092 .init_uarts = s3c64xx_init_uarts,
93 .init = s3c6410_init,
94 .name = name_s3c6410,
95 },
96};
97
98/* minimal IO mapping */
99
100/* see notes on uart map in arch/arm/mach-s3c64xx/include/mach/debug-macro.S */
101#define UART_OFFS (S3C_PA_UART & 0xfffff)
102
103static struct map_desc s3c_iodesc[] __initdata = {
104 {
105 .virtual = (unsigned long)S3C_VA_SYS,
106 .pfn = __phys_to_pfn(S3C64XX_PA_SYSCON),
107 .length = SZ_4K,
108 .type = MT_DEVICE,
109 }, {
110 .virtual = (unsigned long)S3C_VA_MEM,
111 .pfn = __phys_to_pfn(S3C64XX_PA_SROM),
112 .length = SZ_4K,
113 .type = MT_DEVICE,
114 }, {
115 .virtual = (unsigned long)(S3C_VA_UART + UART_OFFS),
116 .pfn = __phys_to_pfn(S3C_PA_UART),
117 .length = SZ_4K,
118 .type = MT_DEVICE,
119 }, {
120 .virtual = (unsigned long)VA_VIC0,
121 .pfn = __phys_to_pfn(S3C64XX_PA_VIC0),
122 .length = SZ_16K,
123 .type = MT_DEVICE,
124 }, {
125 .virtual = (unsigned long)VA_VIC1,
126 .pfn = __phys_to_pfn(S3C64XX_PA_VIC1),
127 .length = SZ_16K,
128 .type = MT_DEVICE,
129 }, {
130 .virtual = (unsigned long)S3C_VA_TIMER,
131 .pfn = __phys_to_pfn(S3C_PA_TIMER),
132 .length = SZ_16K,
133 .type = MT_DEVICE,
134 }, {
135 .virtual = (unsigned long)S3C64XX_VA_GPIO,
136 .pfn = __phys_to_pfn(S3C64XX_PA_GPIO),
137 .length = SZ_4K,
138 .type = MT_DEVICE,
139 }, {
140 .virtual = (unsigned long)S3C64XX_VA_MODEM,
141 .pfn = __phys_to_pfn(S3C64XX_PA_MODEM),
142 .length = SZ_4K,
143 .type = MT_DEVICE,
144 }, {
145 .virtual = (unsigned long)S3C_VA_WATCHDOG,
146 .pfn = __phys_to_pfn(S3C64XX_PA_WATCHDOG),
147 .length = SZ_4K,
148 .type = MT_DEVICE,
149 }, {
150 .virtual = (unsigned long)S3C_VA_USB_HSPHY,
151 .pfn = __phys_to_pfn(S3C64XX_PA_USB_HSPHY),
152 .length = SZ_1K,
153 .type = MT_DEVICE,
154 },
155};
156
Linus Torvalds7affca32012-01-07 12:03:30 -0800157static struct bus_type s3c64xx_subsys = {
158 .name = "s3c64xx-core",
159 .dev_name = "s3c64xx-core",
Kukjin Kimb024043b2011-12-22 23:27:42 +0100160};
161
Linus Torvalds7affca32012-01-07 12:03:30 -0800162static struct device s3c64xx_dev = {
163 .bus = &s3c64xx_subsys,
Kukjin Kimb024043b2011-12-22 23:27:42 +0100164};
165
Tomasz Figa1c161fd2013-04-12 21:17:22 +0200166static struct samsung_pwm_variant s3c64xx_pwm_variant = {
167 .bits = 32,
168 .div_base = 0,
169 .has_tint_cstat = true,
170 .tclk_mask = (1 << 7) | (1 << 6) | (1 << 5),
171};
172
Tomasz Figa42805062013-04-28 02:25:01 +0200173void __init samsung_set_timer_source(unsigned int event, unsigned int source)
174{
175 s3c64xx_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
176 s3c64xx_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
177}
178
179void __init samsung_timer_init(void)
180{
181 unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
182 IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
183 IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
184 };
185
186 samsung_pwm_clocksource_init(S3C_VA_TIMER,
187 timer_irqs, &s3c64xx_pwm_variant);
188}
189
Kukjin Kimb024043b2011-12-22 23:27:42 +0100190/* read cpu identification code */
191
192void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
193{
194 /* initialise the io descriptors we need for initialisation */
195 iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
196 iotable_init(mach_desc, size);
Kukjin Kimb024043b2011-12-22 23:27:42 +0100197
198 /* detect cpu id */
199 s3c64xx_init_cpu();
200
201 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
Tomasz Figa1c161fd2013-04-12 21:17:22 +0200202
203 samsung_pwm_set_platdata(&s3c64xx_pwm_variant);
Kukjin Kimb024043b2011-12-22 23:27:42 +0100204}
205
Linus Torvalds7affca32012-01-07 12:03:30 -0800206static __init int s3c64xx_dev_init(void)
Kukjin Kimb024043b2011-12-22 23:27:42 +0100207{
Tomasz Figac836c902013-08-26 02:37:34 +0900208 /* Not applicable when using DT. */
Arnd Bergmanna0e157a2015-02-27 20:31:51 +0100209 if (of_have_populated_dt() || !soc_is_s3c64xx())
Tomasz Figac836c902013-08-26 02:37:34 +0900210 return 0;
211
Linus Torvalds7affca32012-01-07 12:03:30 -0800212 subsys_system_register(&s3c64xx_subsys, NULL);
213 return device_register(&s3c64xx_dev);
Kukjin Kimb024043b2011-12-22 23:27:42 +0100214}
Linus Torvalds7affca32012-01-07 12:03:30 -0800215core_initcall(s3c64xx_dev_init);
Kukjin Kimb024043b2011-12-22 23:27:42 +0100216
217/*
218 * setup the sources the vic should advertise resume
219 * for, even though it is not doing the wake
220 * (set_irq_wake needs to be valid)
221 */
222#define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
223#define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \
224 1 << (IRQ_PENDN - IRQ_VIC1_BASE) | \
225 1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) | \
226 1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) | \
227 1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
228
229void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
230{
Tomasz Figa88f59732013-06-17 23:45:37 +0900231 /*
232 * FIXME: there is no better place to put this at the moment
Tomasz Figab69f4602013-08-26 02:00:38 +0900233 * (s3c64xx_clk_init needs ioremap and must happen before init_time
234 * samsung_wdt_reset_init needs clocks)
Tomasz Figa88f59732013-06-17 23:45:37 +0900235 */
Tomasz Figab69f4602013-08-26 02:00:38 +0900236 s3c64xx_clk_init(NULL, xtal_f, xusbxti_f, soc_is_s3c6400(), S3C_VA_SYS);
Tomasz Figa88f59732013-06-17 23:45:37 +0900237 samsung_wdt_reset_init(S3C_VA_WATCHDOG);
238
Kukjin Kimb024043b2011-12-22 23:27:42 +0100239 printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
240
241 /* initialise the pair of VICs */
242 vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
243 vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
Kukjin Kimb024043b2011-12-22 23:27:42 +0100244}
245
246#define eint_offset(irq) ((irq) - IRQ_EINT(0))
247#define eint_irq_to_bit(irq) ((u32)(1 << eint_offset(irq)))
248
249static inline void s3c_irq_eint_mask(struct irq_data *data)
250{
251 u32 mask;
252
253 mask = __raw_readl(S3C64XX_EINT0MASK);
254 mask |= (u32)data->chip_data;
255 __raw_writel(mask, S3C64XX_EINT0MASK);
256}
257
258static void s3c_irq_eint_unmask(struct irq_data *data)
259{
260 u32 mask;
261
262 mask = __raw_readl(S3C64XX_EINT0MASK);
263 mask &= ~((u32)data->chip_data);
264 __raw_writel(mask, S3C64XX_EINT0MASK);
265}
266
267static inline void s3c_irq_eint_ack(struct irq_data *data)
268{
269 __raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND);
270}
271
272static void s3c_irq_eint_maskack(struct irq_data *data)
273{
274 /* compiler should in-line these */
275 s3c_irq_eint_mask(data);
276 s3c_irq_eint_ack(data);
277}
278
279static int s3c_irq_eint_set_type(struct irq_data *data, unsigned int type)
280{
281 int offs = eint_offset(data->irq);
282 int pin, pin_val;
283 int shift;
284 u32 ctrl, mask;
285 u32 newvalue = 0;
286 void __iomem *reg;
287
288 if (offs > 27)
289 return -EINVAL;
290
291 if (offs <= 15)
292 reg = S3C64XX_EINT0CON0;
293 else
294 reg = S3C64XX_EINT0CON1;
295
296 switch (type) {
297 case IRQ_TYPE_NONE:
298 printk(KERN_WARNING "No edge setting!\n");
299 break;
300
301 case IRQ_TYPE_EDGE_RISING:
302 newvalue = S3C2410_EXTINT_RISEEDGE;
303 break;
304
305 case IRQ_TYPE_EDGE_FALLING:
306 newvalue = S3C2410_EXTINT_FALLEDGE;
307 break;
308
309 case IRQ_TYPE_EDGE_BOTH:
310 newvalue = S3C2410_EXTINT_BOTHEDGE;
311 break;
312
313 case IRQ_TYPE_LEVEL_LOW:
314 newvalue = S3C2410_EXTINT_LOWLEV;
315 break;
316
317 case IRQ_TYPE_LEVEL_HIGH:
318 newvalue = S3C2410_EXTINT_HILEV;
319 break;
320
321 default:
322 printk(KERN_ERR "No such irq type %d", type);
323 return -1;
324 }
325
326 if (offs <= 15)
327 shift = (offs / 2) * 4;
328 else
329 shift = ((offs - 16) / 2) * 4;
330 mask = 0x7 << shift;
331
332 ctrl = __raw_readl(reg);
333 ctrl &= ~mask;
334 ctrl |= newvalue << shift;
335 __raw_writel(ctrl, reg);
336
337 /* set the GPIO pin appropriately */
338
339 if (offs < 16) {
340 pin = S3C64XX_GPN(offs);
341 pin_val = S3C_GPIO_SFN(2);
342 } else if (offs < 23) {
343 pin = S3C64XX_GPL(offs + 8 - 16);
344 pin_val = S3C_GPIO_SFN(3);
345 } else {
346 pin = S3C64XX_GPM(offs - 23);
347 pin_val = S3C_GPIO_SFN(3);
348 }
349
350 s3c_gpio_cfgpin(pin, pin_val);
351
352 return 0;
353}
354
355static struct irq_chip s3c_irq_eint = {
356 .name = "s3c-eint",
357 .irq_mask = s3c_irq_eint_mask,
358 .irq_unmask = s3c_irq_eint_unmask,
359 .irq_mask_ack = s3c_irq_eint_maskack,
360 .irq_ack = s3c_irq_eint_ack,
361 .irq_set_type = s3c_irq_eint_set_type,
362 .irq_set_wake = s3c_irqext_wake,
363};
364
365/* s3c_irq_demux_eint
366 *
367 * This function demuxes the IRQ from the group0 external interrupts,
368 * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
369 * the specific handlers s3c_irq_demux_eintX_Y.
370 */
371static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
372{
373 u32 status = __raw_readl(S3C64XX_EINT0PEND);
374 u32 mask = __raw_readl(S3C64XX_EINT0MASK);
375 unsigned int irq;
376
377 status &= ~mask;
378 status >>= start;
379 status &= (1 << (end - start + 1)) - 1;
380
381 for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
382 if (status & 1)
383 generic_handle_irq(irq);
384
385 status >>= 1;
386 }
387}
388
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200389static void s3c_irq_demux_eint0_3(struct irq_desc *desc)
Kukjin Kimb024043b2011-12-22 23:27:42 +0100390{
391 s3c_irq_demux_eint(0, 3);
392}
393
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200394static void s3c_irq_demux_eint4_11(struct irq_desc *desc)
Kukjin Kimb024043b2011-12-22 23:27:42 +0100395{
396 s3c_irq_demux_eint(4, 11);
397}
398
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200399static void s3c_irq_demux_eint12_19(struct irq_desc *desc)
Kukjin Kimb024043b2011-12-22 23:27:42 +0100400{
401 s3c_irq_demux_eint(12, 19);
402}
403
Thomas Gleixnerbd0b9ac2015-09-14 10:42:37 +0200404static void s3c_irq_demux_eint20_27(struct irq_desc *desc)
Kukjin Kimb024043b2011-12-22 23:27:42 +0100405{
406 s3c_irq_demux_eint(20, 27);
407}
408
409static int __init s3c64xx_init_irq_eint(void)
410{
411 int irq;
412
Tomasz Figac836c902013-08-26 02:37:34 +0900413 /* On DT-enabled systems EINTs are handled by pinctrl-s3c64xx driver. */
Arnd Bergmanna0e157a2015-02-27 20:31:51 +0100414 if (of_have_populated_dt() || !soc_is_s3c64xx())
Tomasz Figac836c902013-08-26 02:37:34 +0900415 return -ENODEV;
416
Kukjin Kimb024043b2011-12-22 23:27:42 +0100417 for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
418 irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq);
419 irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
Rob Herringe8d36d52015-07-27 15:55:13 -0500420 irq_clear_status_flags(irq, IRQ_NOREQUEST);
Kukjin Kimb024043b2011-12-22 23:27:42 +0100421 }
422
423 irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
424 irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
425 irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
426 irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
427
428 return 0;
429}
430arch_initcall(s3c64xx_init_irq_eint);
Kukjin Kimff84ded2012-01-03 14:03:30 +0100431
Robin Holt7b6d8642013-07-08 16:01:40 -0700432void s3c64xx_restart(enum reboot_mode mode, const char *cmd)
Kukjin Kimff84ded2012-01-03 14:03:30 +0100433{
Robin Holt7b6d8642013-07-08 16:01:40 -0700434 if (mode != REBOOT_SOFT)
Tomasz Figa88f59732013-06-17 23:45:37 +0900435 samsung_wdt_reset();
Kukjin Kimff84ded2012-01-03 14:03:30 +0100436
437 /* if all else fails, or mode was for soft, jump to 0 */
438 soft_restart(0);
439}