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Gregory CLEMENT69f56892018-03-15 14:40:56 +01001// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
Thomas Petazzonif3b42b72012-09-13 17:41:48 +02002/*
3 * Device Tree Include file for Marvell Armada XP family SoC
4 *
5 * Copyright (C) 2012 Marvell
6 *
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 *
Thomas Petazzonif3b42b72012-09-13 17:41:48 +02009 * Contains definitions specific to the Armada XP MV78230 SoC that are not
10 * common to all Armada XP SoCs.
11 */
12
Jason Cooperf72b7202013-08-07 20:04:21 +000013#include "armada-xp.dtsi"
Thomas Petazzonif3b42b72012-09-13 17:41:48 +020014
15/ {
16 model = "Marvell Armada XP MV78230 SoC";
17 compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
18
Thomas Petazzoni397d59f2012-09-19 22:53:01 +020019 aliases {
20 gpio0 = &gpio0;
21 gpio1 = &gpio1;
22 };
23
Gregory CLEMENT9d202782012-11-17 15:22:24 +010024 cpus {
Thomas Petazzoni1b2529d2013-04-12 16:29:06 +020025 #address-cells = <1>;
26 #size-cells = <0>;
Thomas Petazzoni23157852014-04-14 15:54:00 +020027 enable-method = "marvell,armada-xp-smp";
Gregory CLEMENT9d202782012-11-17 15:22:24 +010028
Thomas Petazzoni1b2529d2013-04-12 16:29:06 +020029 cpu@0 {
30 device_type = "cpu";
31 compatible = "marvell,sheeva-v7";
32 reg = <0>;
33 clocks = <&cpuclk 0>;
Thomas Petazzoni38436072014-07-09 17:45:12 +020034 clock-latency = <1000000>;
Thomas Petazzoni1b2529d2013-04-12 16:29:06 +020035 };
Thomas Petazzoni44cfae92013-01-06 11:10:40 +010036
Thomas Petazzoni1b2529d2013-04-12 16:29:06 +020037 cpu@1 {
38 device_type = "cpu";
39 compatible = "marvell,sheeva-v7";
40 reg = <1>;
41 clocks = <&cpuclk 1>;
Thomas Petazzoni38436072014-07-09 17:45:12 +020042 clock-latency = <1000000>;
Thomas Petazzoni1b2529d2013-04-12 16:29:06 +020043 };
Andrew Lunn41be8dc2013-01-06 11:10:42 +010044 };
Gregory CLEMENT9d202782012-11-17 15:22:24 +010045
Thomas Petazzonif3b42b72012-09-13 17:41:48 +020046 soc {
Ezequiel Garcia14fd8ed2013-07-26 10:18:00 -030047 /*
48 * MV78230 has 2 PCIe units Gen2.0: One unit can be
49 * configured as x4 or quad x1 lanes. One unit is
Arnaud Ebalard12b69a52013-11-05 21:45:48 +010050 * x1 only.
Ezequiel Garcia14fd8ed2013-07-26 10:18:00 -030051 */
Rob Herring28fbb9c2017-07-26 16:09:37 -050052 pciec: pcie@82000000 {
Ezequiel Garcia14fd8ed2013-07-26 10:18:00 -030053 compatible = "marvell,armada-xp-pcie";
54 status = "disabled";
55 device_type = "pci";
56
57 #address-cells = <3>;
58 #size-cells = <2>;
59
Thomas Petazzonid4fa9942013-08-09 22:27:15 +020060 msi-parent = <&mpic>;
Ezequiel Garcia14fd8ed2013-07-26 10:18:00 -030061 bus-range = <0x00 0xff>;
62
63 ranges =
64 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
Ezequiel Garcia14fd8ed2013-07-26 10:18:00 -030065 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
66 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
67 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
Arnaud Ebalard12b69a52013-11-05 21:45:48 +010068 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
Ezequiel Garcia14fd8ed2013-07-26 10:18:00 -030069 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
70 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
71 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
72 0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
73 0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
74 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
75 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
76 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
Arnaud Ebalard12b69a52013-11-05 21:45:48 +010077 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
78 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
Ezequiel Garcia14fd8ed2013-07-26 10:18:00 -030079
Gregory CLEMENT11f71352016-11-04 16:27:03 +010080 pcie1: pcie@1,0 {
Ezequiel Garcia14fd8ed2013-07-26 10:18:00 -030081 device_type = "pci";
82 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
83 reg = <0x0800 0 0 0 0>;
84 #address-cells = <3>;
85 #size-cells = <2>;
86 #interrupt-cells = <1>;
87 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
88 0x81000000 0 0 0x81000000 0x1 0 1 0>;
Rob Herring28fbb9c2017-07-26 16:09:37 -050089 bus-range = <0x00 0xff>;
Ezequiel Garcia14fd8ed2013-07-26 10:18:00 -030090 interrupt-map-mask = <0 0 0 0>;
91 interrupt-map = <0 0 0 0 &mpic 58>;
92 marvell,pcie-port = <0>;
93 marvell,pcie-lane = <0>;
94 clocks = <&gateclk 5>;
95 status = "disabled";
96 };
97
Gregory CLEMENT11f71352016-11-04 16:27:03 +010098 pcie2: pcie@2,0 {
Ezequiel Garcia14fd8ed2013-07-26 10:18:00 -030099 device_type = "pci";
100 assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
101 reg = <0x1000 0 0 0 0>;
102 #address-cells = <3>;
103 #size-cells = <2>;
104 #interrupt-cells = <1>;
105 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
106 0x81000000 0 0 0x81000000 0x2 0 1 0>;
Rob Herring28fbb9c2017-07-26 16:09:37 -0500107 bus-range = <0x00 0xff>;
Ezequiel Garcia14fd8ed2013-07-26 10:18:00 -0300108 interrupt-map-mask = <0 0 0 0>;
109 interrupt-map = <0 0 0 0 &mpic 59>;
110 marvell,pcie-port = <0>;
111 marvell,pcie-lane = <1>;
112 clocks = <&gateclk 6>;
113 status = "disabled";
114 };
115
Gregory CLEMENT11f71352016-11-04 16:27:03 +0100116 pcie3: pcie@3,0 {
Ezequiel Garcia14fd8ed2013-07-26 10:18:00 -0300117 device_type = "pci";
118 assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
119 reg = <0x1800 0 0 0 0>;
120 #address-cells = <3>;
121 #size-cells = <2>;
122 #interrupt-cells = <1>;
123 ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
124 0x81000000 0 0 0x81000000 0x3 0 1 0>;
Rob Herring28fbb9c2017-07-26 16:09:37 -0500125 bus-range = <0x00 0xff>;
Ezequiel Garcia14fd8ed2013-07-26 10:18:00 -0300126 interrupt-map-mask = <0 0 0 0>;
127 interrupt-map = <0 0 0 0 &mpic 60>;
128 marvell,pcie-port = <0>;
129 marvell,pcie-lane = <2>;
130 clocks = <&gateclk 7>;
131 status = "disabled";
132 };
133
Gregory CLEMENT11f71352016-11-04 16:27:03 +0100134 pcie4: pcie@4,0 {
Ezequiel Garcia14fd8ed2013-07-26 10:18:00 -0300135 device_type = "pci";
136 assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
137 reg = <0x2000 0 0 0 0>;
138 #address-cells = <3>;
139 #size-cells = <2>;
140 #interrupt-cells = <1>;
141 ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
142 0x81000000 0 0 0x81000000 0x4 0 1 0>;
Rob Herring28fbb9c2017-07-26 16:09:37 -0500143 bus-range = <0x00 0xff>;
Ezequiel Garcia14fd8ed2013-07-26 10:18:00 -0300144 interrupt-map-mask = <0 0 0 0>;
145 interrupt-map = <0 0 0 0 &mpic 61>;
146 marvell,pcie-port = <0>;
147 marvell,pcie-lane = <3>;
148 clocks = <&gateclk 8>;
149 status = "disabled";
150 };
151
Gregory CLEMENT11f71352016-11-04 16:27:03 +0100152 pcie5: pcie@5,0 {
Ezequiel Garcia14fd8ed2013-07-26 10:18:00 -0300153 device_type = "pci";
Arnaud Ebalard12b69a52013-11-05 21:45:48 +0100154 assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
155 reg = <0x2800 0 0 0 0>;
Ezequiel Garcia14fd8ed2013-07-26 10:18:00 -0300156 #address-cells = <3>;
157 #size-cells = <2>;
158 #interrupt-cells = <1>;
Arnaud Ebalard12b69a52013-11-05 21:45:48 +0100159 ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
160 0x81000000 0 0 0x81000000 0x5 0 1 0>;
Rob Herring28fbb9c2017-07-26 16:09:37 -0500161 bus-range = <0x00 0xff>;
Ezequiel Garcia14fd8ed2013-07-26 10:18:00 -0300162 interrupt-map-mask = <0 0 0 0>;
Arnaud Ebalard12b69a52013-11-05 21:45:48 +0100163 interrupt-map = <0 0 0 0 &mpic 62>;
164 marvell,pcie-port = <1>;
Ezequiel Garcia14fd8ed2013-07-26 10:18:00 -0300165 marvell,pcie-lane = <0>;
Arnaud Ebalard12b69a52013-11-05 21:45:48 +0100166 clocks = <&gateclk 9>;
Ezequiel Garcia14fd8ed2013-07-26 10:18:00 -0300167 status = "disabled";
168 };
169 };
170
Gregory CLEMENT467f54b2013-04-12 16:29:09 +0200171 internal-regs {
Gregory CLEMENT467f54b2013-04-12 16:29:09 +0200172 gpio0: gpio@18100 {
Andrew Lunn0c8c9ff2017-06-01 22:09:26 +0200173 compatible = "marvell,armada-370-gpio",
174 "marvell,orion-gpio";
175 reg = <0x18100 0x40>, <0x181c0 0x08>;
176 reg-names = "gpio", "pwm";
Gregory CLEMENT467f54b2013-04-12 16:29:09 +0200177 ngpios = <32>;
178 gpio-controller;
179 #gpio-cells = <2>;
Andrew Lunn0c8c9ff2017-06-01 22:09:26 +0200180 #pwm-cells = <2>;
Gregory CLEMENT467f54b2013-04-12 16:29:09 +0200181 interrupt-controller;
Thomas Petazzonica609852013-07-30 16:59:02 +0200182 #interrupt-cells = <2>;
Gregory CLEMENT467f54b2013-04-12 16:29:09 +0200183 interrupts = <82>, <83>, <84>, <85>;
Andrew Lunn0c8c9ff2017-06-01 22:09:26 +0200184 clocks = <&coreclk 0>;
Thomas Petazzoni9d8f44f2013-04-09 23:06:34 +0200185 };
186
Gregory CLEMENT467f54b2013-04-12 16:29:09 +0200187 gpio1: gpio@18140 {
Andrew Lunn0c8c9ff2017-06-01 22:09:26 +0200188 compatible = "marvell,armada-370-gpio",
189 "marvell,orion-gpio";
190 reg = <0x18140 0x40>, <0x181c8 0x08>;
191 reg-names = "gpio", "pwm";
Gregory CLEMENT467f54b2013-04-12 16:29:09 +0200192 ngpios = <17>;
193 gpio-controller;
194 #gpio-cells = <2>;
Andrew Lunn0c8c9ff2017-06-01 22:09:26 +0200195 #pwm-cells = <2>;
Gregory CLEMENT467f54b2013-04-12 16:29:09 +0200196 interrupt-controller;
Thomas Petazzonica609852013-07-30 16:59:02 +0200197 #interrupt-cells = <2>;
Gregory CLEMENT467f54b2013-04-12 16:29:09 +0200198 interrupts = <87>, <88>, <89>;
Andrew Lunn0c8c9ff2017-06-01 22:09:26 +0200199 clocks = <&coreclk 0>;
Thomas Petazzoni9d8f44f2013-04-09 23:06:34 +0200200 };
Thomas Petazzoni9d8f44f2013-04-09 23:06:34 +0200201 };
Thomas Petazzonif3b42b72012-09-13 17:41:48 +0200202 };
203};
Sebastian Hesselbarth01c43422014-09-19 21:20:09 +0200204
205&pinctrl {
206 compatible = "marvell,mv78230-pinctrl";
207};