Thomas Gleixner | d2912cb | 2019-06-04 10:11:33 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Colin Cross | 1cea732 | 2010-02-21 17:46:23 -0800 | [diff] [blame] | 2 | /* |
| 3 | * linux/arch/arm/mach-tegra/platsmp.c |
| 4 | * |
| 5 | * Copyright (C) 2002 ARM Ltd. |
| 6 | * All Rights Reserved |
| 7 | * |
| 8 | * Copyright (C) 2009 Palm |
| 9 | * All Rights Reserved |
Colin Cross | 1cea732 | 2010-02-21 17:46:23 -0800 | [diff] [blame] | 10 | */ |
Thierry Reding | a0524ac | 2014-07-11 09:44:49 +0200 | [diff] [blame] | 11 | |
| 12 | #include <linux/clk/tegra.h> |
Colin Cross | 1cea732 | 2010-02-21 17:46:23 -0800 | [diff] [blame] | 13 | #include <linux/delay.h> |
| 14 | #include <linux/device.h> |
Thierry Reding | a0524ac | 2014-07-11 09:44:49 +0200 | [diff] [blame] | 15 | #include <linux/errno.h> |
| 16 | #include <linux/init.h> |
| 17 | #include <linux/io.h> |
Colin Cross | 1cea732 | 2010-02-21 17:46:23 -0800 | [diff] [blame] | 18 | #include <linux/jiffies.h> |
| 19 | #include <linux/smp.h> |
Colin Cross | 1cea732 | 2010-02-21 17:46:23 -0800 | [diff] [blame] | 20 | |
Jon Hunter | 7e10cf7 | 2017-03-28 13:42:54 +0100 | [diff] [blame] | 21 | #include <soc/tegra/flowctrl.h> |
Thierry Reding | 304664e | 2014-07-11 09:52:41 +0200 | [diff] [blame] | 22 | #include <soc/tegra/fuse.h> |
Thierry Reding | 7232398 | 2014-07-11 13:19:06 +0200 | [diff] [blame] | 23 | #include <soc/tegra/pmc.h> |
Thierry Reding | 304664e | 2014-07-11 09:52:41 +0200 | [diff] [blame] | 24 | |
Colin Cross | 1cea732 | 2010-02-21 17:46:23 -0800 | [diff] [blame] | 25 | #include <asm/cacheflush.h> |
Colin Cross | 1cea732 | 2010-02-21 17:46:23 -0800 | [diff] [blame] | 26 | #include <asm/mach-types.h> |
Joseph Lo | 130bfed | 2013-01-03 15:31:31 +0800 | [diff] [blame] | 27 | #include <asm/smp_plat.h> |
Thierry Reding | a0524ac | 2014-07-11 09:44:49 +0200 | [diff] [blame] | 28 | #include <asm/smp_scu.h> |
Peter De Schrijver | b36ab97 | 2012-02-10 01:47:45 +0200 | [diff] [blame] | 29 | |
Marc Zyngier | a172573 | 2011-09-08 13:15:22 +0100 | [diff] [blame] | 30 | #include "common.h" |
Stephen Warren | 2be39c0 | 2012-10-04 14:24:09 -0600 | [diff] [blame] | 31 | #include "iomap.h" |
Thierry Reding | a0524ac | 2014-07-11 09:44:49 +0200 | [diff] [blame] | 32 | #include "reset.h" |
Marc Zyngier | a172573 | 2011-09-08 13:15:22 +0100 | [diff] [blame] | 33 | |
Joseph Lo | 130bfed | 2013-01-03 15:31:31 +0800 | [diff] [blame] | 34 | static cpumask_t tegra_cpu_init_mask; |
Colin Cross | 1cea732 | 2010-02-21 17:46:23 -0800 | [diff] [blame] | 35 | |
Paul Gortmaker | 8bd26e3 | 2013-06-17 15:43:14 -0400 | [diff] [blame] | 36 | static void tegra_secondary_init(unsigned int cpu) |
Colin Cross | 1cea732 | 2010-02-21 17:46:23 -0800 | [diff] [blame] | 37 | { |
Joseph Lo | 130bfed | 2013-01-03 15:31:31 +0800 | [diff] [blame] | 38 | cpumask_set_cpu(cpu, &tegra_cpu_init_mask); |
Peter De Schrijver | b36ab97 | 2012-02-10 01:47:45 +0200 | [diff] [blame] | 39 | } |
| 40 | |
Hiroshi Doyu | 0d1f79b | 2013-02-22 14:24:27 +0800 | [diff] [blame] | 41 | |
| 42 | static int tegra20_boot_secondary(unsigned int cpu, struct task_struct *idle) |
Peter De Schrijver | b36ab97 | 2012-02-10 01:47:45 +0200 | [diff] [blame] | 43 | { |
Hiroshi Doyu | 0d1f79b | 2013-02-22 14:24:27 +0800 | [diff] [blame] | 44 | cpu = cpu_logical_map(cpu); |
| 45 | |
| 46 | /* |
| 47 | * Force the CPU into reset. The CPU must remain in reset when |
| 48 | * the flow controller state is cleared (which will cause the |
| 49 | * flow controller to stop driving reset if the CPU has been |
| 50 | * power-gated via the flow controller). This will have no |
| 51 | * effect on first boot of the CPU since it should already be |
| 52 | * in reset. |
| 53 | */ |
| 54 | tegra_put_cpu_in_reset(cpu); |
| 55 | |
| 56 | /* |
| 57 | * Unhalt the CPU. If the flow controller was used to |
| 58 | * power-gate the CPU this will cause the flow controller to |
| 59 | * stop driving reset. The CPU will remain in reset because the |
| 60 | * clock and reset block is now driving reset. |
| 61 | */ |
| 62 | flowctrl_write_cpu_halt(cpu, 0); |
| 63 | |
Joseph Lo | bb60327 | 2012-08-16 17:31:49 +0800 | [diff] [blame] | 64 | tegra_enable_cpu_clock(cpu); |
Hiroshi Doyu | 0d1f79b | 2013-02-22 14:24:27 +0800 | [diff] [blame] | 65 | flowctrl_write_cpu_csr(cpu, 0); /* Clear flow controller CSR. */ |
| 66 | tegra_cpu_out_of_reset(cpu); |
Peter De Schrijver | b36ab97 | 2012-02-10 01:47:45 +0200 | [diff] [blame] | 67 | return 0; |
Colin Cross | 1cea732 | 2010-02-21 17:46:23 -0800 | [diff] [blame] | 68 | } |
| 69 | |
Hiroshi Doyu | 0d1f79b | 2013-02-22 14:24:27 +0800 | [diff] [blame] | 70 | static int tegra30_boot_secondary(unsigned int cpu, struct task_struct *idle) |
Peter De Schrijver | 86e51a2 | 2012-02-10 01:47:50 +0200 | [diff] [blame] | 71 | { |
Joseph Lo | 7e56474 | 2013-02-26 16:28:06 +0000 | [diff] [blame] | 72 | int ret; |
Peter De Schrijver | 86e51a2 | 2012-02-10 01:47:50 +0200 | [diff] [blame] | 73 | unsigned long timeout; |
| 74 | |
Hiroshi Doyu | 0d1f79b | 2013-02-22 14:24:27 +0800 | [diff] [blame] | 75 | cpu = cpu_logical_map(cpu); |
Hiroshi Doyu | 0d1f79b | 2013-02-22 14:24:27 +0800 | [diff] [blame] | 76 | tegra_put_cpu_in_reset(cpu); |
| 77 | flowctrl_write_cpu_halt(cpu, 0); |
| 78 | |
Joseph Lo | 130bfed | 2013-01-03 15:31:31 +0800 | [diff] [blame] | 79 | /* |
| 80 | * The power up sequence of cold boot CPU and warm boot CPU |
| 81 | * was different. |
| 82 | * |
| 83 | * For warm boot CPU that was resumed from CPU hotplug, the |
| 84 | * power will be resumed automatically after un-halting the |
| 85 | * flow controller of the warm boot CPU. We need to wait for |
| 86 | * the confirmaiton that the CPU is powered then removing |
| 87 | * the IO clamps. |
| 88 | * For cold boot CPU, do not wait. After the cold boot CPU be |
| 89 | * booted, it will run to tegra_secondary_init() and set |
Hiroshi Doyu | 0d1f79b | 2013-02-22 14:24:27 +0800 | [diff] [blame] | 90 | * tegra_cpu_init_mask which influences what tegra30_boot_secondary() |
Joseph Lo | 130bfed | 2013-01-03 15:31:31 +0800 | [diff] [blame] | 91 | * next time around. |
| 92 | */ |
| 93 | if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) { |
Joseph Lo | 1395868 | 2013-01-07 10:56:14 +0800 | [diff] [blame] | 94 | timeout = jiffies + msecs_to_jiffies(50); |
Joseph Lo | 130bfed | 2013-01-03 15:31:31 +0800 | [diff] [blame] | 95 | do { |
Joseph Lo | 7e56474 | 2013-02-26 16:28:06 +0000 | [diff] [blame] | 96 | if (tegra_pmc_cpu_is_powered(cpu)) |
Joseph Lo | 130bfed | 2013-01-03 15:31:31 +0800 | [diff] [blame] | 97 | goto remove_clamps; |
| 98 | udelay(10); |
| 99 | } while (time_before(jiffies, timeout)); |
| 100 | } |
| 101 | |
| 102 | /* |
| 103 | * The power status of the cold boot CPU is power gated as |
| 104 | * default. To power up the cold boot CPU, the power should |
| 105 | * be un-gated by un-toggling the power gate register |
| 106 | * manually. |
| 107 | */ |
Jon Hunter | 0a2d87e | 2016-02-26 15:48:40 +0000 | [diff] [blame] | 108 | ret = tegra_pmc_cpu_power_on(cpu); |
| 109 | if (ret) |
| 110 | return ret; |
Peter De Schrijver | 86e51a2 | 2012-02-10 01:47:50 +0200 | [diff] [blame] | 111 | |
Joseph Lo | 130bfed | 2013-01-03 15:31:31 +0800 | [diff] [blame] | 112 | remove_clamps: |
Peter De Schrijver | 86e51a2 | 2012-02-10 01:47:50 +0200 | [diff] [blame] | 113 | /* CPU partition is powered. Enable the CPU clock. */ |
Joseph Lo | bb60327 | 2012-08-16 17:31:49 +0800 | [diff] [blame] | 114 | tegra_enable_cpu_clock(cpu); |
Peter De Schrijver | 86e51a2 | 2012-02-10 01:47:50 +0200 | [diff] [blame] | 115 | udelay(10); |
| 116 | |
| 117 | /* Remove I/O clamps. */ |
Joseph Lo | 7e56474 | 2013-02-26 16:28:06 +0000 | [diff] [blame] | 118 | ret = tegra_pmc_cpu_remove_clamping(cpu); |
Hiroshi Doyu | b4c25cc | 2013-02-22 14:24:25 +0800 | [diff] [blame] | 119 | if (ret) |
| 120 | return ret; |
| 121 | |
Peter De Schrijver | 86e51a2 | 2012-02-10 01:47:50 +0200 | [diff] [blame] | 122 | udelay(10); |
| 123 | |
Hiroshi Doyu | 0d1f79b | 2013-02-22 14:24:27 +0800 | [diff] [blame] | 124 | flowctrl_write_cpu_csr(cpu, 0); /* Clear flow controller CSR. */ |
| 125 | tegra_cpu_out_of_reset(cpu); |
Peter De Schrijver | 86e51a2 | 2012-02-10 01:47:50 +0200 | [diff] [blame] | 126 | return 0; |
| 127 | } |
| 128 | |
Joseph Lo | e562b86 | 2013-02-26 16:28:07 +0000 | [diff] [blame] | 129 | static int tegra114_boot_secondary(unsigned int cpu, struct task_struct *idle) |
| 130 | { |
Joseph Lo | 18901e9 | 2013-05-20 18:39:27 +0800 | [diff] [blame] | 131 | int ret = 0; |
| 132 | |
Joseph Lo | e562b86 | 2013-02-26 16:28:07 +0000 | [diff] [blame] | 133 | cpu = cpu_logical_map(cpu); |
Joseph Lo | 18901e9 | 2013-05-20 18:39:27 +0800 | [diff] [blame] | 134 | |
| 135 | if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) { |
| 136 | /* |
| 137 | * Warm boot flow |
| 138 | * The flow controller in charge of the power state and |
| 139 | * control for each CPU. |
| 140 | */ |
| 141 | /* set SCLK as event trigger for flow controller */ |
| 142 | flowctrl_write_cpu_csr(cpu, 1); |
| 143 | flowctrl_write_cpu_halt(cpu, |
| 144 | FLOW_CTRL_WAITEVENT | FLOW_CTRL_SCLK_RESUME); |
| 145 | } else { |
| 146 | /* |
| 147 | * Cold boot flow |
| 148 | * The CPU is powered up by toggling PMC directly. It will |
| 149 | * also initial power state in flow controller. After that, |
| 150 | * the CPU's power state is maintained by flow controller. |
| 151 | */ |
| 152 | ret = tegra_pmc_cpu_power_on(cpu); |
| 153 | } |
| 154 | |
| 155 | return ret; |
Joseph Lo | e562b86 | 2013-02-26 16:28:07 +0000 | [diff] [blame] | 156 | } |
| 157 | |
Paul Gortmaker | 8bd26e3 | 2013-06-17 15:43:14 -0400 | [diff] [blame] | 158 | static int tegra_boot_secondary(unsigned int cpu, |
Hiroshi Doyu | 0d1f79b | 2013-02-22 14:24:27 +0800 | [diff] [blame] | 159 | struct task_struct *idle) |
Colin Cross | 1cea732 | 2010-02-21 17:46:23 -0800 | [diff] [blame] | 160 | { |
Thierry Reding | 304664e | 2014-07-11 09:52:41 +0200 | [diff] [blame] | 161 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && tegra_get_chip_id() == TEGRA20) |
Hiroshi Doyu | 0d1f79b | 2013-02-22 14:24:27 +0800 | [diff] [blame] | 162 | return tegra20_boot_secondary(cpu, idle); |
Thierry Reding | 304664e | 2014-07-11 09:52:41 +0200 | [diff] [blame] | 163 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_get_chip_id() == TEGRA30) |
Hiroshi Doyu | 0d1f79b | 2013-02-22 14:24:27 +0800 | [diff] [blame] | 164 | return tegra30_boot_secondary(cpu, idle); |
Thierry Reding | 304664e | 2014-07-11 09:52:41 +0200 | [diff] [blame] | 165 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_get_chip_id() == TEGRA114) |
Joseph Lo | e562b86 | 2013-02-26 16:28:07 +0000 | [diff] [blame] | 166 | return tegra114_boot_secondary(cpu, idle); |
Thierry Reding | 304664e | 2014-07-11 09:52:41 +0200 | [diff] [blame] | 167 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) && tegra_get_chip_id() == TEGRA124) |
Joseph Lo | 7394447 | 2013-10-08 12:50:03 +0800 | [diff] [blame] | 168 | return tegra114_boot_secondary(cpu, idle); |
Peter De Schrijver | b36ab97 | 2012-02-10 01:47:45 +0200 | [diff] [blame] | 169 | |
Hiroshi Doyu | 0d1f79b | 2013-02-22 14:24:27 +0800 | [diff] [blame] | 170 | return -EINVAL; |
Colin Cross | 1cea732 | 2010-02-21 17:46:23 -0800 | [diff] [blame] | 171 | } |
| 172 | |
Marc Zyngier | a172573 | 2011-09-08 13:15:22 +0100 | [diff] [blame] | 173 | static void __init tegra_smp_prepare_cpus(unsigned int max_cpus) |
Colin Cross | 1cea732 | 2010-02-21 17:46:23 -0800 | [diff] [blame] | 174 | { |
Joseph Lo | 130bfed | 2013-01-03 15:31:31 +0800 | [diff] [blame] | 175 | /* Always mark the boot CPU (CPU0) as initialized. */ |
| 176 | cpumask_set_cpu(0, &tegra_cpu_init_mask); |
| 177 | |
Hiroshi Doyu | 909444a | 2013-01-22 07:52:02 +0200 | [diff] [blame] | 178 | if (scu_a9_has_base()) |
| 179 | scu_enable(IO_ADDRESS(scu_a9_get_base())); |
Colin Cross | 1cea732 | 2010-02-21 17:46:23 -0800 | [diff] [blame] | 180 | } |
Marc Zyngier | a172573 | 2011-09-08 13:15:22 +0100 | [diff] [blame] | 181 | |
Masahiro Yamada | 7530527 | 2015-11-15 10:39:53 +0900 | [diff] [blame] | 182 | const struct smp_operations tegra_smp_ops __initconst = { |
Marc Zyngier | a172573 | 2011-09-08 13:15:22 +0100 | [diff] [blame] | 183 | .smp_prepare_cpus = tegra_smp_prepare_cpus, |
| 184 | .smp_secondary_init = tegra_secondary_init, |
| 185 | .smp_boot_secondary = tegra_boot_secondary, |
| 186 | #ifdef CONFIG_HOTPLUG_CPU |
Joseph Lo | b811943 | 2013-01-03 14:43:00 +0800 | [diff] [blame] | 187 | .cpu_kill = tegra_cpu_kill, |
Marc Zyngier | a172573 | 2011-09-08 13:15:22 +0100 | [diff] [blame] | 188 | .cpu_die = tegra_cpu_die, |
| 189 | #endif |
| 190 | }; |