Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
Andrew Vasquez | fa90c54 | 2005-10-27 11:10:08 -0700 | [diff] [blame] | 2 | * QLogic Fibre Channel HBA Driver |
Armen Baloyan | bd21eaf | 2014-04-11 16:54:24 -0400 | [diff] [blame] | 3 | * Copyright (c) 2003-2014 QLogic Corporation |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | * |
Andrew Vasquez | fa90c54 | 2005-10-27 11:10:08 -0700 | [diff] [blame] | 5 | * See LICENSE.qla2xxx for copyright and licensing details. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6 | */ |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 7 | |
| 8 | /* |
| 9 | * Table for showing the current message id in use for particular level |
| 10 | * Change this table for addition of log/debug messages. |
Arun Easi | e02587d | 2011-08-16 11:29:23 -0700 | [diff] [blame] | 11 | * ---------------------------------------------------------------------- |
| 12 | * | Level | Last Value Used | Holes | |
| 13 | * ---------------------------------------------------------------------- |
Michael Hernandez | d745952 | 2016-12-12 14:40:07 -0800 | [diff] [blame] | 14 | * | Module Init and Probe | 0x0193 | 0x0146 | |
Chad Dupuis | f73cb69 | 2014-02-26 04:15:06 -0500 | [diff] [blame] | 15 | * | | | 0x015b-0x0160 | |
Joe Carnuccio | a7ddd02 | 2016-07-06 11:14:22 -0400 | [diff] [blame] | 16 | * | | | 0x016e | |
Duane Grigsby | deeae7a | 2017-07-21 09:32:25 -0700 | [diff] [blame] | 17 | * | Mailbox commands | 0x1205 | 0x11a2-0x11ff | |
Duane Grigsby | e84067d | 2017-06-21 13:48:43 -0700 | [diff] [blame] | 18 | * | Device Discovery | 0x2134 | 0x210e-0x2116 | |
Duane Grigsby | a5d42f4 | 2017-06-21 13:48:41 -0700 | [diff] [blame] | 19 | * | | | 0x211a | |
| 20 | * | | | 0x211c-0x2128 | |
| 21 | * | | | 0x212a-0x2130 | |
Himanshu Madhani | 6eb5471 | 2015-12-17 14:57:00 -0500 | [diff] [blame] | 22 | * | Queue Command and IO tracing | 0x3074 | 0x300b | |
Arun Easi | 9e522cd | 2012-08-22 14:21:31 -0400 | [diff] [blame] | 23 | * | | | 0x3027-0x3028 | |
Giridhar Malavali | 8ae6d9c | 2013-03-28 08:21:23 -0400 | [diff] [blame] | 24 | * | | | 0x303d-0x3041 | |
| 25 | * | | | 0x302d,0x3033 | |
| 26 | * | | | 0x3036,0x3038 | |
| 27 | * | | | 0x303a | |
Armen Baloyan | e8f5e95 | 2013-10-30 03:38:17 -0400 | [diff] [blame] | 28 | * | DPC Thread | 0x4023 | 0x4002,0x4013 | |
Sawan Chandak | 75d560e | 2016-07-06 11:14:33 -0400 | [diff] [blame] | 29 | * | Async Events | 0x5090 | 0x502b-0x502f | |
Joe Carnuccio | a29b3dd | 2016-07-06 11:14:19 -0400 | [diff] [blame] | 30 | * | | | 0x5047 | |
Saurav Kashyap | 6ddcfef | 2013-08-27 01:37:53 -0400 | [diff] [blame] | 31 | * | | | 0x5084,0x5075 | |
Chad Dupuis | a78951b | 2013-08-27 01:37:34 -0400 | [diff] [blame] | 32 | * | | | 0x503d,0x5044 | |
Joe Carnuccio | 41233cd | 2016-07-06 11:14:29 -0400 | [diff] [blame] | 33 | * | | | 0x505f | |
Armen Baloyan | 71e5600 | 2013-08-27 01:37:38 -0400 | [diff] [blame] | 34 | * | Timer Routines | 0x6012 | | |
Harish Zunjarrao | 243de67 | 2016-01-27 12:03:33 -0500 | [diff] [blame] | 35 | * | User Space Interactions | 0x70e3 | 0x7018,0x702e | |
Chad Dupuis | f73cb69 | 2014-02-26 04:15:06 -0500 | [diff] [blame] | 36 | * | | | 0x7020,0x7024 | |
| 37 | * | | | 0x7039,0x7045 | |
| 38 | * | | | 0x7073-0x7075 | |
| 39 | * | | | 0x70a5-0x70a6 | |
| 40 | * | | | 0x70a8,0x70ab | |
| 41 | * | | | 0x70ad-0x70ae | |
Joe Carnuccio | f1d7ce6 | 2016-07-06 11:14:17 -0400 | [diff] [blame] | 42 | * | | | 0x70d0-0x70d6 | |
Chad Dupuis | f73cb69 | 2014-02-26 04:15:06 -0500 | [diff] [blame] | 43 | * | | | 0x70d7-0x70db | |
Quinn Tran | 1608cc4 | 2017-08-23 15:05:03 -0700 | [diff] [blame] | 44 | * | Task Management | 0x8042 | 0x8000 | |
Chad Dupuis | 63ee707 | 2014-04-11 16:54:46 -0400 | [diff] [blame] | 45 | * | | | 0x8019 | |
Chad Dupuis | 7108b76 | 2014-04-11 16:54:45 -0400 | [diff] [blame] | 46 | * | | | 0x8025,0x8026 | |
| 47 | * | | | 0x8031,0x8032 | |
| 48 | * | | | 0x8039,0x803c | |
Saurav Kashyap | 5f28d2d | 2012-05-15 14:34:15 -0400 | [diff] [blame] | 49 | * | AER/EEH | 0x9011 | | |
Arun Easi | e02587d | 2011-08-16 11:29:23 -0700 | [diff] [blame] | 50 | * | Virtual Port | 0xa007 | | |
Atul Deshmukh | 27f4b72 | 2014-04-11 16:54:26 -0400 | [diff] [blame] | 51 | * | ISP82XX Specific | 0xb157 | 0xb002,0xb024 | |
Atul Deshmukh | 7ec0eff | 2013-08-27 01:37:28 -0400 | [diff] [blame] | 52 | * | | | 0xb09e,0xb0ae | |
Hiral Patel | a018d8f | 2014-04-11 16:54:34 -0400 | [diff] [blame] | 53 | * | | | 0xb0c3,0xb0c6 | |
Atul Deshmukh | 7ec0eff | 2013-08-27 01:37:28 -0400 | [diff] [blame] | 54 | * | | | 0xb0e0-0xb0ef | |
| 55 | * | | | 0xb085,0xb0dc | |
| 56 | * | | | 0xb107,0xb108 | |
| 57 | * | | | 0xb111,0xb11e | |
| 58 | * | | | 0xb12c,0xb12d | |
| 59 | * | | | 0xb13a,0xb142 | |
| 60 | * | | | 0xb13c-0xb140 | |
Saurav Kashyap | 6ddcfef | 2013-08-27 01:37:53 -0400 | [diff] [blame] | 61 | * | | | 0xb149 | |
Michael Hernandez | d745952 | 2016-12-12 14:40:07 -0800 | [diff] [blame] | 62 | * | MultiQ | 0xc010 | | |
Duane Grigsby | a5d42f4 | 2017-06-21 13:48:41 -0700 | [diff] [blame] | 63 | * | Misc | 0xd302 | 0xd031-0xd0ff | |
Chad Dupuis | f73cb69 | 2014-02-26 04:15:06 -0500 | [diff] [blame] | 64 | * | | | 0xd101-0xd1fe | |
Joe Carnuccio | 2ac224b | 2014-09-25 05:16:36 -0400 | [diff] [blame] | 65 | * | | | 0xd214-0xd2fe | |
Quinn Tran | 83548fe | 2017-06-02 09:12:01 -0700 | [diff] [blame] | 66 | * | Target Mode | 0xe081 | | |
Alexei Potashnik | b7bd104 | 2015-12-17 14:57:02 -0500 | [diff] [blame] | 67 | * | Target Mode Management | 0xf09b | 0xf002 | |
Saurav Kashyap | 6ddcfef | 2013-08-27 01:37:53 -0400 | [diff] [blame] | 68 | * | | | 0xf046-0xf049 | |
Alexei Potashnik | a6ca887 | 2015-07-14 16:00:44 -0400 | [diff] [blame] | 69 | * | Target Mode Task Management | 0x1000d | | |
Arun Easi | e02587d | 2011-08-16 11:29:23 -0700 | [diff] [blame] | 70 | * ---------------------------------------------------------------------- |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 71 | */ |
| 72 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 73 | #include "qla_def.h" |
| 74 | |
| 75 | #include <linux/delay.h> |
| 76 | |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 77 | static uint32_t ql_dbg_offset = 0x800; |
| 78 | |
Andrew Vasquez | a7a167b | 2006-06-23 16:10:29 -0700 | [diff] [blame] | 79 | static inline void |
Anirban Chakraborty | 7b867cf | 2008-11-06 10:40:19 -0800 | [diff] [blame] | 80 | qla2xxx_prep_dump(struct qla_hw_data *ha, struct qla2xxx_fw_dump *fw_dump) |
Andrew Vasquez | a7a167b | 2006-06-23 16:10:29 -0700 | [diff] [blame] | 81 | { |
| 82 | fw_dump->fw_major_version = htonl(ha->fw_major_version); |
| 83 | fw_dump->fw_minor_version = htonl(ha->fw_minor_version); |
| 84 | fw_dump->fw_subminor_version = htonl(ha->fw_subminor_version); |
| 85 | fw_dump->fw_attributes = htonl(ha->fw_attributes); |
| 86 | |
| 87 | fw_dump->vendor = htonl(ha->pdev->vendor); |
| 88 | fw_dump->device = htonl(ha->pdev->device); |
| 89 | fw_dump->subsystem_vendor = htonl(ha->pdev->subsystem_vendor); |
| 90 | fw_dump->subsystem_device = htonl(ha->pdev->subsystem_device); |
| 91 | } |
| 92 | |
| 93 | static inline void * |
Anirban Chakraborty | 73208df | 2008-12-09 16:45:39 -0800 | [diff] [blame] | 94 | qla2xxx_copy_queues(struct qla_hw_data *ha, void *ptr) |
Andrew Vasquez | a7a167b | 2006-06-23 16:10:29 -0700 | [diff] [blame] | 95 | { |
Anirban Chakraborty | 73208df | 2008-12-09 16:45:39 -0800 | [diff] [blame] | 96 | struct req_que *req = ha->req_q_map[0]; |
| 97 | struct rsp_que *rsp = ha->rsp_q_map[0]; |
Andrew Vasquez | a7a167b | 2006-06-23 16:10:29 -0700 | [diff] [blame] | 98 | /* Request queue. */ |
Anirban Chakraborty | 7b867cf | 2008-11-06 10:40:19 -0800 | [diff] [blame] | 99 | memcpy(ptr, req->ring, req->length * |
Andrew Vasquez | a7a167b | 2006-06-23 16:10:29 -0700 | [diff] [blame] | 100 | sizeof(request_t)); |
| 101 | |
| 102 | /* Response queue. */ |
Anirban Chakraborty | 7b867cf | 2008-11-06 10:40:19 -0800 | [diff] [blame] | 103 | ptr += req->length * sizeof(request_t); |
| 104 | memcpy(ptr, rsp->ring, rsp->length * |
Andrew Vasquez | a7a167b | 2006-06-23 16:10:29 -0700 | [diff] [blame] | 105 | sizeof(response_t)); |
| 106 | |
Anirban Chakraborty | 7b867cf | 2008-11-06 10:40:19 -0800 | [diff] [blame] | 107 | return ptr + (rsp->length * sizeof(response_t)); |
Andrew Vasquez | a7a167b | 2006-06-23 16:10:29 -0700 | [diff] [blame] | 108 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 109 | |
Chad Dupuis | f73cb69 | 2014-02-26 04:15:06 -0500 | [diff] [blame] | 110 | int |
| 111 | qla27xx_dump_mpi_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram, |
| 112 | uint32_t ram_dwords, void **nxt) |
| 113 | { |
| 114 | int rval; |
| 115 | uint32_t cnt, stat, timer, dwords, idx; |
Bart Van Assche | 52c8282 | 2015-07-09 07:23:26 -0700 | [diff] [blame] | 116 | uint16_t mb0; |
Chad Dupuis | f73cb69 | 2014-02-26 04:15:06 -0500 | [diff] [blame] | 117 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
| 118 | dma_addr_t dump_dma = ha->gid_list_dma; |
| 119 | uint32_t *dump = (uint32_t *)ha->gid_list; |
| 120 | |
| 121 | rval = QLA_SUCCESS; |
| 122 | mb0 = 0; |
| 123 | |
| 124 | WRT_REG_WORD(®->mailbox0, MBC_LOAD_DUMP_MPI_RAM); |
| 125 | clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); |
| 126 | |
| 127 | dwords = qla2x00_gid_list_size(ha) / 4; |
| 128 | for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS; |
| 129 | cnt += dwords, addr += dwords) { |
| 130 | if (cnt + dwords > ram_dwords) |
| 131 | dwords = ram_dwords - cnt; |
| 132 | |
| 133 | WRT_REG_WORD(®->mailbox1, LSW(addr)); |
| 134 | WRT_REG_WORD(®->mailbox8, MSW(addr)); |
| 135 | |
| 136 | WRT_REG_WORD(®->mailbox2, MSW(dump_dma)); |
| 137 | WRT_REG_WORD(®->mailbox3, LSW(dump_dma)); |
| 138 | WRT_REG_WORD(®->mailbox6, MSW(MSD(dump_dma))); |
| 139 | WRT_REG_WORD(®->mailbox7, LSW(MSD(dump_dma))); |
| 140 | |
| 141 | WRT_REG_WORD(®->mailbox4, MSW(dwords)); |
| 142 | WRT_REG_WORD(®->mailbox5, LSW(dwords)); |
| 143 | |
| 144 | WRT_REG_WORD(®->mailbox9, 0); |
| 145 | WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); |
| 146 | |
| 147 | ha->flags.mbox_int = 0; |
| 148 | for (timer = 6000000; timer; timer--) { |
| 149 | /* Check for pending interrupts. */ |
| 150 | stat = RD_REG_DWORD(®->host_status); |
| 151 | if (stat & HSRX_RISC_INT) { |
| 152 | stat &= 0xff; |
| 153 | |
| 154 | if (stat == 0x1 || stat == 0x2 || |
| 155 | stat == 0x10 || stat == 0x11) { |
| 156 | set_bit(MBX_INTERRUPT, |
| 157 | &ha->mbx_cmd_flags); |
| 158 | |
| 159 | mb0 = RD_REG_WORD(®->mailbox0); |
Bart Van Assche | 52c8282 | 2015-07-09 07:23:26 -0700 | [diff] [blame] | 160 | RD_REG_WORD(®->mailbox1); |
Chad Dupuis | f73cb69 | 2014-02-26 04:15:06 -0500 | [diff] [blame] | 161 | |
| 162 | WRT_REG_DWORD(®->hccr, |
| 163 | HCCRX_CLR_RISC_INT); |
| 164 | RD_REG_DWORD(®->hccr); |
| 165 | break; |
| 166 | } |
| 167 | |
| 168 | /* Clear this intr; it wasn't a mailbox intr */ |
| 169 | WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); |
| 170 | RD_REG_DWORD(®->hccr); |
| 171 | } |
| 172 | udelay(5); |
| 173 | } |
| 174 | ha->flags.mbox_int = 1; |
| 175 | |
| 176 | if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { |
| 177 | rval = mb0 & MBS_MASK; |
| 178 | for (idx = 0; idx < dwords; idx++) |
| 179 | ram[cnt + idx] = IS_QLA27XX(ha) ? |
| 180 | le32_to_cpu(dump[idx]) : swab32(dump[idx]); |
| 181 | } else { |
| 182 | rval = QLA_FUNCTION_FAILED; |
| 183 | } |
| 184 | } |
| 185 | |
| 186 | *nxt = rval == QLA_SUCCESS ? &ram[cnt] : NULL; |
| 187 | return rval; |
| 188 | } |
| 189 | |
| 190 | int |
Anirban Chakraborty | 7b867cf | 2008-11-06 10:40:19 -0800 | [diff] [blame] | 191 | qla24xx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint32_t *ram, |
Andrew Vasquez | c572270 | 2008-04-24 15:21:22 -0700 | [diff] [blame] | 192 | uint32_t ram_dwords, void **nxt) |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 193 | { |
| 194 | int rval; |
Andrew Vasquez | c572270 | 2008-04-24 15:21:22 -0700 | [diff] [blame] | 195 | uint32_t cnt, stat, timer, dwords, idx; |
| 196 | uint16_t mb0; |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 197 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
Andrew Vasquez | c572270 | 2008-04-24 15:21:22 -0700 | [diff] [blame] | 198 | dma_addr_t dump_dma = ha->gid_list_dma; |
| 199 | uint32_t *dump = (uint32_t *)ha->gid_list; |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 200 | |
| 201 | rval = QLA_SUCCESS; |
Andrew Vasquez | c572270 | 2008-04-24 15:21:22 -0700 | [diff] [blame] | 202 | mb0 = 0; |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 203 | |
Andrew Vasquez | c572270 | 2008-04-24 15:21:22 -0700 | [diff] [blame] | 204 | WRT_REG_WORD(®->mailbox0, MBC_DUMP_RISC_RAM_EXTENDED); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 205 | clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); |
| 206 | |
Chad Dupuis | 642ef98 | 2012-02-09 11:15:57 -0800 | [diff] [blame] | 207 | dwords = qla2x00_gid_list_size(ha) / 4; |
Andrew Vasquez | c572270 | 2008-04-24 15:21:22 -0700 | [diff] [blame] | 208 | for (cnt = 0; cnt < ram_dwords && rval == QLA_SUCCESS; |
| 209 | cnt += dwords, addr += dwords) { |
| 210 | if (cnt + dwords > ram_dwords) |
| 211 | dwords = ram_dwords - cnt; |
| 212 | |
| 213 | WRT_REG_WORD(®->mailbox1, LSW(addr)); |
| 214 | WRT_REG_WORD(®->mailbox8, MSW(addr)); |
| 215 | |
| 216 | WRT_REG_WORD(®->mailbox2, MSW(dump_dma)); |
| 217 | WRT_REG_WORD(®->mailbox3, LSW(dump_dma)); |
| 218 | WRT_REG_WORD(®->mailbox6, MSW(MSD(dump_dma))); |
| 219 | WRT_REG_WORD(®->mailbox7, LSW(MSD(dump_dma))); |
| 220 | |
| 221 | WRT_REG_WORD(®->mailbox4, MSW(dwords)); |
| 222 | WRT_REG_WORD(®->mailbox5, LSW(dwords)); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 223 | WRT_REG_DWORD(®->hccr, HCCRX_SET_HOST_INT); |
| 224 | |
Chad Dupuis | f73cb69 | 2014-02-26 04:15:06 -0500 | [diff] [blame] | 225 | ha->flags.mbox_int = 0; |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 226 | for (timer = 6000000; timer; timer--) { |
| 227 | /* Check for pending interrupts. */ |
| 228 | stat = RD_REG_DWORD(®->host_status); |
| 229 | if (stat & HSRX_RISC_INT) { |
| 230 | stat &= 0xff; |
| 231 | |
| 232 | if (stat == 0x1 || stat == 0x2 || |
| 233 | stat == 0x10 || stat == 0x11) { |
| 234 | set_bit(MBX_INTERRUPT, |
| 235 | &ha->mbx_cmd_flags); |
| 236 | |
Andrew Vasquez | c572270 | 2008-04-24 15:21:22 -0700 | [diff] [blame] | 237 | mb0 = RD_REG_WORD(®->mailbox0); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 238 | |
| 239 | WRT_REG_DWORD(®->hccr, |
| 240 | HCCRX_CLR_RISC_INT); |
| 241 | RD_REG_DWORD(®->hccr); |
| 242 | break; |
| 243 | } |
| 244 | |
| 245 | /* Clear this intr; it wasn't a mailbox intr */ |
| 246 | WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_INT); |
| 247 | RD_REG_DWORD(®->hccr); |
| 248 | } |
| 249 | udelay(5); |
| 250 | } |
Chad Dupuis | f73cb69 | 2014-02-26 04:15:06 -0500 | [diff] [blame] | 251 | ha->flags.mbox_int = 1; |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 252 | |
| 253 | if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { |
Andrew Vasquez | c572270 | 2008-04-24 15:21:22 -0700 | [diff] [blame] | 254 | rval = mb0 & MBS_MASK; |
| 255 | for (idx = 0; idx < dwords; idx++) |
Chad Dupuis | f73cb69 | 2014-02-26 04:15:06 -0500 | [diff] [blame] | 256 | ram[cnt + idx] = IS_QLA27XX(ha) ? |
| 257 | le32_to_cpu(dump[idx]) : swab32(dump[idx]); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 258 | } else { |
| 259 | rval = QLA_FUNCTION_FAILED; |
| 260 | } |
| 261 | } |
| 262 | |
Andrew Vasquez | c572270 | 2008-04-24 15:21:22 -0700 | [diff] [blame] | 263 | *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL; |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 264 | return rval; |
| 265 | } |
| 266 | |
Andrew Vasquez | c572270 | 2008-04-24 15:21:22 -0700 | [diff] [blame] | 267 | static int |
Anirban Chakraborty | 7b867cf | 2008-11-06 10:40:19 -0800 | [diff] [blame] | 268 | qla24xx_dump_memory(struct qla_hw_data *ha, uint32_t *code_ram, |
Andrew Vasquez | c572270 | 2008-04-24 15:21:22 -0700 | [diff] [blame] | 269 | uint32_t cram_size, void **nxt) |
| 270 | { |
| 271 | int rval; |
| 272 | |
| 273 | /* Code RAM. */ |
| 274 | rval = qla24xx_dump_ram(ha, 0x20000, code_ram, cram_size / 4, nxt); |
| 275 | if (rval != QLA_SUCCESS) |
| 276 | return rval; |
| 277 | |
Hiral Patel | 61f098d | 2014-04-11 16:54:21 -0400 | [diff] [blame] | 278 | set_bit(RISC_SRAM_DUMP_CMPL, &ha->fw_dump_cap_flags); |
| 279 | |
Andrew Vasquez | c572270 | 2008-04-24 15:21:22 -0700 | [diff] [blame] | 280 | /* External Memory. */ |
Hiral Patel | 61f098d | 2014-04-11 16:54:21 -0400 | [diff] [blame] | 281 | rval = qla24xx_dump_ram(ha, 0x100000, *nxt, |
Andrew Vasquez | c572270 | 2008-04-24 15:21:22 -0700 | [diff] [blame] | 282 | ha->fw_memory_size - 0x100000 + 1, nxt); |
Hiral Patel | 61f098d | 2014-04-11 16:54:21 -0400 | [diff] [blame] | 283 | if (rval == QLA_SUCCESS) |
| 284 | set_bit(RISC_EXT_MEM_DUMP_CMPL, &ha->fw_dump_cap_flags); |
| 285 | |
| 286 | return rval; |
Andrew Vasquez | c572270 | 2008-04-24 15:21:22 -0700 | [diff] [blame] | 287 | } |
| 288 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 289 | static uint32_t * |
| 290 | qla24xx_read_window(struct device_reg_24xx __iomem *reg, uint32_t iobase, |
| 291 | uint32_t count, uint32_t *buf) |
| 292 | { |
| 293 | uint32_t __iomem *dmp_reg; |
| 294 | |
| 295 | WRT_REG_DWORD(®->iobase_addr, iobase); |
| 296 | dmp_reg = ®->iobase_window; |
Joe Carnuccio | da08ef5 | 2016-01-27 12:03:34 -0500 | [diff] [blame] | 297 | for ( ; count--; dmp_reg++) |
| 298 | *buf++ = htonl(RD_REG_DWORD(dmp_reg)); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 299 | |
| 300 | return buf; |
| 301 | } |
| 302 | |
Hiral Patel | 2f389fc | 2014-04-11 16:54:20 -0400 | [diff] [blame] | 303 | void |
Hiral Patel | 61f098d | 2014-04-11 16:54:21 -0400 | [diff] [blame] | 304 | qla24xx_pause_risc(struct device_reg_24xx __iomem *reg, struct qla_hw_data *ha) |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 305 | { |
Andrew Vasquez | c3b058a | 2007-09-20 14:07:38 -0700 | [diff] [blame] | 306 | WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_PAUSE); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 307 | |
Hiral Patel | 2f389fc | 2014-04-11 16:54:20 -0400 | [diff] [blame] | 308 | /* 100 usec delay is sufficient enough for hardware to pause RISC */ |
| 309 | udelay(100); |
Hiral Patel | 61f098d | 2014-04-11 16:54:21 -0400 | [diff] [blame] | 310 | if (RD_REG_DWORD(®->host_status) & HSRX_RISC_PAUSED) |
| 311 | set_bit(RISC_PAUSE_CMPL, &ha->fw_dump_cap_flags); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 312 | } |
| 313 | |
Chad Dupuis | f73cb69 | 2014-02-26 04:15:06 -0500 | [diff] [blame] | 314 | int |
Anirban Chakraborty | 7b867cf | 2008-11-06 10:40:19 -0800 | [diff] [blame] | 315 | qla24xx_soft_reset(struct qla_hw_data *ha) |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 316 | { |
| 317 | int rval = QLA_SUCCESS; |
| 318 | uint32_t cnt; |
Hiral Patel | 2f389fc | 2014-04-11 16:54:20 -0400 | [diff] [blame] | 319 | uint16_t wd; |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 320 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
| 321 | |
Hiral Patel | 2f389fc | 2014-04-11 16:54:20 -0400 | [diff] [blame] | 322 | /* |
| 323 | * Reset RISC. The delay is dependent on system architecture. |
| 324 | * Driver can proceed with the reset sequence after waiting |
| 325 | * for a timeout period. |
| 326 | */ |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 327 | WRT_REG_DWORD(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); |
| 328 | for (cnt = 0; cnt < 30000; cnt++) { |
| 329 | if ((RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) |
| 330 | break; |
| 331 | |
| 332 | udelay(10); |
| 333 | } |
Hiral Patel | 61f098d | 2014-04-11 16:54:21 -0400 | [diff] [blame] | 334 | if (!(RD_REG_DWORD(®->ctrl_status) & CSRX_DMA_ACTIVE)) |
| 335 | set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 336 | |
| 337 | WRT_REG_DWORD(®->ctrl_status, |
| 338 | CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); |
| 339 | pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); |
| 340 | |
| 341 | udelay(100); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 342 | |
| 343 | /* Wait for soft-reset to complete. */ |
| 344 | for (cnt = 0; cnt < 30000; cnt++) { |
| 345 | if ((RD_REG_DWORD(®->ctrl_status) & |
| 346 | CSRX_ISP_SOFT_RESET) == 0) |
| 347 | break; |
| 348 | |
| 349 | udelay(10); |
| 350 | } |
Hiral Patel | 61f098d | 2014-04-11 16:54:21 -0400 | [diff] [blame] | 351 | if (!(RD_REG_DWORD(®->ctrl_status) & CSRX_ISP_SOFT_RESET)) |
| 352 | set_bit(ISP_RESET_CMPL, &ha->fw_dump_cap_flags); |
| 353 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 354 | WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); |
| 355 | RD_REG_DWORD(®->hccr); /* PCI Posting. */ |
| 356 | |
Hiral Patel | 2f389fc | 2014-04-11 16:54:20 -0400 | [diff] [blame] | 357 | for (cnt = 10000; RD_REG_WORD(®->mailbox0) != 0 && |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 358 | rval == QLA_SUCCESS; cnt--) { |
| 359 | if (cnt) |
Hiral Patel | 2f389fc | 2014-04-11 16:54:20 -0400 | [diff] [blame] | 360 | udelay(10); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 361 | else |
| 362 | rval = QLA_FUNCTION_TIMEOUT; |
| 363 | } |
Hiral Patel | 61f098d | 2014-04-11 16:54:21 -0400 | [diff] [blame] | 364 | if (rval == QLA_SUCCESS) |
| 365 | set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 366 | |
| 367 | return rval; |
| 368 | } |
| 369 | |
Andrew Vasquez | c572270 | 2008-04-24 15:21:22 -0700 | [diff] [blame] | 370 | static int |
Anirban Chakraborty | 7b867cf | 2008-11-06 10:40:19 -0800 | [diff] [blame] | 371 | qla2xxx_dump_ram(struct qla_hw_data *ha, uint32_t addr, uint16_t *ram, |
Andrew Vasquez | e18e963 | 2009-06-17 10:30:31 -0700 | [diff] [blame] | 372 | uint32_t ram_words, void **nxt) |
Andrew Vasquez | c572270 | 2008-04-24 15:21:22 -0700 | [diff] [blame] | 373 | { |
| 374 | int rval; |
| 375 | uint32_t cnt, stat, timer, words, idx; |
| 376 | uint16_t mb0; |
| 377 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
| 378 | dma_addr_t dump_dma = ha->gid_list_dma; |
| 379 | uint16_t *dump = (uint16_t *)ha->gid_list; |
| 380 | |
| 381 | rval = QLA_SUCCESS; |
| 382 | mb0 = 0; |
| 383 | |
| 384 | WRT_MAILBOX_REG(ha, reg, 0, MBC_DUMP_RISC_RAM_EXTENDED); |
| 385 | clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); |
| 386 | |
Chad Dupuis | 642ef98 | 2012-02-09 11:15:57 -0800 | [diff] [blame] | 387 | words = qla2x00_gid_list_size(ha) / 2; |
Andrew Vasquez | c572270 | 2008-04-24 15:21:22 -0700 | [diff] [blame] | 388 | for (cnt = 0; cnt < ram_words && rval == QLA_SUCCESS; |
| 389 | cnt += words, addr += words) { |
| 390 | if (cnt + words > ram_words) |
| 391 | words = ram_words - cnt; |
| 392 | |
| 393 | WRT_MAILBOX_REG(ha, reg, 1, LSW(addr)); |
| 394 | WRT_MAILBOX_REG(ha, reg, 8, MSW(addr)); |
| 395 | |
| 396 | WRT_MAILBOX_REG(ha, reg, 2, MSW(dump_dma)); |
| 397 | WRT_MAILBOX_REG(ha, reg, 3, LSW(dump_dma)); |
| 398 | WRT_MAILBOX_REG(ha, reg, 6, MSW(MSD(dump_dma))); |
| 399 | WRT_MAILBOX_REG(ha, reg, 7, LSW(MSD(dump_dma))); |
| 400 | |
| 401 | WRT_MAILBOX_REG(ha, reg, 4, words); |
| 402 | WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); |
| 403 | |
| 404 | for (timer = 6000000; timer; timer--) { |
| 405 | /* Check for pending interrupts. */ |
| 406 | stat = RD_REG_DWORD(®->u.isp2300.host_status); |
| 407 | if (stat & HSR_RISC_INT) { |
| 408 | stat &= 0xff; |
| 409 | |
| 410 | if (stat == 0x1 || stat == 0x2) { |
| 411 | set_bit(MBX_INTERRUPT, |
| 412 | &ha->mbx_cmd_flags); |
| 413 | |
| 414 | mb0 = RD_MAILBOX_REG(ha, reg, 0); |
| 415 | |
| 416 | /* Release mailbox registers. */ |
| 417 | WRT_REG_WORD(®->semaphore, 0); |
| 418 | WRT_REG_WORD(®->hccr, |
| 419 | HCCR_CLR_RISC_INT); |
| 420 | RD_REG_WORD(®->hccr); |
| 421 | break; |
| 422 | } else if (stat == 0x10 || stat == 0x11) { |
| 423 | set_bit(MBX_INTERRUPT, |
| 424 | &ha->mbx_cmd_flags); |
| 425 | |
| 426 | mb0 = RD_MAILBOX_REG(ha, reg, 0); |
| 427 | |
| 428 | WRT_REG_WORD(®->hccr, |
| 429 | HCCR_CLR_RISC_INT); |
| 430 | RD_REG_WORD(®->hccr); |
| 431 | break; |
| 432 | } |
| 433 | |
| 434 | /* clear this intr; it wasn't a mailbox intr */ |
| 435 | WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); |
| 436 | RD_REG_WORD(®->hccr); |
| 437 | } |
| 438 | udelay(5); |
| 439 | } |
| 440 | |
| 441 | if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { |
| 442 | rval = mb0 & MBS_MASK; |
| 443 | for (idx = 0; idx < words; idx++) |
| 444 | ram[cnt + idx] = swab16(dump[idx]); |
| 445 | } else { |
| 446 | rval = QLA_FUNCTION_FAILED; |
| 447 | } |
| 448 | } |
| 449 | |
| 450 | *nxt = rval == QLA_SUCCESS ? &ram[cnt]: NULL; |
| 451 | return rval; |
| 452 | } |
| 453 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 454 | static inline void |
| 455 | qla2xxx_read_window(struct device_reg_2xxx __iomem *reg, uint32_t count, |
| 456 | uint16_t *buf) |
| 457 | { |
| 458 | uint16_t __iomem *dmp_reg = ®->u.isp2300.fb_cmd; |
| 459 | |
Joe Carnuccio | da08ef5 | 2016-01-27 12:03:34 -0500 | [diff] [blame] | 460 | for ( ; count--; dmp_reg++) |
| 461 | *buf++ = htons(RD_REG_WORD(dmp_reg)); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 462 | } |
| 463 | |
Andrew Vasquez | bb99de6 | 2009-01-05 11:18:08 -0800 | [diff] [blame] | 464 | static inline void * |
| 465 | qla24xx_copy_eft(struct qla_hw_data *ha, void *ptr) |
| 466 | { |
| 467 | if (!ha->eft) |
| 468 | return ptr; |
| 469 | |
| 470 | memcpy(ptr, ha->eft, ntohl(ha->fw_dump->eft_size)); |
| 471 | return ptr + ntohl(ha->fw_dump->eft_size); |
| 472 | } |
| 473 | |
| 474 | static inline void * |
| 475 | qla25xx_copy_fce(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) |
| 476 | { |
| 477 | uint32_t cnt; |
| 478 | uint32_t *iter_reg; |
| 479 | struct qla2xxx_fce_chain *fcec = ptr; |
| 480 | |
| 481 | if (!ha->fce) |
| 482 | return ptr; |
| 483 | |
| 484 | *last_chain = &fcec->type; |
Bart Van Assche | ad95036 | 2015-07-09 07:24:08 -0700 | [diff] [blame] | 485 | fcec->type = htonl(DUMP_CHAIN_FCE); |
Andrew Vasquez | bb99de6 | 2009-01-05 11:18:08 -0800 | [diff] [blame] | 486 | fcec->chain_size = htonl(sizeof(struct qla2xxx_fce_chain) + |
| 487 | fce_calc_size(ha->fce_bufs)); |
| 488 | fcec->size = htonl(fce_calc_size(ha->fce_bufs)); |
| 489 | fcec->addr_l = htonl(LSD(ha->fce_dma)); |
| 490 | fcec->addr_h = htonl(MSD(ha->fce_dma)); |
| 491 | |
| 492 | iter_reg = fcec->eregs; |
| 493 | for (cnt = 0; cnt < 8; cnt++) |
| 494 | *iter_reg++ = htonl(ha->fce_mb[cnt]); |
| 495 | |
| 496 | memcpy(iter_reg, ha->fce, ntohl(fcec->size)); |
| 497 | |
Giridhar Malavali | 3cb0a67 | 2011-11-18 09:03:11 -0800 | [diff] [blame] | 498 | return (char *)iter_reg + ntohl(fcec->size); |
Andrew Vasquez | bb99de6 | 2009-01-05 11:18:08 -0800 | [diff] [blame] | 499 | } |
| 500 | |
Andrew Vasquez | d63ab53 | 2009-01-05 11:18:09 -0800 | [diff] [blame] | 501 | static inline void * |
Quinn Tran | b945e77 | 2017-06-13 20:47:29 -0700 | [diff] [blame] | 502 | qla25xx_copy_exlogin(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) |
| 503 | { |
| 504 | struct qla2xxx_offld_chain *c = ptr; |
| 505 | |
| 506 | if (!ha->exlogin_buf) |
| 507 | return ptr; |
| 508 | |
| 509 | *last_chain = &c->type; |
| 510 | |
| 511 | c->type = cpu_to_be32(DUMP_CHAIN_EXLOGIN); |
| 512 | c->chain_size = cpu_to_be32(sizeof(struct qla2xxx_offld_chain) + |
| 513 | ha->exlogin_size); |
| 514 | c->size = cpu_to_be32(ha->exlogin_size); |
| 515 | c->addr = cpu_to_be64(ha->exlogin_buf_dma); |
| 516 | |
| 517 | ptr += sizeof(struct qla2xxx_offld_chain); |
| 518 | memcpy(ptr, ha->exlogin_buf, ha->exlogin_size); |
| 519 | |
| 520 | return (char *)ptr + cpu_to_be32(c->size); |
| 521 | } |
| 522 | |
| 523 | static inline void * |
| 524 | qla81xx_copy_exchoffld(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) |
| 525 | { |
| 526 | struct qla2xxx_offld_chain *c = ptr; |
| 527 | |
| 528 | if (!ha->exchoffld_buf) |
| 529 | return ptr; |
| 530 | |
| 531 | *last_chain = &c->type; |
| 532 | |
| 533 | c->type = cpu_to_be32(DUMP_CHAIN_EXCHG); |
| 534 | c->chain_size = cpu_to_be32(sizeof(struct qla2xxx_offld_chain) + |
| 535 | ha->exchoffld_size); |
| 536 | c->size = cpu_to_be32(ha->exchoffld_size); |
| 537 | c->addr = cpu_to_be64(ha->exchoffld_buf_dma); |
| 538 | |
| 539 | ptr += sizeof(struct qla2xxx_offld_chain); |
| 540 | memcpy(ptr, ha->exchoffld_buf, ha->exchoffld_size); |
| 541 | |
| 542 | return (char *)ptr + cpu_to_be32(c->size); |
| 543 | } |
| 544 | |
| 545 | static inline void * |
Nicholas Bellinger | 2d70c10 | 2012-05-15 14:34:28 -0400 | [diff] [blame] | 546 | qla2xxx_copy_atioqueues(struct qla_hw_data *ha, void *ptr, |
| 547 | uint32_t **last_chain) |
| 548 | { |
| 549 | struct qla2xxx_mqueue_chain *q; |
| 550 | struct qla2xxx_mqueue_header *qh; |
| 551 | uint32_t num_queues; |
| 552 | int que; |
| 553 | struct { |
| 554 | int length; |
| 555 | void *ring; |
| 556 | } aq, *aqp; |
| 557 | |
Arun Easi | 00876ae | 2013-03-25 02:21:37 -0400 | [diff] [blame] | 558 | if (!ha->tgt.atio_ring) |
Nicholas Bellinger | 2d70c10 | 2012-05-15 14:34:28 -0400 | [diff] [blame] | 559 | return ptr; |
| 560 | |
| 561 | num_queues = 1; |
| 562 | aqp = &aq; |
| 563 | aqp->length = ha->tgt.atio_q_length; |
| 564 | aqp->ring = ha->tgt.atio_ring; |
| 565 | |
| 566 | for (que = 0; que < num_queues; que++) { |
| 567 | /* aqp = ha->atio_q_map[que]; */ |
| 568 | q = ptr; |
| 569 | *last_chain = &q->type; |
Bart Van Assche | ad95036 | 2015-07-09 07:24:08 -0700 | [diff] [blame] | 570 | q->type = htonl(DUMP_CHAIN_QUEUE); |
Nicholas Bellinger | 2d70c10 | 2012-05-15 14:34:28 -0400 | [diff] [blame] | 571 | q->chain_size = htonl( |
| 572 | sizeof(struct qla2xxx_mqueue_chain) + |
| 573 | sizeof(struct qla2xxx_mqueue_header) + |
| 574 | (aqp->length * sizeof(request_t))); |
| 575 | ptr += sizeof(struct qla2xxx_mqueue_chain); |
| 576 | |
| 577 | /* Add header. */ |
| 578 | qh = ptr; |
Bart Van Assche | ad95036 | 2015-07-09 07:24:08 -0700 | [diff] [blame] | 579 | qh->queue = htonl(TYPE_ATIO_QUEUE); |
Nicholas Bellinger | 2d70c10 | 2012-05-15 14:34:28 -0400 | [diff] [blame] | 580 | qh->number = htonl(que); |
| 581 | qh->size = htonl(aqp->length * sizeof(request_t)); |
| 582 | ptr += sizeof(struct qla2xxx_mqueue_header); |
| 583 | |
| 584 | /* Add data. */ |
| 585 | memcpy(ptr, aqp->ring, aqp->length * sizeof(request_t)); |
| 586 | |
| 587 | ptr += aqp->length * sizeof(request_t); |
| 588 | } |
| 589 | |
| 590 | return ptr; |
| 591 | } |
| 592 | |
| 593 | static inline void * |
Giridhar Malavali | 050c9bb | 2012-02-09 11:15:33 -0800 | [diff] [blame] | 594 | qla25xx_copy_mqueues(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) |
| 595 | { |
| 596 | struct qla2xxx_mqueue_chain *q; |
| 597 | struct qla2xxx_mqueue_header *qh; |
| 598 | struct req_que *req; |
| 599 | struct rsp_que *rsp; |
| 600 | int que; |
| 601 | |
| 602 | if (!ha->mqenable) |
| 603 | return ptr; |
| 604 | |
| 605 | /* Request queues */ |
| 606 | for (que = 1; que < ha->max_req_queues; que++) { |
| 607 | req = ha->req_q_map[que]; |
| 608 | if (!req) |
| 609 | break; |
| 610 | |
| 611 | /* Add chain. */ |
| 612 | q = ptr; |
| 613 | *last_chain = &q->type; |
Bart Van Assche | ad95036 | 2015-07-09 07:24:08 -0700 | [diff] [blame] | 614 | q->type = htonl(DUMP_CHAIN_QUEUE); |
Giridhar Malavali | 050c9bb | 2012-02-09 11:15:33 -0800 | [diff] [blame] | 615 | q->chain_size = htonl( |
| 616 | sizeof(struct qla2xxx_mqueue_chain) + |
| 617 | sizeof(struct qla2xxx_mqueue_header) + |
| 618 | (req->length * sizeof(request_t))); |
| 619 | ptr += sizeof(struct qla2xxx_mqueue_chain); |
| 620 | |
| 621 | /* Add header. */ |
| 622 | qh = ptr; |
Bart Van Assche | ad95036 | 2015-07-09 07:24:08 -0700 | [diff] [blame] | 623 | qh->queue = htonl(TYPE_REQUEST_QUEUE); |
Giridhar Malavali | 050c9bb | 2012-02-09 11:15:33 -0800 | [diff] [blame] | 624 | qh->number = htonl(que); |
| 625 | qh->size = htonl(req->length * sizeof(request_t)); |
| 626 | ptr += sizeof(struct qla2xxx_mqueue_header); |
| 627 | |
| 628 | /* Add data. */ |
| 629 | memcpy(ptr, req->ring, req->length * sizeof(request_t)); |
| 630 | ptr += req->length * sizeof(request_t); |
| 631 | } |
| 632 | |
| 633 | /* Response queues */ |
| 634 | for (que = 1; que < ha->max_rsp_queues; que++) { |
| 635 | rsp = ha->rsp_q_map[que]; |
| 636 | if (!rsp) |
| 637 | break; |
| 638 | |
| 639 | /* Add chain. */ |
| 640 | q = ptr; |
| 641 | *last_chain = &q->type; |
Bart Van Assche | ad95036 | 2015-07-09 07:24:08 -0700 | [diff] [blame] | 642 | q->type = htonl(DUMP_CHAIN_QUEUE); |
Giridhar Malavali | 050c9bb | 2012-02-09 11:15:33 -0800 | [diff] [blame] | 643 | q->chain_size = htonl( |
| 644 | sizeof(struct qla2xxx_mqueue_chain) + |
| 645 | sizeof(struct qla2xxx_mqueue_header) + |
| 646 | (rsp->length * sizeof(response_t))); |
| 647 | ptr += sizeof(struct qla2xxx_mqueue_chain); |
| 648 | |
| 649 | /* Add header. */ |
| 650 | qh = ptr; |
Bart Van Assche | ad95036 | 2015-07-09 07:24:08 -0700 | [diff] [blame] | 651 | qh->queue = htonl(TYPE_RESPONSE_QUEUE); |
Giridhar Malavali | 050c9bb | 2012-02-09 11:15:33 -0800 | [diff] [blame] | 652 | qh->number = htonl(que); |
| 653 | qh->size = htonl(rsp->length * sizeof(response_t)); |
| 654 | ptr += sizeof(struct qla2xxx_mqueue_header); |
| 655 | |
| 656 | /* Add data. */ |
| 657 | memcpy(ptr, rsp->ring, rsp->length * sizeof(response_t)); |
| 658 | ptr += rsp->length * sizeof(response_t); |
| 659 | } |
| 660 | |
| 661 | return ptr; |
| 662 | } |
| 663 | |
| 664 | static inline void * |
Andrew Vasquez | d63ab53 | 2009-01-05 11:18:09 -0800 | [diff] [blame] | 665 | qla25xx_copy_mq(struct qla_hw_data *ha, void *ptr, uint32_t **last_chain) |
| 666 | { |
| 667 | uint32_t cnt, que_idx; |
Anirban Chakraborty | 2afa19a | 2009-04-06 22:33:40 -0700 | [diff] [blame] | 668 | uint8_t que_cnt; |
Andrew Vasquez | d63ab53 | 2009-01-05 11:18:09 -0800 | [diff] [blame] | 669 | struct qla2xxx_mq_chain *mq = ptr; |
Bart Van Assche | 118e2ef | 2015-07-09 07:24:27 -0700 | [diff] [blame] | 670 | device_reg_t *reg; |
Andrew Vasquez | d63ab53 | 2009-01-05 11:18:09 -0800 | [diff] [blame] | 671 | |
Chad Dupuis | f73cb69 | 2014-02-26 04:15:06 -0500 | [diff] [blame] | 672 | if (!ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) |
Andrew Vasquez | d63ab53 | 2009-01-05 11:18:09 -0800 | [diff] [blame] | 673 | return ptr; |
| 674 | |
| 675 | mq = ptr; |
| 676 | *last_chain = &mq->type; |
Bart Van Assche | ad95036 | 2015-07-09 07:24:08 -0700 | [diff] [blame] | 677 | mq->type = htonl(DUMP_CHAIN_MQ); |
| 678 | mq->chain_size = htonl(sizeof(struct qla2xxx_mq_chain)); |
Andrew Vasquez | d63ab53 | 2009-01-05 11:18:09 -0800 | [diff] [blame] | 679 | |
Anirban Chakraborty | 2afa19a | 2009-04-06 22:33:40 -0700 | [diff] [blame] | 680 | que_cnt = ha->max_req_queues > ha->max_rsp_queues ? |
| 681 | ha->max_req_queues : ha->max_rsp_queues; |
Andrew Vasquez | d63ab53 | 2009-01-05 11:18:09 -0800 | [diff] [blame] | 682 | mq->count = htonl(que_cnt); |
| 683 | for (cnt = 0; cnt < que_cnt; cnt++) { |
Andrew Vasquez | da9b1d5 | 2013-08-27 01:37:30 -0400 | [diff] [blame] | 684 | reg = ISP_QUE_REG(ha, cnt); |
Andrew Vasquez | d63ab53 | 2009-01-05 11:18:09 -0800 | [diff] [blame] | 685 | que_idx = cnt * 4; |
Andrew Vasquez | da9b1d5 | 2013-08-27 01:37:30 -0400 | [diff] [blame] | 686 | mq->qregs[que_idx] = |
| 687 | htonl(RD_REG_DWORD(®->isp25mq.req_q_in)); |
| 688 | mq->qregs[que_idx+1] = |
| 689 | htonl(RD_REG_DWORD(®->isp25mq.req_q_out)); |
| 690 | mq->qregs[que_idx+2] = |
| 691 | htonl(RD_REG_DWORD(®->isp25mq.rsp_q_in)); |
| 692 | mq->qregs[que_idx+3] = |
| 693 | htonl(RD_REG_DWORD(®->isp25mq.rsp_q_out)); |
Andrew Vasquez | d63ab53 | 2009-01-05 11:18:09 -0800 | [diff] [blame] | 694 | } |
| 695 | |
| 696 | return ptr + sizeof(struct qla2xxx_mq_chain); |
| 697 | } |
| 698 | |
Giridhar Malavali | 08de284 | 2011-08-16 11:31:44 -0700 | [diff] [blame] | 699 | void |
Andrew Vasquez | 3420d36 | 2009-10-13 15:16:45 -0700 | [diff] [blame] | 700 | qla2xxx_dump_post_process(scsi_qla_host_t *vha, int rval) |
| 701 | { |
| 702 | struct qla_hw_data *ha = vha->hw; |
| 703 | |
| 704 | if (rval != QLA_SUCCESS) { |
Saurav Kashyap | 7c3df13 | 2011-07-14 12:00:13 -0700 | [diff] [blame] | 705 | ql_log(ql_log_warn, vha, 0xd000, |
Hiral Patel | 61f098d | 2014-04-11 16:54:21 -0400 | [diff] [blame] | 706 | "Failed to dump firmware (%x), dump status flags (0x%lx).\n", |
| 707 | rval, ha->fw_dump_cap_flags); |
Andrew Vasquez | 3420d36 | 2009-10-13 15:16:45 -0700 | [diff] [blame] | 708 | ha->fw_dumped = 0; |
| 709 | } else { |
Saurav Kashyap | 7c3df13 | 2011-07-14 12:00:13 -0700 | [diff] [blame] | 710 | ql_log(ql_log_info, vha, 0xd001, |
Hiral Patel | 61f098d | 2014-04-11 16:54:21 -0400 | [diff] [blame] | 711 | "Firmware dump saved to temp buffer (%ld/%p), dump status flags (0x%lx).\n", |
| 712 | vha->host_no, ha->fw_dump, ha->fw_dump_cap_flags); |
Andrew Vasquez | 3420d36 | 2009-10-13 15:16:45 -0700 | [diff] [blame] | 713 | ha->fw_dumped = 1; |
| 714 | qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); |
| 715 | } |
| 716 | } |
| 717 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 718 | /** |
| 719 | * qla2300_fw_dump() - Dumps binary data from the 2300 firmware. |
| 720 | * @ha: HA context |
| 721 | * @hardware_locked: Called with the hardware_lock |
| 722 | */ |
| 723 | void |
Anirban Chakraborty | 7b867cf | 2008-11-06 10:40:19 -0800 | [diff] [blame] | 724 | qla2300_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 725 | { |
| 726 | int rval; |
Andrew Vasquez | c572270 | 2008-04-24 15:21:22 -0700 | [diff] [blame] | 727 | uint32_t cnt; |
Anirban Chakraborty | 7b867cf | 2008-11-06 10:40:19 -0800 | [diff] [blame] | 728 | struct qla_hw_data *ha = vha->hw; |
Andrew Vasquez | 3d71644 | 2005-07-06 10:30:26 -0700 | [diff] [blame] | 729 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 730 | uint16_t __iomem *dmp_reg; |
| 731 | unsigned long flags; |
| 732 | struct qla2300_fw_dump *fw; |
Andrew Vasquez | c572270 | 2008-04-24 15:21:22 -0700 | [diff] [blame] | 733 | void *nxt; |
Anirban Chakraborty | 73208df | 2008-12-09 16:45:39 -0800 | [diff] [blame] | 734 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 735 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 736 | flags = 0; |
| 737 | |
Bart Van Assche | 8d16366 | 2015-07-09 07:25:46 -0700 | [diff] [blame] | 738 | #ifndef __CHECKER__ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 739 | if (!hardware_locked) |
| 740 | spin_lock_irqsave(&ha->hardware_lock, flags); |
Bart Van Assche | 8d16366 | 2015-07-09 07:25:46 -0700 | [diff] [blame] | 741 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 742 | |
Andrew Vasquez | d4e3e04 | 2006-05-17 15:09:50 -0700 | [diff] [blame] | 743 | if (!ha->fw_dump) { |
Saurav Kashyap | 7c3df13 | 2011-07-14 12:00:13 -0700 | [diff] [blame] | 744 | ql_log(ql_log_warn, vha, 0xd002, |
| 745 | "No buffer available for dump.\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 746 | goto qla2300_fw_dump_failed; |
| 747 | } |
| 748 | |
Andrew Vasquez | d4e3e04 | 2006-05-17 15:09:50 -0700 | [diff] [blame] | 749 | if (ha->fw_dumped) { |
Saurav Kashyap | 7c3df13 | 2011-07-14 12:00:13 -0700 | [diff] [blame] | 750 | ql_log(ql_log_warn, vha, 0xd003, |
| 751 | "Firmware has been previously dumped (%p) " |
| 752 | "-- ignoring request.\n", |
| 753 | ha->fw_dump); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 754 | goto qla2300_fw_dump_failed; |
| 755 | } |
Andrew Vasquez | a7a167b | 2006-06-23 16:10:29 -0700 | [diff] [blame] | 756 | fw = &ha->fw_dump->isp.isp23; |
| 757 | qla2xxx_prep_dump(ha, ha->fw_dump); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 758 | |
| 759 | rval = QLA_SUCCESS; |
Andrew Vasquez | a7a167b | 2006-06-23 16:10:29 -0700 | [diff] [blame] | 760 | fw->hccr = htons(RD_REG_WORD(®->hccr)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 761 | |
| 762 | /* Pause RISC. */ |
Andrew Vasquez | fa2a1ce | 2005-07-06 10:32:07 -0700 | [diff] [blame] | 763 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 764 | if (IS_QLA2300(ha)) { |
| 765 | for (cnt = 30000; |
| 766 | (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && |
| 767 | rval == QLA_SUCCESS; cnt--) { |
| 768 | if (cnt) |
| 769 | udelay(100); |
| 770 | else |
| 771 | rval = QLA_FUNCTION_TIMEOUT; |
| 772 | } |
| 773 | } else { |
| 774 | RD_REG_WORD(®->hccr); /* PCI Posting. */ |
| 775 | udelay(10); |
| 776 | } |
| 777 | |
| 778 | if (rval == QLA_SUCCESS) { |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 779 | dmp_reg = ®->flash_address; |
Joe Carnuccio | da08ef5 | 2016-01-27 12:03:34 -0500 | [diff] [blame] | 780 | for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++, dmp_reg++) |
| 781 | fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 782 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 783 | dmp_reg = ®->u.isp2300.req_q_in; |
Joe Carnuccio | da08ef5 | 2016-01-27 12:03:34 -0500 | [diff] [blame] | 784 | for (cnt = 0; cnt < sizeof(fw->risc_host_reg) / 2; |
| 785 | cnt++, dmp_reg++) |
| 786 | fw->risc_host_reg[cnt] = htons(RD_REG_WORD(dmp_reg)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 787 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 788 | dmp_reg = ®->u.isp2300.mailbox0; |
Joe Carnuccio | da08ef5 | 2016-01-27 12:03:34 -0500 | [diff] [blame] | 789 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; |
| 790 | cnt++, dmp_reg++) |
| 791 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 792 | |
| 793 | WRT_REG_WORD(®->ctrl_status, 0x40); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 794 | qla2xxx_read_window(reg, 32, fw->resp_dma_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 795 | |
| 796 | WRT_REG_WORD(®->ctrl_status, 0x50); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 797 | qla2xxx_read_window(reg, 48, fw->dma_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 798 | |
| 799 | WRT_REG_WORD(®->ctrl_status, 0x00); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 800 | dmp_reg = ®->risc_hw; |
Joe Carnuccio | da08ef5 | 2016-01-27 12:03:34 -0500 | [diff] [blame] | 801 | for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; |
| 802 | cnt++, dmp_reg++) |
| 803 | fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 804 | |
Andrew Vasquez | fa2a1ce | 2005-07-06 10:32:07 -0700 | [diff] [blame] | 805 | WRT_REG_WORD(®->pcr, 0x2000); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 806 | qla2xxx_read_window(reg, 16, fw->risc_gp0_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 807 | |
Andrew Vasquez | fa2a1ce | 2005-07-06 10:32:07 -0700 | [diff] [blame] | 808 | WRT_REG_WORD(®->pcr, 0x2200); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 809 | qla2xxx_read_window(reg, 16, fw->risc_gp1_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 810 | |
Andrew Vasquez | fa2a1ce | 2005-07-06 10:32:07 -0700 | [diff] [blame] | 811 | WRT_REG_WORD(®->pcr, 0x2400); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 812 | qla2xxx_read_window(reg, 16, fw->risc_gp2_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 813 | |
Andrew Vasquez | fa2a1ce | 2005-07-06 10:32:07 -0700 | [diff] [blame] | 814 | WRT_REG_WORD(®->pcr, 0x2600); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 815 | qla2xxx_read_window(reg, 16, fw->risc_gp3_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 816 | |
Andrew Vasquez | fa2a1ce | 2005-07-06 10:32:07 -0700 | [diff] [blame] | 817 | WRT_REG_WORD(®->pcr, 0x2800); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 818 | qla2xxx_read_window(reg, 16, fw->risc_gp4_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 819 | |
Andrew Vasquez | fa2a1ce | 2005-07-06 10:32:07 -0700 | [diff] [blame] | 820 | WRT_REG_WORD(®->pcr, 0x2A00); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 821 | qla2xxx_read_window(reg, 16, fw->risc_gp5_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 822 | |
Andrew Vasquez | fa2a1ce | 2005-07-06 10:32:07 -0700 | [diff] [blame] | 823 | WRT_REG_WORD(®->pcr, 0x2C00); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 824 | qla2xxx_read_window(reg, 16, fw->risc_gp6_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 825 | |
Andrew Vasquez | fa2a1ce | 2005-07-06 10:32:07 -0700 | [diff] [blame] | 826 | WRT_REG_WORD(®->pcr, 0x2E00); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 827 | qla2xxx_read_window(reg, 16, fw->risc_gp7_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 828 | |
Andrew Vasquez | fa2a1ce | 2005-07-06 10:32:07 -0700 | [diff] [blame] | 829 | WRT_REG_WORD(®->ctrl_status, 0x10); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 830 | qla2xxx_read_window(reg, 64, fw->frame_buf_hdw_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 831 | |
Andrew Vasquez | fa2a1ce | 2005-07-06 10:32:07 -0700 | [diff] [blame] | 832 | WRT_REG_WORD(®->ctrl_status, 0x20); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 833 | qla2xxx_read_window(reg, 64, fw->fpm_b0_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 834 | |
Andrew Vasquez | fa2a1ce | 2005-07-06 10:32:07 -0700 | [diff] [blame] | 835 | WRT_REG_WORD(®->ctrl_status, 0x30); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 836 | qla2xxx_read_window(reg, 64, fw->fpm_b1_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 837 | |
| 838 | /* Reset RISC. */ |
| 839 | WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); |
| 840 | for (cnt = 0; cnt < 30000; cnt++) { |
| 841 | if ((RD_REG_WORD(®->ctrl_status) & |
| 842 | CSR_ISP_SOFT_RESET) == 0) |
| 843 | break; |
| 844 | |
| 845 | udelay(10); |
| 846 | } |
| 847 | } |
| 848 | |
| 849 | if (!IS_QLA2300(ha)) { |
| 850 | for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && |
| 851 | rval == QLA_SUCCESS; cnt--) { |
| 852 | if (cnt) |
| 853 | udelay(100); |
| 854 | else |
| 855 | rval = QLA_FUNCTION_TIMEOUT; |
| 856 | } |
| 857 | } |
| 858 | |
Andrew Vasquez | c572270 | 2008-04-24 15:21:22 -0700 | [diff] [blame] | 859 | /* Get RISC SRAM. */ |
| 860 | if (rval == QLA_SUCCESS) |
| 861 | rval = qla2xxx_dump_ram(ha, 0x800, fw->risc_ram, |
| 862 | sizeof(fw->risc_ram) / 2, &nxt); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 863 | |
Andrew Vasquez | c572270 | 2008-04-24 15:21:22 -0700 | [diff] [blame] | 864 | /* Get stack SRAM. */ |
| 865 | if (rval == QLA_SUCCESS) |
| 866 | rval = qla2xxx_dump_ram(ha, 0x10000, fw->stack_ram, |
| 867 | sizeof(fw->stack_ram) / 2, &nxt); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 868 | |
Andrew Vasquez | c572270 | 2008-04-24 15:21:22 -0700 | [diff] [blame] | 869 | /* Get data SRAM. */ |
| 870 | if (rval == QLA_SUCCESS) |
| 871 | rval = qla2xxx_dump_ram(ha, 0x11000, fw->data_ram, |
| 872 | ha->fw_memory_size - 0x11000 + 1, &nxt); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 873 | |
Andrew Vasquez | a7a167b | 2006-06-23 16:10:29 -0700 | [diff] [blame] | 874 | if (rval == QLA_SUCCESS) |
Anirban Chakraborty | 73208df | 2008-12-09 16:45:39 -0800 | [diff] [blame] | 875 | qla2xxx_copy_queues(ha, nxt); |
Andrew Vasquez | a7a167b | 2006-06-23 16:10:29 -0700 | [diff] [blame] | 876 | |
Andrew Vasquez | 3420d36 | 2009-10-13 15:16:45 -0700 | [diff] [blame] | 877 | qla2xxx_dump_post_process(base_vha, rval); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 878 | |
| 879 | qla2300_fw_dump_failed: |
Bart Van Assche | 8d16366 | 2015-07-09 07:25:46 -0700 | [diff] [blame] | 880 | #ifndef __CHECKER__ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 881 | if (!hardware_locked) |
| 882 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
Bart Van Assche | 8d16366 | 2015-07-09 07:25:46 -0700 | [diff] [blame] | 883 | #else |
| 884 | ; |
| 885 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 886 | } |
| 887 | |
| 888 | /** |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 889 | * qla2100_fw_dump() - Dumps binary data from the 2100/2200 firmware. |
| 890 | * @ha: HA context |
| 891 | * @hardware_locked: Called with the hardware_lock |
| 892 | */ |
| 893 | void |
Anirban Chakraborty | 7b867cf | 2008-11-06 10:40:19 -0800 | [diff] [blame] | 894 | qla2100_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 895 | { |
| 896 | int rval; |
| 897 | uint32_t cnt, timer; |
| 898 | uint16_t risc_address; |
| 899 | uint16_t mb0, mb2; |
Anirban Chakraborty | 7b867cf | 2008-11-06 10:40:19 -0800 | [diff] [blame] | 900 | struct qla_hw_data *ha = vha->hw; |
Andrew Vasquez | 3d71644 | 2005-07-06 10:30:26 -0700 | [diff] [blame] | 901 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 902 | uint16_t __iomem *dmp_reg; |
| 903 | unsigned long flags; |
| 904 | struct qla2100_fw_dump *fw; |
Anirban Chakraborty | 73208df | 2008-12-09 16:45:39 -0800 | [diff] [blame] | 905 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 906 | |
| 907 | risc_address = 0; |
| 908 | mb0 = mb2 = 0; |
| 909 | flags = 0; |
| 910 | |
Bart Van Assche | 8d16366 | 2015-07-09 07:25:46 -0700 | [diff] [blame] | 911 | #ifndef __CHECKER__ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 912 | if (!hardware_locked) |
| 913 | spin_lock_irqsave(&ha->hardware_lock, flags); |
Bart Van Assche | 8d16366 | 2015-07-09 07:25:46 -0700 | [diff] [blame] | 914 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 915 | |
Andrew Vasquez | d4e3e04 | 2006-05-17 15:09:50 -0700 | [diff] [blame] | 916 | if (!ha->fw_dump) { |
Saurav Kashyap | 7c3df13 | 2011-07-14 12:00:13 -0700 | [diff] [blame] | 917 | ql_log(ql_log_warn, vha, 0xd004, |
| 918 | "No buffer available for dump.\n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 919 | goto qla2100_fw_dump_failed; |
| 920 | } |
| 921 | |
Andrew Vasquez | d4e3e04 | 2006-05-17 15:09:50 -0700 | [diff] [blame] | 922 | if (ha->fw_dumped) { |
Saurav Kashyap | 7c3df13 | 2011-07-14 12:00:13 -0700 | [diff] [blame] | 923 | ql_log(ql_log_warn, vha, 0xd005, |
| 924 | "Firmware has been previously dumped (%p) " |
| 925 | "-- ignoring request.\n", |
| 926 | ha->fw_dump); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 927 | goto qla2100_fw_dump_failed; |
| 928 | } |
Andrew Vasquez | a7a167b | 2006-06-23 16:10:29 -0700 | [diff] [blame] | 929 | fw = &ha->fw_dump->isp.isp21; |
| 930 | qla2xxx_prep_dump(ha, ha->fw_dump); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 931 | |
| 932 | rval = QLA_SUCCESS; |
Andrew Vasquez | a7a167b | 2006-06-23 16:10:29 -0700 | [diff] [blame] | 933 | fw->hccr = htons(RD_REG_WORD(®->hccr)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 934 | |
| 935 | /* Pause RISC. */ |
Andrew Vasquez | fa2a1ce | 2005-07-06 10:32:07 -0700 | [diff] [blame] | 936 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 937 | for (cnt = 30000; (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && |
| 938 | rval == QLA_SUCCESS; cnt--) { |
| 939 | if (cnt) |
| 940 | udelay(100); |
| 941 | else |
| 942 | rval = QLA_FUNCTION_TIMEOUT; |
| 943 | } |
| 944 | if (rval == QLA_SUCCESS) { |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 945 | dmp_reg = ®->flash_address; |
Joe Carnuccio | da08ef5 | 2016-01-27 12:03:34 -0500 | [diff] [blame] | 946 | for (cnt = 0; cnt < sizeof(fw->pbiu_reg) / 2; cnt++, dmp_reg++) |
| 947 | fw->pbiu_reg[cnt] = htons(RD_REG_WORD(dmp_reg)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 948 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 949 | dmp_reg = ®->u.isp2100.mailbox0; |
Joe Carnuccio | da08ef5 | 2016-01-27 12:03:34 -0500 | [diff] [blame] | 950 | for (cnt = 0; cnt < ha->mbx_count; cnt++, dmp_reg++) { |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 951 | if (cnt == 8) |
| 952 | dmp_reg = ®->u_end.isp2200.mailbox8; |
| 953 | |
Joe Carnuccio | da08ef5 | 2016-01-27 12:03:34 -0500 | [diff] [blame] | 954 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(dmp_reg)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 955 | } |
| 956 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 957 | dmp_reg = ®->u.isp2100.unused_2[0]; |
Joe Carnuccio | da08ef5 | 2016-01-27 12:03:34 -0500 | [diff] [blame] | 958 | for (cnt = 0; cnt < sizeof(fw->dma_reg) / 2; cnt++, dmp_reg++) |
| 959 | fw->dma_reg[cnt] = htons(RD_REG_WORD(dmp_reg)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 960 | |
| 961 | WRT_REG_WORD(®->ctrl_status, 0x00); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 962 | dmp_reg = ®->risc_hw; |
Joe Carnuccio | da08ef5 | 2016-01-27 12:03:34 -0500 | [diff] [blame] | 963 | for (cnt = 0; cnt < sizeof(fw->risc_hdw_reg) / 2; cnt++, dmp_reg++) |
| 964 | fw->risc_hdw_reg[cnt] = htons(RD_REG_WORD(dmp_reg)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 965 | |
Andrew Vasquez | fa2a1ce | 2005-07-06 10:32:07 -0700 | [diff] [blame] | 966 | WRT_REG_WORD(®->pcr, 0x2000); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 967 | qla2xxx_read_window(reg, 16, fw->risc_gp0_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 968 | |
Andrew Vasquez | fa2a1ce | 2005-07-06 10:32:07 -0700 | [diff] [blame] | 969 | WRT_REG_WORD(®->pcr, 0x2100); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 970 | qla2xxx_read_window(reg, 16, fw->risc_gp1_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 971 | |
Andrew Vasquez | fa2a1ce | 2005-07-06 10:32:07 -0700 | [diff] [blame] | 972 | WRT_REG_WORD(®->pcr, 0x2200); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 973 | qla2xxx_read_window(reg, 16, fw->risc_gp2_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 974 | |
Andrew Vasquez | fa2a1ce | 2005-07-06 10:32:07 -0700 | [diff] [blame] | 975 | WRT_REG_WORD(®->pcr, 0x2300); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 976 | qla2xxx_read_window(reg, 16, fw->risc_gp3_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 977 | |
Andrew Vasquez | fa2a1ce | 2005-07-06 10:32:07 -0700 | [diff] [blame] | 978 | WRT_REG_WORD(®->pcr, 0x2400); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 979 | qla2xxx_read_window(reg, 16, fw->risc_gp4_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 980 | |
Andrew Vasquez | fa2a1ce | 2005-07-06 10:32:07 -0700 | [diff] [blame] | 981 | WRT_REG_WORD(®->pcr, 0x2500); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 982 | qla2xxx_read_window(reg, 16, fw->risc_gp5_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 983 | |
Andrew Vasquez | fa2a1ce | 2005-07-06 10:32:07 -0700 | [diff] [blame] | 984 | WRT_REG_WORD(®->pcr, 0x2600); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 985 | qla2xxx_read_window(reg, 16, fw->risc_gp6_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 986 | |
Andrew Vasquez | fa2a1ce | 2005-07-06 10:32:07 -0700 | [diff] [blame] | 987 | WRT_REG_WORD(®->pcr, 0x2700); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 988 | qla2xxx_read_window(reg, 16, fw->risc_gp7_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 989 | |
Andrew Vasquez | fa2a1ce | 2005-07-06 10:32:07 -0700 | [diff] [blame] | 990 | WRT_REG_WORD(®->ctrl_status, 0x10); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 991 | qla2xxx_read_window(reg, 16, fw->frame_buf_hdw_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 992 | |
Andrew Vasquez | fa2a1ce | 2005-07-06 10:32:07 -0700 | [diff] [blame] | 993 | WRT_REG_WORD(®->ctrl_status, 0x20); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 994 | qla2xxx_read_window(reg, 64, fw->fpm_b0_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 995 | |
Andrew Vasquez | fa2a1ce | 2005-07-06 10:32:07 -0700 | [diff] [blame] | 996 | WRT_REG_WORD(®->ctrl_status, 0x30); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 997 | qla2xxx_read_window(reg, 64, fw->fpm_b1_reg); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 998 | |
| 999 | /* Reset the ISP. */ |
| 1000 | WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET); |
| 1001 | } |
| 1002 | |
| 1003 | for (cnt = 30000; RD_MAILBOX_REG(ha, reg, 0) != 0 && |
| 1004 | rval == QLA_SUCCESS; cnt--) { |
| 1005 | if (cnt) |
| 1006 | udelay(100); |
| 1007 | else |
| 1008 | rval = QLA_FUNCTION_TIMEOUT; |
| 1009 | } |
| 1010 | |
| 1011 | /* Pause RISC. */ |
| 1012 | if (rval == QLA_SUCCESS && (IS_QLA2200(ha) || (IS_QLA2100(ha) && |
| 1013 | (RD_REG_WORD(®->mctr) & (BIT_1 | BIT_0)) != 0))) { |
| 1014 | |
Andrew Vasquez | fa2a1ce | 2005-07-06 10:32:07 -0700 | [diff] [blame] | 1015 | WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1016 | for (cnt = 30000; |
| 1017 | (RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) == 0 && |
| 1018 | rval == QLA_SUCCESS; cnt--) { |
| 1019 | if (cnt) |
| 1020 | udelay(100); |
| 1021 | else |
| 1022 | rval = QLA_FUNCTION_TIMEOUT; |
| 1023 | } |
| 1024 | if (rval == QLA_SUCCESS) { |
| 1025 | /* Set memory configuration and timing. */ |
| 1026 | if (IS_QLA2100(ha)) |
| 1027 | WRT_REG_WORD(®->mctr, 0xf1); |
| 1028 | else |
| 1029 | WRT_REG_WORD(®->mctr, 0xf2); |
| 1030 | RD_REG_WORD(®->mctr); /* PCI Posting. */ |
| 1031 | |
| 1032 | /* Release RISC. */ |
| 1033 | WRT_REG_WORD(®->hccr, HCCR_RELEASE_RISC); |
| 1034 | } |
| 1035 | } |
| 1036 | |
| 1037 | if (rval == QLA_SUCCESS) { |
| 1038 | /* Get RISC SRAM. */ |
| 1039 | risc_address = 0x1000; |
| 1040 | WRT_MAILBOX_REG(ha, reg, 0, MBC_READ_RAM_WORD); |
| 1041 | clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags); |
| 1042 | } |
| 1043 | for (cnt = 0; cnt < sizeof(fw->risc_ram) / 2 && rval == QLA_SUCCESS; |
| 1044 | cnt++, risc_address++) { |
| 1045 | WRT_MAILBOX_REG(ha, reg, 1, risc_address); |
| 1046 | WRT_REG_WORD(®->hccr, HCCR_SET_HOST_INT); |
| 1047 | |
| 1048 | for (timer = 6000000; timer != 0; timer--) { |
| 1049 | /* Check for pending interrupts. */ |
| 1050 | if (RD_REG_WORD(®->istatus) & ISR_RISC_INT) { |
| 1051 | if (RD_REG_WORD(®->semaphore) & BIT_0) { |
| 1052 | set_bit(MBX_INTERRUPT, |
| 1053 | &ha->mbx_cmd_flags); |
| 1054 | |
| 1055 | mb0 = RD_MAILBOX_REG(ha, reg, 0); |
| 1056 | mb2 = RD_MAILBOX_REG(ha, reg, 2); |
| 1057 | |
| 1058 | WRT_REG_WORD(®->semaphore, 0); |
| 1059 | WRT_REG_WORD(®->hccr, |
| 1060 | HCCR_CLR_RISC_INT); |
| 1061 | RD_REG_WORD(®->hccr); |
| 1062 | break; |
| 1063 | } |
| 1064 | WRT_REG_WORD(®->hccr, HCCR_CLR_RISC_INT); |
| 1065 | RD_REG_WORD(®->hccr); |
| 1066 | } |
| 1067 | udelay(5); |
| 1068 | } |
| 1069 | |
| 1070 | if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags)) { |
| 1071 | rval = mb0 & MBS_MASK; |
Andrew Vasquez | a7a167b | 2006-06-23 16:10:29 -0700 | [diff] [blame] | 1072 | fw->risc_ram[cnt] = htons(mb2); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1073 | } else { |
| 1074 | rval = QLA_FUNCTION_FAILED; |
| 1075 | } |
| 1076 | } |
| 1077 | |
Andrew Vasquez | a7a167b | 2006-06-23 16:10:29 -0700 | [diff] [blame] | 1078 | if (rval == QLA_SUCCESS) |
Anirban Chakraborty | 73208df | 2008-12-09 16:45:39 -0800 | [diff] [blame] | 1079 | qla2xxx_copy_queues(ha, &fw->risc_ram[cnt]); |
Andrew Vasquez | a7a167b | 2006-06-23 16:10:29 -0700 | [diff] [blame] | 1080 | |
Andrew Vasquez | 3420d36 | 2009-10-13 15:16:45 -0700 | [diff] [blame] | 1081 | qla2xxx_dump_post_process(base_vha, rval); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1082 | |
| 1083 | qla2100_fw_dump_failed: |
Bart Van Assche | 8d16366 | 2015-07-09 07:25:46 -0700 | [diff] [blame] | 1084 | #ifndef __CHECKER__ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1085 | if (!hardware_locked) |
| 1086 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
Bart Van Assche | 8d16366 | 2015-07-09 07:25:46 -0700 | [diff] [blame] | 1087 | #else |
| 1088 | ; |
| 1089 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1090 | } |
| 1091 | |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1092 | void |
Anirban Chakraborty | 7b867cf | 2008-11-06 10:40:19 -0800 | [diff] [blame] | 1093 | qla24xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1094 | { |
| 1095 | int rval; |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1096 | uint32_t cnt; |
Anirban Chakraborty | 7b867cf | 2008-11-06 10:40:19 -0800 | [diff] [blame] | 1097 | struct qla_hw_data *ha = vha->hw; |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1098 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
| 1099 | uint32_t __iomem *dmp_reg; |
| 1100 | uint32_t *iter_reg; |
| 1101 | uint16_t __iomem *mbx_reg; |
| 1102 | unsigned long flags; |
| 1103 | struct qla24xx_fw_dump *fw; |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1104 | void *nxt; |
Nicholas Bellinger | 2d70c10 | 2012-05-15 14:34:28 -0400 | [diff] [blame] | 1105 | void *nxt_chain; |
| 1106 | uint32_t *last_chain = NULL; |
Anirban Chakraborty | 73208df | 2008-12-09 16:45:39 -0800 | [diff] [blame] | 1107 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1108 | |
Atul Deshmukh | 7ec0eff | 2013-08-27 01:37:28 -0400 | [diff] [blame] | 1109 | if (IS_P3P_TYPE(ha)) |
Giridhar Malavali | a908301 | 2010-04-12 17:59:55 -0700 | [diff] [blame] | 1110 | return; |
| 1111 | |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1112 | flags = 0; |
Hiral Patel | 61f098d | 2014-04-11 16:54:21 -0400 | [diff] [blame] | 1113 | ha->fw_dump_cap_flags = 0; |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1114 | |
Bart Van Assche | 8d16366 | 2015-07-09 07:25:46 -0700 | [diff] [blame] | 1115 | #ifndef __CHECKER__ |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1116 | if (!hardware_locked) |
| 1117 | spin_lock_irqsave(&ha->hardware_lock, flags); |
Bart Van Assche | 8d16366 | 2015-07-09 07:25:46 -0700 | [diff] [blame] | 1118 | #endif |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1119 | |
Andrew Vasquez | d4e3e04 | 2006-05-17 15:09:50 -0700 | [diff] [blame] | 1120 | if (!ha->fw_dump) { |
Saurav Kashyap | 7c3df13 | 2011-07-14 12:00:13 -0700 | [diff] [blame] | 1121 | ql_log(ql_log_warn, vha, 0xd006, |
| 1122 | "No buffer available for dump.\n"); |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1123 | goto qla24xx_fw_dump_failed; |
| 1124 | } |
| 1125 | |
| 1126 | if (ha->fw_dumped) { |
Saurav Kashyap | 7c3df13 | 2011-07-14 12:00:13 -0700 | [diff] [blame] | 1127 | ql_log(ql_log_warn, vha, 0xd007, |
| 1128 | "Firmware has been previously dumped (%p) " |
| 1129 | "-- ignoring request.\n", |
| 1130 | ha->fw_dump); |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1131 | goto qla24xx_fw_dump_failed; |
| 1132 | } |
Andrew Vasquez | a7a167b | 2006-06-23 16:10:29 -0700 | [diff] [blame] | 1133 | fw = &ha->fw_dump->isp.isp24; |
| 1134 | qla2xxx_prep_dump(ha, ha->fw_dump); |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1135 | |
Andrew Vasquez | a7a167b | 2006-06-23 16:10:29 -0700 | [diff] [blame] | 1136 | fw->host_status = htonl(RD_REG_DWORD(®->host_status)); |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1137 | |
Hiral Patel | 2f389fc | 2014-04-11 16:54:20 -0400 | [diff] [blame] | 1138 | /* |
| 1139 | * Pause RISC. No need to track timeout, as resetting the chip |
| 1140 | * is the right approach incase of pause timeout |
| 1141 | */ |
Hiral Patel | 61f098d | 2014-04-11 16:54:21 -0400 | [diff] [blame] | 1142 | qla24xx_pause_risc(reg, ha); |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1143 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1144 | /* Host interface registers. */ |
| 1145 | dmp_reg = ®->flash_addr; |
Joe Carnuccio | da08ef5 | 2016-01-27 12:03:34 -0500 | [diff] [blame] | 1146 | for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++, dmp_reg++) |
| 1147 | fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg)); |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1148 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1149 | /* Disable interrupts. */ |
| 1150 | WRT_REG_DWORD(®->ictrl, 0); |
| 1151 | RD_REG_DWORD(®->ictrl); |
andrew.vasquez@qlogic.com | 210d535 | 2006-01-13 17:05:21 -0800 | [diff] [blame] | 1152 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1153 | /* Shadow registers. */ |
| 1154 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); |
| 1155 | RD_REG_DWORD(®->iobase_addr); |
| 1156 | WRT_REG_DWORD(®->iobase_select, 0xB0000000); |
| 1157 | fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
andrew.vasquez@qlogic.com | 210d535 | 2006-01-13 17:05:21 -0800 | [diff] [blame] | 1158 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1159 | WRT_REG_DWORD(®->iobase_select, 0xB0100000); |
| 1160 | fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
andrew.vasquez@qlogic.com | 210d535 | 2006-01-13 17:05:21 -0800 | [diff] [blame] | 1161 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1162 | WRT_REG_DWORD(®->iobase_select, 0xB0200000); |
| 1163 | fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
andrew.vasquez@qlogic.com | 210d535 | 2006-01-13 17:05:21 -0800 | [diff] [blame] | 1164 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1165 | WRT_REG_DWORD(®->iobase_select, 0xB0300000); |
| 1166 | fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
andrew.vasquez@qlogic.com | 210d535 | 2006-01-13 17:05:21 -0800 | [diff] [blame] | 1167 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1168 | WRT_REG_DWORD(®->iobase_select, 0xB0400000); |
| 1169 | fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
andrew.vasquez@qlogic.com | 210d535 | 2006-01-13 17:05:21 -0800 | [diff] [blame] | 1170 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1171 | WRT_REG_DWORD(®->iobase_select, 0xB0500000); |
| 1172 | fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
andrew.vasquez@qlogic.com | 210d535 | 2006-01-13 17:05:21 -0800 | [diff] [blame] | 1173 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1174 | WRT_REG_DWORD(®->iobase_select, 0xB0600000); |
| 1175 | fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
andrew.vasquez@qlogic.com | 210d535 | 2006-01-13 17:05:21 -0800 | [diff] [blame] | 1176 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1177 | /* Mailbox registers. */ |
| 1178 | mbx_reg = ®->mailbox0; |
Joe Carnuccio | 74939a0 | 2017-05-24 18:06:23 -0700 | [diff] [blame] | 1179 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++, mbx_reg++) |
Joe Carnuccio | da08ef5 | 2016-01-27 12:03:34 -0500 | [diff] [blame] | 1180 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg)); |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1181 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1182 | /* Transfer sequence registers. */ |
| 1183 | iter_reg = fw->xseq_gp_reg; |
| 1184 | iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); |
| 1185 | iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); |
| 1186 | iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); |
| 1187 | iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); |
| 1188 | iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); |
| 1189 | iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); |
| 1190 | iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); |
| 1191 | qla24xx_read_window(reg, 0xBF70, 16, iter_reg); |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1192 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1193 | qla24xx_read_window(reg, 0xBFE0, 16, fw->xseq_0_reg); |
| 1194 | qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1195 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1196 | /* Receive sequence registers. */ |
| 1197 | iter_reg = fw->rseq_gp_reg; |
| 1198 | iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); |
| 1199 | iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); |
| 1200 | iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); |
| 1201 | iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); |
| 1202 | iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); |
| 1203 | iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); |
| 1204 | iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); |
| 1205 | qla24xx_read_window(reg, 0xFF70, 16, iter_reg); |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1206 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1207 | qla24xx_read_window(reg, 0xFFD0, 16, fw->rseq_0_reg); |
| 1208 | qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); |
| 1209 | qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1210 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1211 | /* Command DMA registers. */ |
| 1212 | qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1213 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1214 | /* Queues. */ |
| 1215 | iter_reg = fw->req0_dma_reg; |
| 1216 | iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); |
| 1217 | dmp_reg = ®->iobase_q; |
Joe Carnuccio | da08ef5 | 2016-01-27 12:03:34 -0500 | [diff] [blame] | 1218 | for (cnt = 0; cnt < 7; cnt++, dmp_reg++) |
| 1219 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg)); |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1220 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1221 | iter_reg = fw->resp0_dma_reg; |
| 1222 | iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); |
| 1223 | dmp_reg = ®->iobase_q; |
Joe Carnuccio | da08ef5 | 2016-01-27 12:03:34 -0500 | [diff] [blame] | 1224 | for (cnt = 0; cnt < 7; cnt++, dmp_reg++) |
| 1225 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg)); |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1226 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1227 | iter_reg = fw->req1_dma_reg; |
| 1228 | iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); |
| 1229 | dmp_reg = ®->iobase_q; |
Joe Carnuccio | da08ef5 | 2016-01-27 12:03:34 -0500 | [diff] [blame] | 1230 | for (cnt = 0; cnt < 7; cnt++, dmp_reg++) |
| 1231 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg)); |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1232 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1233 | /* Transmit DMA registers. */ |
| 1234 | iter_reg = fw->xmt0_dma_reg; |
| 1235 | iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); |
| 1236 | qla24xx_read_window(reg, 0x7610, 16, iter_reg); |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1237 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1238 | iter_reg = fw->xmt1_dma_reg; |
| 1239 | iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); |
| 1240 | qla24xx_read_window(reg, 0x7630, 16, iter_reg); |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1241 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1242 | iter_reg = fw->xmt2_dma_reg; |
| 1243 | iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); |
| 1244 | qla24xx_read_window(reg, 0x7650, 16, iter_reg); |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1245 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1246 | iter_reg = fw->xmt3_dma_reg; |
| 1247 | iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); |
| 1248 | qla24xx_read_window(reg, 0x7670, 16, iter_reg); |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1249 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1250 | iter_reg = fw->xmt4_dma_reg; |
| 1251 | iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); |
| 1252 | qla24xx_read_window(reg, 0x7690, 16, iter_reg); |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1253 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1254 | qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1255 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1256 | /* Receive DMA registers. */ |
| 1257 | iter_reg = fw->rcvt0_data_dma_reg; |
| 1258 | iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); |
| 1259 | qla24xx_read_window(reg, 0x7710, 16, iter_reg); |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1260 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1261 | iter_reg = fw->rcvt1_data_dma_reg; |
| 1262 | iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); |
| 1263 | qla24xx_read_window(reg, 0x7730, 16, iter_reg); |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1264 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1265 | /* RISC registers. */ |
| 1266 | iter_reg = fw->risc_gp_reg; |
| 1267 | iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); |
| 1268 | iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); |
| 1269 | iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); |
| 1270 | iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); |
| 1271 | iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); |
| 1272 | iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); |
| 1273 | iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); |
| 1274 | qla24xx_read_window(reg, 0x0F70, 16, iter_reg); |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1275 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1276 | /* Local memory controller registers. */ |
| 1277 | iter_reg = fw->lmc_reg; |
| 1278 | iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); |
| 1279 | iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); |
| 1280 | iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); |
| 1281 | iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); |
| 1282 | iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); |
| 1283 | iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); |
| 1284 | qla24xx_read_window(reg, 0x3060, 16, iter_reg); |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1285 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1286 | /* Fibre Protocol Module registers. */ |
| 1287 | iter_reg = fw->fpm_hdw_reg; |
| 1288 | iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); |
| 1289 | iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); |
| 1290 | iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); |
| 1291 | iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); |
| 1292 | iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); |
| 1293 | iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); |
| 1294 | iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); |
| 1295 | iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); |
| 1296 | iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); |
| 1297 | iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); |
| 1298 | iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); |
| 1299 | qla24xx_read_window(reg, 0x40B0, 16, iter_reg); |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1300 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1301 | /* Frame Buffer registers. */ |
| 1302 | iter_reg = fw->fb_hdw_reg; |
| 1303 | iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); |
| 1304 | iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); |
| 1305 | iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); |
| 1306 | iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); |
| 1307 | iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); |
| 1308 | iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); |
| 1309 | iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); |
| 1310 | iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); |
| 1311 | iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); |
| 1312 | iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); |
| 1313 | qla24xx_read_window(reg, 0x61B0, 16, iter_reg); |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1314 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1315 | rval = qla24xx_soft_reset(ha); |
| 1316 | if (rval != QLA_SUCCESS) |
| 1317 | goto qla24xx_fw_dump_failed_0; |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1318 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1319 | rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), |
Andrew Vasquez | c572270 | 2008-04-24 15:21:22 -0700 | [diff] [blame] | 1320 | &nxt); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1321 | if (rval != QLA_SUCCESS) |
| 1322 | goto qla24xx_fw_dump_failed_0; |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1323 | |
Anirban Chakraborty | 73208df | 2008-12-09 16:45:39 -0800 | [diff] [blame] | 1324 | nxt = qla2xxx_copy_queues(ha, nxt); |
Andrew Vasquez | bb99de6 | 2009-01-05 11:18:08 -0800 | [diff] [blame] | 1325 | |
| 1326 | qla24xx_copy_eft(ha, nxt); |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1327 | |
Nicholas Bellinger | 2d70c10 | 2012-05-15 14:34:28 -0400 | [diff] [blame] | 1328 | nxt_chain = (void *)ha->fw_dump + ha->chain_offset; |
| 1329 | nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain); |
| 1330 | if (last_chain) { |
Bart Van Assche | ad95036 | 2015-07-09 07:24:08 -0700 | [diff] [blame] | 1331 | ha->fw_dump->version |= htonl(DUMP_CHAIN_VARIANT); |
| 1332 | *last_chain |= htonl(DUMP_CHAIN_LAST); |
Nicholas Bellinger | 2d70c10 | 2012-05-15 14:34:28 -0400 | [diff] [blame] | 1333 | } |
| 1334 | |
| 1335 | /* Adjust valid length. */ |
| 1336 | ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); |
| 1337 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1338 | qla24xx_fw_dump_failed_0: |
Andrew Vasquez | 3420d36 | 2009-10-13 15:16:45 -0700 | [diff] [blame] | 1339 | qla2xxx_dump_post_process(base_vha, rval); |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1340 | |
| 1341 | qla24xx_fw_dump_failed: |
Bart Van Assche | 8d16366 | 2015-07-09 07:25:46 -0700 | [diff] [blame] | 1342 | #ifndef __CHECKER__ |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1343 | if (!hardware_locked) |
| 1344 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
Bart Van Assche | 8d16366 | 2015-07-09 07:25:46 -0700 | [diff] [blame] | 1345 | #else |
| 1346 | ; |
| 1347 | #endif |
Andrew Vasquez | 6d9b61e | 2005-07-06 10:30:36 -0700 | [diff] [blame] | 1348 | } |
| 1349 | |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1350 | void |
Anirban Chakraborty | 7b867cf | 2008-11-06 10:40:19 -0800 | [diff] [blame] | 1351 | qla25xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1352 | { |
| 1353 | int rval; |
| 1354 | uint32_t cnt; |
Anirban Chakraborty | 7b867cf | 2008-11-06 10:40:19 -0800 | [diff] [blame] | 1355 | struct qla_hw_data *ha = vha->hw; |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1356 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
| 1357 | uint32_t __iomem *dmp_reg; |
| 1358 | uint32_t *iter_reg; |
| 1359 | uint16_t __iomem *mbx_reg; |
| 1360 | unsigned long flags; |
| 1361 | struct qla25xx_fw_dump *fw; |
Andrew Vasquez | d63ab53 | 2009-01-05 11:18:09 -0800 | [diff] [blame] | 1362 | void *nxt, *nxt_chain; |
Andrew Vasquez | bb99de6 | 2009-01-05 11:18:08 -0800 | [diff] [blame] | 1363 | uint32_t *last_chain = NULL; |
Anirban Chakraborty | 73208df | 2008-12-09 16:45:39 -0800 | [diff] [blame] | 1364 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1365 | |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1366 | flags = 0; |
Hiral Patel | 61f098d | 2014-04-11 16:54:21 -0400 | [diff] [blame] | 1367 | ha->fw_dump_cap_flags = 0; |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1368 | |
Bart Van Assche | 8d16366 | 2015-07-09 07:25:46 -0700 | [diff] [blame] | 1369 | #ifndef __CHECKER__ |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1370 | if (!hardware_locked) |
| 1371 | spin_lock_irqsave(&ha->hardware_lock, flags); |
Bart Van Assche | 8d16366 | 2015-07-09 07:25:46 -0700 | [diff] [blame] | 1372 | #endif |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1373 | |
| 1374 | if (!ha->fw_dump) { |
Saurav Kashyap | 7c3df13 | 2011-07-14 12:00:13 -0700 | [diff] [blame] | 1375 | ql_log(ql_log_warn, vha, 0xd008, |
| 1376 | "No buffer available for dump.\n"); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1377 | goto qla25xx_fw_dump_failed; |
| 1378 | } |
| 1379 | |
| 1380 | if (ha->fw_dumped) { |
Saurav Kashyap | 7c3df13 | 2011-07-14 12:00:13 -0700 | [diff] [blame] | 1381 | ql_log(ql_log_warn, vha, 0xd009, |
| 1382 | "Firmware has been previously dumped (%p) " |
| 1383 | "-- ignoring request.\n", |
| 1384 | ha->fw_dump); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1385 | goto qla25xx_fw_dump_failed; |
| 1386 | } |
| 1387 | fw = &ha->fw_dump->isp.isp25; |
| 1388 | qla2xxx_prep_dump(ha, ha->fw_dump); |
Bart Van Assche | ad95036 | 2015-07-09 07:24:08 -0700 | [diff] [blame] | 1389 | ha->fw_dump->version = htonl(2); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1390 | |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1391 | fw->host_status = htonl(RD_REG_DWORD(®->host_status)); |
| 1392 | |
Hiral Patel | 2f389fc | 2014-04-11 16:54:20 -0400 | [diff] [blame] | 1393 | /* |
| 1394 | * Pause RISC. No need to track timeout, as resetting the chip |
| 1395 | * is the right approach incase of pause timeout |
| 1396 | */ |
Hiral Patel | 61f098d | 2014-04-11 16:54:21 -0400 | [diff] [blame] | 1397 | qla24xx_pause_risc(reg, ha); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1398 | |
Andrew Vasquez | b583692 | 2007-09-20 14:07:39 -0700 | [diff] [blame] | 1399 | /* Host/Risc registers. */ |
| 1400 | iter_reg = fw->host_risc_reg; |
| 1401 | iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); |
| 1402 | qla24xx_read_window(reg, 0x7010, 16, iter_reg); |
| 1403 | |
| 1404 | /* PCIe registers. */ |
| 1405 | WRT_REG_DWORD(®->iobase_addr, 0x7C00); |
| 1406 | RD_REG_DWORD(®->iobase_addr); |
| 1407 | WRT_REG_DWORD(®->iobase_window, 0x01); |
| 1408 | dmp_reg = ®->iobase_c4; |
Joe Carnuccio | da08ef5 | 2016-01-27 12:03:34 -0500 | [diff] [blame] | 1409 | fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg)); |
| 1410 | dmp_reg++; |
| 1411 | fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg)); |
| 1412 | dmp_reg++; |
Andrew Vasquez | b583692 | 2007-09-20 14:07:39 -0700 | [diff] [blame] | 1413 | fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); |
| 1414 | fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); |
Anirban Chakraborty | 73208df | 2008-12-09 16:45:39 -0800 | [diff] [blame] | 1415 | |
Andrew Vasquez | b583692 | 2007-09-20 14:07:39 -0700 | [diff] [blame] | 1416 | WRT_REG_DWORD(®->iobase_window, 0x00); |
| 1417 | RD_REG_DWORD(®->iobase_window); |
| 1418 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1419 | /* Host interface registers. */ |
| 1420 | dmp_reg = ®->flash_addr; |
Joe Carnuccio | da08ef5 | 2016-01-27 12:03:34 -0500 | [diff] [blame] | 1421 | for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++, dmp_reg++) |
| 1422 | fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg)); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1423 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1424 | /* Disable interrupts. */ |
| 1425 | WRT_REG_DWORD(®->ictrl, 0); |
| 1426 | RD_REG_DWORD(®->ictrl); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1427 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1428 | /* Shadow registers. */ |
| 1429 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); |
| 1430 | RD_REG_DWORD(®->iobase_addr); |
| 1431 | WRT_REG_DWORD(®->iobase_select, 0xB0000000); |
| 1432 | fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1433 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1434 | WRT_REG_DWORD(®->iobase_select, 0xB0100000); |
| 1435 | fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1436 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1437 | WRT_REG_DWORD(®->iobase_select, 0xB0200000); |
| 1438 | fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1439 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1440 | WRT_REG_DWORD(®->iobase_select, 0xB0300000); |
| 1441 | fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1442 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1443 | WRT_REG_DWORD(®->iobase_select, 0xB0400000); |
| 1444 | fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1445 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1446 | WRT_REG_DWORD(®->iobase_select, 0xB0500000); |
| 1447 | fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1448 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1449 | WRT_REG_DWORD(®->iobase_select, 0xB0600000); |
| 1450 | fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1451 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1452 | WRT_REG_DWORD(®->iobase_select, 0xB0700000); |
| 1453 | fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1454 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1455 | WRT_REG_DWORD(®->iobase_select, 0xB0800000); |
| 1456 | fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1457 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1458 | WRT_REG_DWORD(®->iobase_select, 0xB0900000); |
| 1459 | fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1460 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1461 | WRT_REG_DWORD(®->iobase_select, 0xB0A00000); |
| 1462 | fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1463 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1464 | /* RISC I/O register. */ |
| 1465 | WRT_REG_DWORD(®->iobase_addr, 0x0010); |
| 1466 | fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1467 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1468 | /* Mailbox registers. */ |
| 1469 | mbx_reg = ®->mailbox0; |
Joe Carnuccio | da08ef5 | 2016-01-27 12:03:34 -0500 | [diff] [blame] | 1470 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++, mbx_reg++) |
| 1471 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg)); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1472 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1473 | /* Transfer sequence registers. */ |
| 1474 | iter_reg = fw->xseq_gp_reg; |
| 1475 | iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); |
| 1476 | iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); |
| 1477 | iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); |
| 1478 | iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); |
| 1479 | iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); |
| 1480 | iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); |
| 1481 | iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); |
| 1482 | qla24xx_read_window(reg, 0xBF70, 16, iter_reg); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1483 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1484 | iter_reg = fw->xseq_0_reg; |
| 1485 | iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); |
| 1486 | iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); |
| 1487 | qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1488 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1489 | qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1490 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1491 | /* Receive sequence registers. */ |
| 1492 | iter_reg = fw->rseq_gp_reg; |
| 1493 | iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); |
| 1494 | iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); |
| 1495 | iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); |
| 1496 | iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); |
| 1497 | iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); |
| 1498 | iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); |
| 1499 | iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); |
| 1500 | qla24xx_read_window(reg, 0xFF70, 16, iter_reg); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1501 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1502 | iter_reg = fw->rseq_0_reg; |
| 1503 | iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); |
| 1504 | qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1505 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1506 | qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); |
| 1507 | qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1508 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1509 | /* Auxiliary sequence registers. */ |
| 1510 | iter_reg = fw->aseq_gp_reg; |
| 1511 | iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); |
| 1512 | iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); |
| 1513 | iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); |
| 1514 | iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); |
| 1515 | iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); |
| 1516 | iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); |
| 1517 | iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); |
| 1518 | qla24xx_read_window(reg, 0xB070, 16, iter_reg); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1519 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1520 | iter_reg = fw->aseq_0_reg; |
| 1521 | iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); |
| 1522 | qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1523 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1524 | qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); |
| 1525 | qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1526 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1527 | /* Command DMA registers. */ |
| 1528 | qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1529 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1530 | /* Queues. */ |
| 1531 | iter_reg = fw->req0_dma_reg; |
| 1532 | iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); |
| 1533 | dmp_reg = ®->iobase_q; |
Joe Carnuccio | da08ef5 | 2016-01-27 12:03:34 -0500 | [diff] [blame] | 1534 | for (cnt = 0; cnt < 7; cnt++, dmp_reg++) |
| 1535 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg)); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1536 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1537 | iter_reg = fw->resp0_dma_reg; |
| 1538 | iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); |
| 1539 | dmp_reg = ®->iobase_q; |
Joe Carnuccio | da08ef5 | 2016-01-27 12:03:34 -0500 | [diff] [blame] | 1540 | for (cnt = 0; cnt < 7; cnt++, dmp_reg++) |
| 1541 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg)); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1542 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1543 | iter_reg = fw->req1_dma_reg; |
| 1544 | iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); |
| 1545 | dmp_reg = ®->iobase_q; |
Joe Carnuccio | da08ef5 | 2016-01-27 12:03:34 -0500 | [diff] [blame] | 1546 | for (cnt = 0; cnt < 7; cnt++, dmp_reg++) |
| 1547 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg)); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1548 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1549 | /* Transmit DMA registers. */ |
| 1550 | iter_reg = fw->xmt0_dma_reg; |
| 1551 | iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); |
| 1552 | qla24xx_read_window(reg, 0x7610, 16, iter_reg); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1553 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1554 | iter_reg = fw->xmt1_dma_reg; |
| 1555 | iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); |
| 1556 | qla24xx_read_window(reg, 0x7630, 16, iter_reg); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1557 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1558 | iter_reg = fw->xmt2_dma_reg; |
| 1559 | iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); |
| 1560 | qla24xx_read_window(reg, 0x7650, 16, iter_reg); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1561 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1562 | iter_reg = fw->xmt3_dma_reg; |
| 1563 | iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); |
| 1564 | qla24xx_read_window(reg, 0x7670, 16, iter_reg); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1565 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1566 | iter_reg = fw->xmt4_dma_reg; |
| 1567 | iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); |
| 1568 | qla24xx_read_window(reg, 0x7690, 16, iter_reg); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1569 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1570 | qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1571 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1572 | /* Receive DMA registers. */ |
| 1573 | iter_reg = fw->rcvt0_data_dma_reg; |
| 1574 | iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); |
| 1575 | qla24xx_read_window(reg, 0x7710, 16, iter_reg); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1576 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1577 | iter_reg = fw->rcvt1_data_dma_reg; |
| 1578 | iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); |
| 1579 | qla24xx_read_window(reg, 0x7730, 16, iter_reg); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1580 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1581 | /* RISC registers. */ |
| 1582 | iter_reg = fw->risc_gp_reg; |
| 1583 | iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); |
| 1584 | iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); |
| 1585 | iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); |
| 1586 | iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); |
| 1587 | iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); |
| 1588 | iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); |
| 1589 | iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); |
| 1590 | qla24xx_read_window(reg, 0x0F70, 16, iter_reg); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1591 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1592 | /* Local memory controller registers. */ |
| 1593 | iter_reg = fw->lmc_reg; |
| 1594 | iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); |
| 1595 | iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); |
| 1596 | iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); |
| 1597 | iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); |
| 1598 | iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); |
| 1599 | iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); |
| 1600 | iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); |
| 1601 | qla24xx_read_window(reg, 0x3070, 16, iter_reg); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1602 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1603 | /* Fibre Protocol Module registers. */ |
| 1604 | iter_reg = fw->fpm_hdw_reg; |
| 1605 | iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); |
| 1606 | iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); |
| 1607 | iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); |
| 1608 | iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); |
| 1609 | iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); |
| 1610 | iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); |
| 1611 | iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); |
| 1612 | iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); |
| 1613 | iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); |
| 1614 | iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); |
| 1615 | iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); |
| 1616 | qla24xx_read_window(reg, 0x40B0, 16, iter_reg); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1617 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1618 | /* Frame Buffer registers. */ |
| 1619 | iter_reg = fw->fb_hdw_reg; |
| 1620 | iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); |
| 1621 | iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); |
| 1622 | iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); |
| 1623 | iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); |
| 1624 | iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); |
| 1625 | iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); |
| 1626 | iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); |
| 1627 | iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); |
| 1628 | iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); |
| 1629 | iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); |
| 1630 | iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); |
| 1631 | qla24xx_read_window(reg, 0x6F00, 16, iter_reg); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1632 | |
Andrew Vasquez | d63ab53 | 2009-01-05 11:18:09 -0800 | [diff] [blame] | 1633 | /* Multi queue registers */ |
| 1634 | nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, |
| 1635 | &last_chain); |
| 1636 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1637 | rval = qla24xx_soft_reset(ha); |
| 1638 | if (rval != QLA_SUCCESS) |
| 1639 | goto qla25xx_fw_dump_failed_0; |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1640 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1641 | rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), |
Andrew Vasquez | c572270 | 2008-04-24 15:21:22 -0700 | [diff] [blame] | 1642 | &nxt); |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1643 | if (rval != QLA_SUCCESS) |
| 1644 | goto qla25xx_fw_dump_failed_0; |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1645 | |
Anirban Chakraborty | 73208df | 2008-12-09 16:45:39 -0800 | [diff] [blame] | 1646 | nxt = qla2xxx_copy_queues(ha, nxt); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1647 | |
Bart Van Assche | 7f544d0 | 2013-06-25 11:27:27 -0400 | [diff] [blame] | 1648 | qla24xx_copy_eft(ha, nxt); |
Andrew Vasquez | df613b9 | 2008-01-17 09:02:17 -0800 | [diff] [blame] | 1649 | |
Andrew Vasquez | d63ab53 | 2009-01-05 11:18:09 -0800 | [diff] [blame] | 1650 | /* Chain entries -- started with MQ. */ |
Giridhar Malavali | 050c9bb | 2012-02-09 11:15:33 -0800 | [diff] [blame] | 1651 | nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain); |
| 1652 | nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain); |
Nicholas Bellinger | 2d70c10 | 2012-05-15 14:34:28 -0400 | [diff] [blame] | 1653 | nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain); |
Quinn Tran | b945e77 | 2017-06-13 20:47:29 -0700 | [diff] [blame] | 1654 | nxt_chain = qla25xx_copy_exlogin(ha, nxt_chain, &last_chain); |
Andrew Vasquez | bb99de6 | 2009-01-05 11:18:08 -0800 | [diff] [blame] | 1655 | if (last_chain) { |
Bart Van Assche | ad95036 | 2015-07-09 07:24:08 -0700 | [diff] [blame] | 1656 | ha->fw_dump->version |= htonl(DUMP_CHAIN_VARIANT); |
| 1657 | *last_chain |= htonl(DUMP_CHAIN_LAST); |
Andrew Vasquez | bb99de6 | 2009-01-05 11:18:08 -0800 | [diff] [blame] | 1658 | } |
Andrew Vasquez | df613b9 | 2008-01-17 09:02:17 -0800 | [diff] [blame] | 1659 | |
Giridhar Malavali | 050c9bb | 2012-02-09 11:15:33 -0800 | [diff] [blame] | 1660 | /* Adjust valid length. */ |
| 1661 | ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); |
| 1662 | |
Andrew Vasquez | c81d04c | 2007-07-26 11:41:13 -0700 | [diff] [blame] | 1663 | qla25xx_fw_dump_failed_0: |
Andrew Vasquez | 3420d36 | 2009-10-13 15:16:45 -0700 | [diff] [blame] | 1664 | qla2xxx_dump_post_process(base_vha, rval); |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1665 | |
| 1666 | qla25xx_fw_dump_failed: |
Bart Van Assche | 8d16366 | 2015-07-09 07:25:46 -0700 | [diff] [blame] | 1667 | #ifndef __CHECKER__ |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1668 | if (!hardware_locked) |
| 1669 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
Bart Van Assche | 8d16366 | 2015-07-09 07:25:46 -0700 | [diff] [blame] | 1670 | #else |
| 1671 | ; |
| 1672 | #endif |
Andrew Vasquez | c3a2f0d | 2007-07-19 20:37:34 -0700 | [diff] [blame] | 1673 | } |
Andrew Vasquez | 3a03eb7 | 2009-01-05 11:18:11 -0800 | [diff] [blame] | 1674 | |
| 1675 | void |
| 1676 | qla81xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
| 1677 | { |
| 1678 | int rval; |
| 1679 | uint32_t cnt; |
Andrew Vasquez | 3a03eb7 | 2009-01-05 11:18:11 -0800 | [diff] [blame] | 1680 | struct qla_hw_data *ha = vha->hw; |
| 1681 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
| 1682 | uint32_t __iomem *dmp_reg; |
| 1683 | uint32_t *iter_reg; |
| 1684 | uint16_t __iomem *mbx_reg; |
| 1685 | unsigned long flags; |
| 1686 | struct qla81xx_fw_dump *fw; |
Andrew Vasquez | 3a03eb7 | 2009-01-05 11:18:11 -0800 | [diff] [blame] | 1687 | void *nxt, *nxt_chain; |
| 1688 | uint32_t *last_chain = NULL; |
| 1689 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
| 1690 | |
Andrew Vasquez | 3a03eb7 | 2009-01-05 11:18:11 -0800 | [diff] [blame] | 1691 | flags = 0; |
Hiral Patel | 61f098d | 2014-04-11 16:54:21 -0400 | [diff] [blame] | 1692 | ha->fw_dump_cap_flags = 0; |
Andrew Vasquez | 3a03eb7 | 2009-01-05 11:18:11 -0800 | [diff] [blame] | 1693 | |
Bart Van Assche | 8d16366 | 2015-07-09 07:25:46 -0700 | [diff] [blame] | 1694 | #ifndef __CHECKER__ |
Andrew Vasquez | 3a03eb7 | 2009-01-05 11:18:11 -0800 | [diff] [blame] | 1695 | if (!hardware_locked) |
| 1696 | spin_lock_irqsave(&ha->hardware_lock, flags); |
Bart Van Assche | 8d16366 | 2015-07-09 07:25:46 -0700 | [diff] [blame] | 1697 | #endif |
Andrew Vasquez | 3a03eb7 | 2009-01-05 11:18:11 -0800 | [diff] [blame] | 1698 | |
| 1699 | if (!ha->fw_dump) { |
Saurav Kashyap | 7c3df13 | 2011-07-14 12:00:13 -0700 | [diff] [blame] | 1700 | ql_log(ql_log_warn, vha, 0xd00a, |
| 1701 | "No buffer available for dump.\n"); |
Andrew Vasquez | 3a03eb7 | 2009-01-05 11:18:11 -0800 | [diff] [blame] | 1702 | goto qla81xx_fw_dump_failed; |
| 1703 | } |
| 1704 | |
| 1705 | if (ha->fw_dumped) { |
Saurav Kashyap | 7c3df13 | 2011-07-14 12:00:13 -0700 | [diff] [blame] | 1706 | ql_log(ql_log_warn, vha, 0xd00b, |
| 1707 | "Firmware has been previously dumped (%p) " |
| 1708 | "-- ignoring request.\n", |
| 1709 | ha->fw_dump); |
Andrew Vasquez | 3a03eb7 | 2009-01-05 11:18:11 -0800 | [diff] [blame] | 1710 | goto qla81xx_fw_dump_failed; |
| 1711 | } |
| 1712 | fw = &ha->fw_dump->isp.isp81; |
| 1713 | qla2xxx_prep_dump(ha, ha->fw_dump); |
| 1714 | |
| 1715 | fw->host_status = htonl(RD_REG_DWORD(®->host_status)); |
| 1716 | |
Hiral Patel | 2f389fc | 2014-04-11 16:54:20 -0400 | [diff] [blame] | 1717 | /* |
| 1718 | * Pause RISC. No need to track timeout, as resetting the chip |
| 1719 | * is the right approach incase of pause timeout |
| 1720 | */ |
Hiral Patel | 61f098d | 2014-04-11 16:54:21 -0400 | [diff] [blame] | 1721 | qla24xx_pause_risc(reg, ha); |
Andrew Vasquez | 3a03eb7 | 2009-01-05 11:18:11 -0800 | [diff] [blame] | 1722 | |
| 1723 | /* Host/Risc registers. */ |
| 1724 | iter_reg = fw->host_risc_reg; |
| 1725 | iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); |
| 1726 | qla24xx_read_window(reg, 0x7010, 16, iter_reg); |
| 1727 | |
| 1728 | /* PCIe registers. */ |
| 1729 | WRT_REG_DWORD(®->iobase_addr, 0x7C00); |
| 1730 | RD_REG_DWORD(®->iobase_addr); |
| 1731 | WRT_REG_DWORD(®->iobase_window, 0x01); |
| 1732 | dmp_reg = ®->iobase_c4; |
Joe Carnuccio | da08ef5 | 2016-01-27 12:03:34 -0500 | [diff] [blame] | 1733 | fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg)); |
| 1734 | dmp_reg++; |
| 1735 | fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg)); |
| 1736 | dmp_reg++; |
Andrew Vasquez | 3a03eb7 | 2009-01-05 11:18:11 -0800 | [diff] [blame] | 1737 | fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); |
| 1738 | fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); |
| 1739 | |
| 1740 | WRT_REG_DWORD(®->iobase_window, 0x00); |
| 1741 | RD_REG_DWORD(®->iobase_window); |
| 1742 | |
| 1743 | /* Host interface registers. */ |
| 1744 | dmp_reg = ®->flash_addr; |
Joe Carnuccio | da08ef5 | 2016-01-27 12:03:34 -0500 | [diff] [blame] | 1745 | for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++, dmp_reg++) |
| 1746 | fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg)); |
Andrew Vasquez | 3a03eb7 | 2009-01-05 11:18:11 -0800 | [diff] [blame] | 1747 | |
| 1748 | /* Disable interrupts. */ |
| 1749 | WRT_REG_DWORD(®->ictrl, 0); |
| 1750 | RD_REG_DWORD(®->ictrl); |
| 1751 | |
| 1752 | /* Shadow registers. */ |
| 1753 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); |
| 1754 | RD_REG_DWORD(®->iobase_addr); |
| 1755 | WRT_REG_DWORD(®->iobase_select, 0xB0000000); |
| 1756 | fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
| 1757 | |
| 1758 | WRT_REG_DWORD(®->iobase_select, 0xB0100000); |
| 1759 | fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
| 1760 | |
| 1761 | WRT_REG_DWORD(®->iobase_select, 0xB0200000); |
| 1762 | fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
| 1763 | |
| 1764 | WRT_REG_DWORD(®->iobase_select, 0xB0300000); |
| 1765 | fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
| 1766 | |
| 1767 | WRT_REG_DWORD(®->iobase_select, 0xB0400000); |
| 1768 | fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
| 1769 | |
| 1770 | WRT_REG_DWORD(®->iobase_select, 0xB0500000); |
| 1771 | fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
| 1772 | |
| 1773 | WRT_REG_DWORD(®->iobase_select, 0xB0600000); |
| 1774 | fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
| 1775 | |
| 1776 | WRT_REG_DWORD(®->iobase_select, 0xB0700000); |
| 1777 | fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
| 1778 | |
| 1779 | WRT_REG_DWORD(®->iobase_select, 0xB0800000); |
| 1780 | fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
| 1781 | |
| 1782 | WRT_REG_DWORD(®->iobase_select, 0xB0900000); |
| 1783 | fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
| 1784 | |
| 1785 | WRT_REG_DWORD(®->iobase_select, 0xB0A00000); |
| 1786 | fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
| 1787 | |
| 1788 | /* RISC I/O register. */ |
| 1789 | WRT_REG_DWORD(®->iobase_addr, 0x0010); |
| 1790 | fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); |
| 1791 | |
| 1792 | /* Mailbox registers. */ |
| 1793 | mbx_reg = ®->mailbox0; |
Joe Carnuccio | da08ef5 | 2016-01-27 12:03:34 -0500 | [diff] [blame] | 1794 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++, mbx_reg++) |
| 1795 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg)); |
Andrew Vasquez | 3a03eb7 | 2009-01-05 11:18:11 -0800 | [diff] [blame] | 1796 | |
| 1797 | /* Transfer sequence registers. */ |
| 1798 | iter_reg = fw->xseq_gp_reg; |
| 1799 | iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); |
| 1800 | iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); |
| 1801 | iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); |
| 1802 | iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); |
| 1803 | iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); |
| 1804 | iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); |
| 1805 | iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); |
| 1806 | qla24xx_read_window(reg, 0xBF70, 16, iter_reg); |
| 1807 | |
| 1808 | iter_reg = fw->xseq_0_reg; |
| 1809 | iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); |
| 1810 | iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); |
| 1811 | qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); |
| 1812 | |
| 1813 | qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); |
| 1814 | |
| 1815 | /* Receive sequence registers. */ |
| 1816 | iter_reg = fw->rseq_gp_reg; |
| 1817 | iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); |
| 1818 | iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); |
| 1819 | iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); |
| 1820 | iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); |
| 1821 | iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); |
| 1822 | iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); |
| 1823 | iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); |
| 1824 | qla24xx_read_window(reg, 0xFF70, 16, iter_reg); |
| 1825 | |
| 1826 | iter_reg = fw->rseq_0_reg; |
| 1827 | iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); |
| 1828 | qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); |
| 1829 | |
| 1830 | qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); |
| 1831 | qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); |
| 1832 | |
| 1833 | /* Auxiliary sequence registers. */ |
| 1834 | iter_reg = fw->aseq_gp_reg; |
| 1835 | iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); |
| 1836 | iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); |
| 1837 | iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); |
| 1838 | iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); |
| 1839 | iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); |
| 1840 | iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); |
| 1841 | iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); |
| 1842 | qla24xx_read_window(reg, 0xB070, 16, iter_reg); |
| 1843 | |
| 1844 | iter_reg = fw->aseq_0_reg; |
| 1845 | iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); |
| 1846 | qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); |
| 1847 | |
| 1848 | qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); |
| 1849 | qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); |
| 1850 | |
| 1851 | /* Command DMA registers. */ |
| 1852 | qla24xx_read_window(reg, 0x7100, 16, fw->cmd_dma_reg); |
| 1853 | |
| 1854 | /* Queues. */ |
| 1855 | iter_reg = fw->req0_dma_reg; |
| 1856 | iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); |
| 1857 | dmp_reg = ®->iobase_q; |
Joe Carnuccio | da08ef5 | 2016-01-27 12:03:34 -0500 | [diff] [blame] | 1858 | for (cnt = 0; cnt < 7; cnt++, dmp_reg++) |
| 1859 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg)); |
Andrew Vasquez | 3a03eb7 | 2009-01-05 11:18:11 -0800 | [diff] [blame] | 1860 | |
| 1861 | iter_reg = fw->resp0_dma_reg; |
| 1862 | iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); |
| 1863 | dmp_reg = ®->iobase_q; |
Joe Carnuccio | da08ef5 | 2016-01-27 12:03:34 -0500 | [diff] [blame] | 1864 | for (cnt = 0; cnt < 7; cnt++, dmp_reg++) |
| 1865 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg)); |
Andrew Vasquez | 3a03eb7 | 2009-01-05 11:18:11 -0800 | [diff] [blame] | 1866 | |
| 1867 | iter_reg = fw->req1_dma_reg; |
| 1868 | iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); |
| 1869 | dmp_reg = ®->iobase_q; |
Joe Carnuccio | da08ef5 | 2016-01-27 12:03:34 -0500 | [diff] [blame] | 1870 | for (cnt = 0; cnt < 7; cnt++, dmp_reg++) |
| 1871 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg)); |
Andrew Vasquez | 3a03eb7 | 2009-01-05 11:18:11 -0800 | [diff] [blame] | 1872 | |
| 1873 | /* Transmit DMA registers. */ |
| 1874 | iter_reg = fw->xmt0_dma_reg; |
| 1875 | iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); |
| 1876 | qla24xx_read_window(reg, 0x7610, 16, iter_reg); |
| 1877 | |
| 1878 | iter_reg = fw->xmt1_dma_reg; |
| 1879 | iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); |
| 1880 | qla24xx_read_window(reg, 0x7630, 16, iter_reg); |
| 1881 | |
| 1882 | iter_reg = fw->xmt2_dma_reg; |
| 1883 | iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); |
| 1884 | qla24xx_read_window(reg, 0x7650, 16, iter_reg); |
| 1885 | |
| 1886 | iter_reg = fw->xmt3_dma_reg; |
| 1887 | iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); |
| 1888 | qla24xx_read_window(reg, 0x7670, 16, iter_reg); |
| 1889 | |
| 1890 | iter_reg = fw->xmt4_dma_reg; |
| 1891 | iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); |
| 1892 | qla24xx_read_window(reg, 0x7690, 16, iter_reg); |
| 1893 | |
| 1894 | qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); |
| 1895 | |
| 1896 | /* Receive DMA registers. */ |
| 1897 | iter_reg = fw->rcvt0_data_dma_reg; |
| 1898 | iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); |
| 1899 | qla24xx_read_window(reg, 0x7710, 16, iter_reg); |
| 1900 | |
| 1901 | iter_reg = fw->rcvt1_data_dma_reg; |
| 1902 | iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); |
| 1903 | qla24xx_read_window(reg, 0x7730, 16, iter_reg); |
| 1904 | |
| 1905 | /* RISC registers. */ |
| 1906 | iter_reg = fw->risc_gp_reg; |
| 1907 | iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); |
| 1908 | iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); |
| 1909 | iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); |
| 1910 | iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); |
| 1911 | iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); |
| 1912 | iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); |
| 1913 | iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); |
| 1914 | qla24xx_read_window(reg, 0x0F70, 16, iter_reg); |
| 1915 | |
| 1916 | /* Local memory controller registers. */ |
| 1917 | iter_reg = fw->lmc_reg; |
| 1918 | iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); |
| 1919 | iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); |
| 1920 | iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); |
| 1921 | iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); |
| 1922 | iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); |
| 1923 | iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); |
| 1924 | iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); |
| 1925 | qla24xx_read_window(reg, 0x3070, 16, iter_reg); |
| 1926 | |
| 1927 | /* Fibre Protocol Module registers. */ |
| 1928 | iter_reg = fw->fpm_hdw_reg; |
| 1929 | iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); |
| 1930 | iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); |
| 1931 | iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); |
| 1932 | iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); |
| 1933 | iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); |
| 1934 | iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); |
| 1935 | iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); |
| 1936 | iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); |
| 1937 | iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); |
| 1938 | iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); |
| 1939 | iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); |
| 1940 | iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg); |
| 1941 | iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg); |
| 1942 | qla24xx_read_window(reg, 0x40D0, 16, iter_reg); |
| 1943 | |
| 1944 | /* Frame Buffer registers. */ |
| 1945 | iter_reg = fw->fb_hdw_reg; |
| 1946 | iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); |
| 1947 | iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); |
| 1948 | iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); |
| 1949 | iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); |
| 1950 | iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); |
| 1951 | iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); |
| 1952 | iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); |
| 1953 | iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); |
| 1954 | iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); |
| 1955 | iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); |
| 1956 | iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); |
| 1957 | iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg); |
| 1958 | qla24xx_read_window(reg, 0x6F00, 16, iter_reg); |
| 1959 | |
| 1960 | /* Multi queue registers */ |
| 1961 | nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, |
| 1962 | &last_chain); |
| 1963 | |
| 1964 | rval = qla24xx_soft_reset(ha); |
| 1965 | if (rval != QLA_SUCCESS) |
| 1966 | goto qla81xx_fw_dump_failed_0; |
| 1967 | |
| 1968 | rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), |
| 1969 | &nxt); |
| 1970 | if (rval != QLA_SUCCESS) |
| 1971 | goto qla81xx_fw_dump_failed_0; |
| 1972 | |
| 1973 | nxt = qla2xxx_copy_queues(ha, nxt); |
| 1974 | |
Bart Van Assche | 7f544d0 | 2013-06-25 11:27:27 -0400 | [diff] [blame] | 1975 | qla24xx_copy_eft(ha, nxt); |
Andrew Vasquez | 3a03eb7 | 2009-01-05 11:18:11 -0800 | [diff] [blame] | 1976 | |
| 1977 | /* Chain entries -- started with MQ. */ |
Giridhar Malavali | 050c9bb | 2012-02-09 11:15:33 -0800 | [diff] [blame] | 1978 | nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain); |
| 1979 | nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain); |
Nicholas Bellinger | 2d70c10 | 2012-05-15 14:34:28 -0400 | [diff] [blame] | 1980 | nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain); |
Quinn Tran | b945e77 | 2017-06-13 20:47:29 -0700 | [diff] [blame] | 1981 | nxt_chain = qla25xx_copy_exlogin(ha, nxt_chain, &last_chain); |
| 1982 | nxt_chain = qla81xx_copy_exchoffld(ha, nxt_chain, &last_chain); |
Andrew Vasquez | 3a03eb7 | 2009-01-05 11:18:11 -0800 | [diff] [blame] | 1983 | if (last_chain) { |
Bart Van Assche | ad95036 | 2015-07-09 07:24:08 -0700 | [diff] [blame] | 1984 | ha->fw_dump->version |= htonl(DUMP_CHAIN_VARIANT); |
| 1985 | *last_chain |= htonl(DUMP_CHAIN_LAST); |
Andrew Vasquez | 3a03eb7 | 2009-01-05 11:18:11 -0800 | [diff] [blame] | 1986 | } |
| 1987 | |
Giridhar Malavali | 050c9bb | 2012-02-09 11:15:33 -0800 | [diff] [blame] | 1988 | /* Adjust valid length. */ |
| 1989 | ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); |
| 1990 | |
Andrew Vasquez | 3a03eb7 | 2009-01-05 11:18:11 -0800 | [diff] [blame] | 1991 | qla81xx_fw_dump_failed_0: |
Andrew Vasquez | 3420d36 | 2009-10-13 15:16:45 -0700 | [diff] [blame] | 1992 | qla2xxx_dump_post_process(base_vha, rval); |
Andrew Vasquez | 3a03eb7 | 2009-01-05 11:18:11 -0800 | [diff] [blame] | 1993 | |
| 1994 | qla81xx_fw_dump_failed: |
Bart Van Assche | 8d16366 | 2015-07-09 07:25:46 -0700 | [diff] [blame] | 1995 | #ifndef __CHECKER__ |
Andrew Vasquez | 3a03eb7 | 2009-01-05 11:18:11 -0800 | [diff] [blame] | 1996 | if (!hardware_locked) |
| 1997 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
Bart Van Assche | 8d16366 | 2015-07-09 07:25:46 -0700 | [diff] [blame] | 1998 | #else |
| 1999 | ; |
| 2000 | #endif |
Andrew Vasquez | 3a03eb7 | 2009-01-05 11:18:11 -0800 | [diff] [blame] | 2001 | } |
| 2002 | |
Giridhar Malavali | 6246b8a | 2012-02-09 11:15:34 -0800 | [diff] [blame] | 2003 | void |
| 2004 | qla83xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked) |
| 2005 | { |
| 2006 | int rval; |
Bart Van Assche | 52c8282 | 2015-07-09 07:23:26 -0700 | [diff] [blame] | 2007 | uint32_t cnt; |
Giridhar Malavali | 6246b8a | 2012-02-09 11:15:34 -0800 | [diff] [blame] | 2008 | struct qla_hw_data *ha = vha->hw; |
| 2009 | struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; |
| 2010 | uint32_t __iomem *dmp_reg; |
| 2011 | uint32_t *iter_reg; |
| 2012 | uint16_t __iomem *mbx_reg; |
| 2013 | unsigned long flags; |
| 2014 | struct qla83xx_fw_dump *fw; |
Giridhar Malavali | 6246b8a | 2012-02-09 11:15:34 -0800 | [diff] [blame] | 2015 | void *nxt, *nxt_chain; |
| 2016 | uint32_t *last_chain = NULL; |
| 2017 | struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); |
| 2018 | |
Giridhar Malavali | 6246b8a | 2012-02-09 11:15:34 -0800 | [diff] [blame] | 2019 | flags = 0; |
Hiral Patel | 61f098d | 2014-04-11 16:54:21 -0400 | [diff] [blame] | 2020 | ha->fw_dump_cap_flags = 0; |
Giridhar Malavali | 6246b8a | 2012-02-09 11:15:34 -0800 | [diff] [blame] | 2021 | |
Bart Van Assche | 8d16366 | 2015-07-09 07:25:46 -0700 | [diff] [blame] | 2022 | #ifndef __CHECKER__ |
Giridhar Malavali | 6246b8a | 2012-02-09 11:15:34 -0800 | [diff] [blame] | 2023 | if (!hardware_locked) |
| 2024 | spin_lock_irqsave(&ha->hardware_lock, flags); |
Bart Van Assche | 8d16366 | 2015-07-09 07:25:46 -0700 | [diff] [blame] | 2025 | #endif |
Giridhar Malavali | 6246b8a | 2012-02-09 11:15:34 -0800 | [diff] [blame] | 2026 | |
| 2027 | if (!ha->fw_dump) { |
| 2028 | ql_log(ql_log_warn, vha, 0xd00c, |
| 2029 | "No buffer available for dump!!!\n"); |
| 2030 | goto qla83xx_fw_dump_failed; |
| 2031 | } |
| 2032 | |
| 2033 | if (ha->fw_dumped) { |
| 2034 | ql_log(ql_log_warn, vha, 0xd00d, |
| 2035 | "Firmware has been previously dumped (%p) -- ignoring " |
| 2036 | "request...\n", ha->fw_dump); |
| 2037 | goto qla83xx_fw_dump_failed; |
| 2038 | } |
| 2039 | fw = &ha->fw_dump->isp.isp83; |
| 2040 | qla2xxx_prep_dump(ha, ha->fw_dump); |
| 2041 | |
| 2042 | fw->host_status = htonl(RD_REG_DWORD(®->host_status)); |
| 2043 | |
Hiral Patel | 2f389fc | 2014-04-11 16:54:20 -0400 | [diff] [blame] | 2044 | /* |
| 2045 | * Pause RISC. No need to track timeout, as resetting the chip |
| 2046 | * is the right approach incase of pause timeout |
| 2047 | */ |
Hiral Patel | 61f098d | 2014-04-11 16:54:21 -0400 | [diff] [blame] | 2048 | qla24xx_pause_risc(reg, ha); |
Giridhar Malavali | 6246b8a | 2012-02-09 11:15:34 -0800 | [diff] [blame] | 2049 | |
| 2050 | WRT_REG_DWORD(®->iobase_addr, 0x6000); |
| 2051 | dmp_reg = ®->iobase_window; |
Bart Van Assche | 52c8282 | 2015-07-09 07:23:26 -0700 | [diff] [blame] | 2052 | RD_REG_DWORD(dmp_reg); |
Giridhar Malavali | 6246b8a | 2012-02-09 11:15:34 -0800 | [diff] [blame] | 2053 | WRT_REG_DWORD(dmp_reg, 0); |
| 2054 | |
| 2055 | dmp_reg = ®->unused_4_1[0]; |
Bart Van Assche | 52c8282 | 2015-07-09 07:23:26 -0700 | [diff] [blame] | 2056 | RD_REG_DWORD(dmp_reg); |
Giridhar Malavali | 6246b8a | 2012-02-09 11:15:34 -0800 | [diff] [blame] | 2057 | WRT_REG_DWORD(dmp_reg, 0); |
| 2058 | |
| 2059 | WRT_REG_DWORD(®->iobase_addr, 0x6010); |
| 2060 | dmp_reg = ®->unused_4_1[2]; |
Bart Van Assche | 52c8282 | 2015-07-09 07:23:26 -0700 | [diff] [blame] | 2061 | RD_REG_DWORD(dmp_reg); |
Giridhar Malavali | 6246b8a | 2012-02-09 11:15:34 -0800 | [diff] [blame] | 2062 | WRT_REG_DWORD(dmp_reg, 0); |
| 2063 | |
| 2064 | /* select PCR and disable ecc checking and correction */ |
| 2065 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); |
| 2066 | RD_REG_DWORD(®->iobase_addr); |
| 2067 | WRT_REG_DWORD(®->iobase_select, 0x60000000); /* write to F0h = PCR */ |
| 2068 | |
| 2069 | /* Host/Risc registers. */ |
| 2070 | iter_reg = fw->host_risc_reg; |
| 2071 | iter_reg = qla24xx_read_window(reg, 0x7000, 16, iter_reg); |
| 2072 | iter_reg = qla24xx_read_window(reg, 0x7010, 16, iter_reg); |
| 2073 | qla24xx_read_window(reg, 0x7040, 16, iter_reg); |
| 2074 | |
| 2075 | /* PCIe registers. */ |
| 2076 | WRT_REG_DWORD(®->iobase_addr, 0x7C00); |
| 2077 | RD_REG_DWORD(®->iobase_addr); |
| 2078 | WRT_REG_DWORD(®->iobase_window, 0x01); |
| 2079 | dmp_reg = ®->iobase_c4; |
Joe Carnuccio | da08ef5 | 2016-01-27 12:03:34 -0500 | [diff] [blame] | 2080 | fw->pcie_regs[0] = htonl(RD_REG_DWORD(dmp_reg)); |
| 2081 | dmp_reg++; |
| 2082 | fw->pcie_regs[1] = htonl(RD_REG_DWORD(dmp_reg)); |
| 2083 | dmp_reg++; |
Giridhar Malavali | 6246b8a | 2012-02-09 11:15:34 -0800 | [diff] [blame] | 2084 | fw->pcie_regs[2] = htonl(RD_REG_DWORD(dmp_reg)); |
| 2085 | fw->pcie_regs[3] = htonl(RD_REG_DWORD(®->iobase_window)); |
| 2086 | |
| 2087 | WRT_REG_DWORD(®->iobase_window, 0x00); |
| 2088 | RD_REG_DWORD(®->iobase_window); |
| 2089 | |
| 2090 | /* Host interface registers. */ |
| 2091 | dmp_reg = ®->flash_addr; |
Joe Carnuccio | da08ef5 | 2016-01-27 12:03:34 -0500 | [diff] [blame] | 2092 | for (cnt = 0; cnt < sizeof(fw->host_reg) / 4; cnt++, dmp_reg++) |
| 2093 | fw->host_reg[cnt] = htonl(RD_REG_DWORD(dmp_reg)); |
Giridhar Malavali | 6246b8a | 2012-02-09 11:15:34 -0800 | [diff] [blame] | 2094 | |
| 2095 | /* Disable interrupts. */ |
| 2096 | WRT_REG_DWORD(®->ictrl, 0); |
| 2097 | RD_REG_DWORD(®->ictrl); |
| 2098 | |
| 2099 | /* Shadow registers. */ |
| 2100 | WRT_REG_DWORD(®->iobase_addr, 0x0F70); |
| 2101 | RD_REG_DWORD(®->iobase_addr); |
| 2102 | WRT_REG_DWORD(®->iobase_select, 0xB0000000); |
| 2103 | fw->shadow_reg[0] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
| 2104 | |
| 2105 | WRT_REG_DWORD(®->iobase_select, 0xB0100000); |
| 2106 | fw->shadow_reg[1] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
| 2107 | |
| 2108 | WRT_REG_DWORD(®->iobase_select, 0xB0200000); |
| 2109 | fw->shadow_reg[2] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
| 2110 | |
| 2111 | WRT_REG_DWORD(®->iobase_select, 0xB0300000); |
| 2112 | fw->shadow_reg[3] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
| 2113 | |
| 2114 | WRT_REG_DWORD(®->iobase_select, 0xB0400000); |
| 2115 | fw->shadow_reg[4] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
| 2116 | |
| 2117 | WRT_REG_DWORD(®->iobase_select, 0xB0500000); |
| 2118 | fw->shadow_reg[5] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
| 2119 | |
| 2120 | WRT_REG_DWORD(®->iobase_select, 0xB0600000); |
| 2121 | fw->shadow_reg[6] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
| 2122 | |
| 2123 | WRT_REG_DWORD(®->iobase_select, 0xB0700000); |
| 2124 | fw->shadow_reg[7] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
| 2125 | |
| 2126 | WRT_REG_DWORD(®->iobase_select, 0xB0800000); |
| 2127 | fw->shadow_reg[8] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
| 2128 | |
| 2129 | WRT_REG_DWORD(®->iobase_select, 0xB0900000); |
| 2130 | fw->shadow_reg[9] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
| 2131 | |
| 2132 | WRT_REG_DWORD(®->iobase_select, 0xB0A00000); |
| 2133 | fw->shadow_reg[10] = htonl(RD_REG_DWORD(®->iobase_sdata)); |
| 2134 | |
| 2135 | /* RISC I/O register. */ |
| 2136 | WRT_REG_DWORD(®->iobase_addr, 0x0010); |
| 2137 | fw->risc_io_reg = htonl(RD_REG_DWORD(®->iobase_window)); |
| 2138 | |
| 2139 | /* Mailbox registers. */ |
| 2140 | mbx_reg = ®->mailbox0; |
Joe Carnuccio | 74939a0 | 2017-05-24 18:06:23 -0700 | [diff] [blame] | 2141 | for (cnt = 0; cnt < sizeof(fw->mailbox_reg) / 2; cnt++, mbx_reg++) |
Joe Carnuccio | da08ef5 | 2016-01-27 12:03:34 -0500 | [diff] [blame] | 2142 | fw->mailbox_reg[cnt] = htons(RD_REG_WORD(mbx_reg)); |
Giridhar Malavali | 6246b8a | 2012-02-09 11:15:34 -0800 | [diff] [blame] | 2143 | |
| 2144 | /* Transfer sequence registers. */ |
| 2145 | iter_reg = fw->xseq_gp_reg; |
| 2146 | iter_reg = qla24xx_read_window(reg, 0xBE00, 16, iter_reg); |
| 2147 | iter_reg = qla24xx_read_window(reg, 0xBE10, 16, iter_reg); |
| 2148 | iter_reg = qla24xx_read_window(reg, 0xBE20, 16, iter_reg); |
| 2149 | iter_reg = qla24xx_read_window(reg, 0xBE30, 16, iter_reg); |
| 2150 | iter_reg = qla24xx_read_window(reg, 0xBE40, 16, iter_reg); |
| 2151 | iter_reg = qla24xx_read_window(reg, 0xBE50, 16, iter_reg); |
| 2152 | iter_reg = qla24xx_read_window(reg, 0xBE60, 16, iter_reg); |
| 2153 | iter_reg = qla24xx_read_window(reg, 0xBE70, 16, iter_reg); |
| 2154 | iter_reg = qla24xx_read_window(reg, 0xBF00, 16, iter_reg); |
| 2155 | iter_reg = qla24xx_read_window(reg, 0xBF10, 16, iter_reg); |
| 2156 | iter_reg = qla24xx_read_window(reg, 0xBF20, 16, iter_reg); |
| 2157 | iter_reg = qla24xx_read_window(reg, 0xBF30, 16, iter_reg); |
| 2158 | iter_reg = qla24xx_read_window(reg, 0xBF40, 16, iter_reg); |
| 2159 | iter_reg = qla24xx_read_window(reg, 0xBF50, 16, iter_reg); |
| 2160 | iter_reg = qla24xx_read_window(reg, 0xBF60, 16, iter_reg); |
| 2161 | qla24xx_read_window(reg, 0xBF70, 16, iter_reg); |
| 2162 | |
| 2163 | iter_reg = fw->xseq_0_reg; |
| 2164 | iter_reg = qla24xx_read_window(reg, 0xBFC0, 16, iter_reg); |
| 2165 | iter_reg = qla24xx_read_window(reg, 0xBFD0, 16, iter_reg); |
| 2166 | qla24xx_read_window(reg, 0xBFE0, 16, iter_reg); |
| 2167 | |
| 2168 | qla24xx_read_window(reg, 0xBFF0, 16, fw->xseq_1_reg); |
| 2169 | |
| 2170 | qla24xx_read_window(reg, 0xBEF0, 16, fw->xseq_2_reg); |
| 2171 | |
| 2172 | /* Receive sequence registers. */ |
| 2173 | iter_reg = fw->rseq_gp_reg; |
| 2174 | iter_reg = qla24xx_read_window(reg, 0xFE00, 16, iter_reg); |
| 2175 | iter_reg = qla24xx_read_window(reg, 0xFE10, 16, iter_reg); |
| 2176 | iter_reg = qla24xx_read_window(reg, 0xFE20, 16, iter_reg); |
| 2177 | iter_reg = qla24xx_read_window(reg, 0xFE30, 16, iter_reg); |
| 2178 | iter_reg = qla24xx_read_window(reg, 0xFE40, 16, iter_reg); |
| 2179 | iter_reg = qla24xx_read_window(reg, 0xFE50, 16, iter_reg); |
| 2180 | iter_reg = qla24xx_read_window(reg, 0xFE60, 16, iter_reg); |
| 2181 | iter_reg = qla24xx_read_window(reg, 0xFE70, 16, iter_reg); |
| 2182 | iter_reg = qla24xx_read_window(reg, 0xFF00, 16, iter_reg); |
| 2183 | iter_reg = qla24xx_read_window(reg, 0xFF10, 16, iter_reg); |
| 2184 | iter_reg = qla24xx_read_window(reg, 0xFF20, 16, iter_reg); |
| 2185 | iter_reg = qla24xx_read_window(reg, 0xFF30, 16, iter_reg); |
| 2186 | iter_reg = qla24xx_read_window(reg, 0xFF40, 16, iter_reg); |
| 2187 | iter_reg = qla24xx_read_window(reg, 0xFF50, 16, iter_reg); |
| 2188 | iter_reg = qla24xx_read_window(reg, 0xFF60, 16, iter_reg); |
| 2189 | qla24xx_read_window(reg, 0xFF70, 16, iter_reg); |
| 2190 | |
| 2191 | iter_reg = fw->rseq_0_reg; |
| 2192 | iter_reg = qla24xx_read_window(reg, 0xFFC0, 16, iter_reg); |
| 2193 | qla24xx_read_window(reg, 0xFFD0, 16, iter_reg); |
| 2194 | |
| 2195 | qla24xx_read_window(reg, 0xFFE0, 16, fw->rseq_1_reg); |
| 2196 | qla24xx_read_window(reg, 0xFFF0, 16, fw->rseq_2_reg); |
| 2197 | qla24xx_read_window(reg, 0xFEF0, 16, fw->rseq_3_reg); |
| 2198 | |
| 2199 | /* Auxiliary sequence registers. */ |
| 2200 | iter_reg = fw->aseq_gp_reg; |
| 2201 | iter_reg = qla24xx_read_window(reg, 0xB000, 16, iter_reg); |
| 2202 | iter_reg = qla24xx_read_window(reg, 0xB010, 16, iter_reg); |
| 2203 | iter_reg = qla24xx_read_window(reg, 0xB020, 16, iter_reg); |
| 2204 | iter_reg = qla24xx_read_window(reg, 0xB030, 16, iter_reg); |
| 2205 | iter_reg = qla24xx_read_window(reg, 0xB040, 16, iter_reg); |
| 2206 | iter_reg = qla24xx_read_window(reg, 0xB050, 16, iter_reg); |
| 2207 | iter_reg = qla24xx_read_window(reg, 0xB060, 16, iter_reg); |
| 2208 | iter_reg = qla24xx_read_window(reg, 0xB070, 16, iter_reg); |
| 2209 | iter_reg = qla24xx_read_window(reg, 0xB100, 16, iter_reg); |
| 2210 | iter_reg = qla24xx_read_window(reg, 0xB110, 16, iter_reg); |
| 2211 | iter_reg = qla24xx_read_window(reg, 0xB120, 16, iter_reg); |
| 2212 | iter_reg = qla24xx_read_window(reg, 0xB130, 16, iter_reg); |
| 2213 | iter_reg = qla24xx_read_window(reg, 0xB140, 16, iter_reg); |
| 2214 | iter_reg = qla24xx_read_window(reg, 0xB150, 16, iter_reg); |
| 2215 | iter_reg = qla24xx_read_window(reg, 0xB160, 16, iter_reg); |
| 2216 | qla24xx_read_window(reg, 0xB170, 16, iter_reg); |
| 2217 | |
| 2218 | iter_reg = fw->aseq_0_reg; |
| 2219 | iter_reg = qla24xx_read_window(reg, 0xB0C0, 16, iter_reg); |
| 2220 | qla24xx_read_window(reg, 0xB0D0, 16, iter_reg); |
| 2221 | |
| 2222 | qla24xx_read_window(reg, 0xB0E0, 16, fw->aseq_1_reg); |
| 2223 | qla24xx_read_window(reg, 0xB0F0, 16, fw->aseq_2_reg); |
| 2224 | qla24xx_read_window(reg, 0xB1F0, 16, fw->aseq_3_reg); |
| 2225 | |
| 2226 | /* Command DMA registers. */ |
| 2227 | iter_reg = fw->cmd_dma_reg; |
| 2228 | iter_reg = qla24xx_read_window(reg, 0x7100, 16, iter_reg); |
| 2229 | iter_reg = qla24xx_read_window(reg, 0x7120, 16, iter_reg); |
| 2230 | iter_reg = qla24xx_read_window(reg, 0x7130, 16, iter_reg); |
| 2231 | qla24xx_read_window(reg, 0x71F0, 16, iter_reg); |
| 2232 | |
| 2233 | /* Queues. */ |
| 2234 | iter_reg = fw->req0_dma_reg; |
| 2235 | iter_reg = qla24xx_read_window(reg, 0x7200, 8, iter_reg); |
| 2236 | dmp_reg = ®->iobase_q; |
Joe Carnuccio | da08ef5 | 2016-01-27 12:03:34 -0500 | [diff] [blame] | 2237 | for (cnt = 0; cnt < 7; cnt++, dmp_reg++) |
| 2238 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg)); |
Giridhar Malavali | 6246b8a | 2012-02-09 11:15:34 -0800 | [diff] [blame] | 2239 | |
| 2240 | iter_reg = fw->resp0_dma_reg; |
| 2241 | iter_reg = qla24xx_read_window(reg, 0x7300, 8, iter_reg); |
| 2242 | dmp_reg = ®->iobase_q; |
Joe Carnuccio | da08ef5 | 2016-01-27 12:03:34 -0500 | [diff] [blame] | 2243 | for (cnt = 0; cnt < 7; cnt++, dmp_reg++) |
| 2244 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg)); |
Giridhar Malavali | 6246b8a | 2012-02-09 11:15:34 -0800 | [diff] [blame] | 2245 | |
| 2246 | iter_reg = fw->req1_dma_reg; |
| 2247 | iter_reg = qla24xx_read_window(reg, 0x7400, 8, iter_reg); |
| 2248 | dmp_reg = ®->iobase_q; |
Joe Carnuccio | da08ef5 | 2016-01-27 12:03:34 -0500 | [diff] [blame] | 2249 | for (cnt = 0; cnt < 7; cnt++, dmp_reg++) |
| 2250 | *iter_reg++ = htonl(RD_REG_DWORD(dmp_reg)); |
Giridhar Malavali | 6246b8a | 2012-02-09 11:15:34 -0800 | [diff] [blame] | 2251 | |
| 2252 | /* Transmit DMA registers. */ |
| 2253 | iter_reg = fw->xmt0_dma_reg; |
| 2254 | iter_reg = qla24xx_read_window(reg, 0x7600, 16, iter_reg); |
| 2255 | qla24xx_read_window(reg, 0x7610, 16, iter_reg); |
| 2256 | |
| 2257 | iter_reg = fw->xmt1_dma_reg; |
| 2258 | iter_reg = qla24xx_read_window(reg, 0x7620, 16, iter_reg); |
| 2259 | qla24xx_read_window(reg, 0x7630, 16, iter_reg); |
| 2260 | |
| 2261 | iter_reg = fw->xmt2_dma_reg; |
| 2262 | iter_reg = qla24xx_read_window(reg, 0x7640, 16, iter_reg); |
| 2263 | qla24xx_read_window(reg, 0x7650, 16, iter_reg); |
| 2264 | |
| 2265 | iter_reg = fw->xmt3_dma_reg; |
| 2266 | iter_reg = qla24xx_read_window(reg, 0x7660, 16, iter_reg); |
| 2267 | qla24xx_read_window(reg, 0x7670, 16, iter_reg); |
| 2268 | |
| 2269 | iter_reg = fw->xmt4_dma_reg; |
| 2270 | iter_reg = qla24xx_read_window(reg, 0x7680, 16, iter_reg); |
| 2271 | qla24xx_read_window(reg, 0x7690, 16, iter_reg); |
| 2272 | |
| 2273 | qla24xx_read_window(reg, 0x76A0, 16, fw->xmt_data_dma_reg); |
| 2274 | |
| 2275 | /* Receive DMA registers. */ |
| 2276 | iter_reg = fw->rcvt0_data_dma_reg; |
| 2277 | iter_reg = qla24xx_read_window(reg, 0x7700, 16, iter_reg); |
| 2278 | qla24xx_read_window(reg, 0x7710, 16, iter_reg); |
| 2279 | |
| 2280 | iter_reg = fw->rcvt1_data_dma_reg; |
| 2281 | iter_reg = qla24xx_read_window(reg, 0x7720, 16, iter_reg); |
| 2282 | qla24xx_read_window(reg, 0x7730, 16, iter_reg); |
| 2283 | |
| 2284 | /* RISC registers. */ |
| 2285 | iter_reg = fw->risc_gp_reg; |
| 2286 | iter_reg = qla24xx_read_window(reg, 0x0F00, 16, iter_reg); |
| 2287 | iter_reg = qla24xx_read_window(reg, 0x0F10, 16, iter_reg); |
| 2288 | iter_reg = qla24xx_read_window(reg, 0x0F20, 16, iter_reg); |
| 2289 | iter_reg = qla24xx_read_window(reg, 0x0F30, 16, iter_reg); |
| 2290 | iter_reg = qla24xx_read_window(reg, 0x0F40, 16, iter_reg); |
| 2291 | iter_reg = qla24xx_read_window(reg, 0x0F50, 16, iter_reg); |
| 2292 | iter_reg = qla24xx_read_window(reg, 0x0F60, 16, iter_reg); |
| 2293 | qla24xx_read_window(reg, 0x0F70, 16, iter_reg); |
| 2294 | |
| 2295 | /* Local memory controller registers. */ |
| 2296 | iter_reg = fw->lmc_reg; |
| 2297 | iter_reg = qla24xx_read_window(reg, 0x3000, 16, iter_reg); |
| 2298 | iter_reg = qla24xx_read_window(reg, 0x3010, 16, iter_reg); |
| 2299 | iter_reg = qla24xx_read_window(reg, 0x3020, 16, iter_reg); |
| 2300 | iter_reg = qla24xx_read_window(reg, 0x3030, 16, iter_reg); |
| 2301 | iter_reg = qla24xx_read_window(reg, 0x3040, 16, iter_reg); |
| 2302 | iter_reg = qla24xx_read_window(reg, 0x3050, 16, iter_reg); |
| 2303 | iter_reg = qla24xx_read_window(reg, 0x3060, 16, iter_reg); |
| 2304 | qla24xx_read_window(reg, 0x3070, 16, iter_reg); |
| 2305 | |
| 2306 | /* Fibre Protocol Module registers. */ |
| 2307 | iter_reg = fw->fpm_hdw_reg; |
| 2308 | iter_reg = qla24xx_read_window(reg, 0x4000, 16, iter_reg); |
| 2309 | iter_reg = qla24xx_read_window(reg, 0x4010, 16, iter_reg); |
| 2310 | iter_reg = qla24xx_read_window(reg, 0x4020, 16, iter_reg); |
| 2311 | iter_reg = qla24xx_read_window(reg, 0x4030, 16, iter_reg); |
| 2312 | iter_reg = qla24xx_read_window(reg, 0x4040, 16, iter_reg); |
| 2313 | iter_reg = qla24xx_read_window(reg, 0x4050, 16, iter_reg); |
| 2314 | iter_reg = qla24xx_read_window(reg, 0x4060, 16, iter_reg); |
| 2315 | iter_reg = qla24xx_read_window(reg, 0x4070, 16, iter_reg); |
| 2316 | iter_reg = qla24xx_read_window(reg, 0x4080, 16, iter_reg); |
| 2317 | iter_reg = qla24xx_read_window(reg, 0x4090, 16, iter_reg); |
| 2318 | iter_reg = qla24xx_read_window(reg, 0x40A0, 16, iter_reg); |
| 2319 | iter_reg = qla24xx_read_window(reg, 0x40B0, 16, iter_reg); |
| 2320 | iter_reg = qla24xx_read_window(reg, 0x40C0, 16, iter_reg); |
| 2321 | iter_reg = qla24xx_read_window(reg, 0x40D0, 16, iter_reg); |
| 2322 | iter_reg = qla24xx_read_window(reg, 0x40E0, 16, iter_reg); |
| 2323 | qla24xx_read_window(reg, 0x40F0, 16, iter_reg); |
| 2324 | |
| 2325 | /* RQ0 Array registers. */ |
| 2326 | iter_reg = fw->rq0_array_reg; |
| 2327 | iter_reg = qla24xx_read_window(reg, 0x5C00, 16, iter_reg); |
| 2328 | iter_reg = qla24xx_read_window(reg, 0x5C10, 16, iter_reg); |
| 2329 | iter_reg = qla24xx_read_window(reg, 0x5C20, 16, iter_reg); |
| 2330 | iter_reg = qla24xx_read_window(reg, 0x5C30, 16, iter_reg); |
| 2331 | iter_reg = qla24xx_read_window(reg, 0x5C40, 16, iter_reg); |
| 2332 | iter_reg = qla24xx_read_window(reg, 0x5C50, 16, iter_reg); |
| 2333 | iter_reg = qla24xx_read_window(reg, 0x5C60, 16, iter_reg); |
| 2334 | iter_reg = qla24xx_read_window(reg, 0x5C70, 16, iter_reg); |
| 2335 | iter_reg = qla24xx_read_window(reg, 0x5C80, 16, iter_reg); |
| 2336 | iter_reg = qla24xx_read_window(reg, 0x5C90, 16, iter_reg); |
| 2337 | iter_reg = qla24xx_read_window(reg, 0x5CA0, 16, iter_reg); |
| 2338 | iter_reg = qla24xx_read_window(reg, 0x5CB0, 16, iter_reg); |
| 2339 | iter_reg = qla24xx_read_window(reg, 0x5CC0, 16, iter_reg); |
| 2340 | iter_reg = qla24xx_read_window(reg, 0x5CD0, 16, iter_reg); |
| 2341 | iter_reg = qla24xx_read_window(reg, 0x5CE0, 16, iter_reg); |
| 2342 | qla24xx_read_window(reg, 0x5CF0, 16, iter_reg); |
| 2343 | |
| 2344 | /* RQ1 Array registers. */ |
| 2345 | iter_reg = fw->rq1_array_reg; |
| 2346 | iter_reg = qla24xx_read_window(reg, 0x5D00, 16, iter_reg); |
| 2347 | iter_reg = qla24xx_read_window(reg, 0x5D10, 16, iter_reg); |
| 2348 | iter_reg = qla24xx_read_window(reg, 0x5D20, 16, iter_reg); |
| 2349 | iter_reg = qla24xx_read_window(reg, 0x5D30, 16, iter_reg); |
| 2350 | iter_reg = qla24xx_read_window(reg, 0x5D40, 16, iter_reg); |
| 2351 | iter_reg = qla24xx_read_window(reg, 0x5D50, 16, iter_reg); |
| 2352 | iter_reg = qla24xx_read_window(reg, 0x5D60, 16, iter_reg); |
| 2353 | iter_reg = qla24xx_read_window(reg, 0x5D70, 16, iter_reg); |
| 2354 | iter_reg = qla24xx_read_window(reg, 0x5D80, 16, iter_reg); |
| 2355 | iter_reg = qla24xx_read_window(reg, 0x5D90, 16, iter_reg); |
| 2356 | iter_reg = qla24xx_read_window(reg, 0x5DA0, 16, iter_reg); |
| 2357 | iter_reg = qla24xx_read_window(reg, 0x5DB0, 16, iter_reg); |
| 2358 | iter_reg = qla24xx_read_window(reg, 0x5DC0, 16, iter_reg); |
| 2359 | iter_reg = qla24xx_read_window(reg, 0x5DD0, 16, iter_reg); |
| 2360 | iter_reg = qla24xx_read_window(reg, 0x5DE0, 16, iter_reg); |
| 2361 | qla24xx_read_window(reg, 0x5DF0, 16, iter_reg); |
| 2362 | |
| 2363 | /* RP0 Array registers. */ |
| 2364 | iter_reg = fw->rp0_array_reg; |
| 2365 | iter_reg = qla24xx_read_window(reg, 0x5E00, 16, iter_reg); |
| 2366 | iter_reg = qla24xx_read_window(reg, 0x5E10, 16, iter_reg); |
| 2367 | iter_reg = qla24xx_read_window(reg, 0x5E20, 16, iter_reg); |
| 2368 | iter_reg = qla24xx_read_window(reg, 0x5E30, 16, iter_reg); |
| 2369 | iter_reg = qla24xx_read_window(reg, 0x5E40, 16, iter_reg); |
| 2370 | iter_reg = qla24xx_read_window(reg, 0x5E50, 16, iter_reg); |
| 2371 | iter_reg = qla24xx_read_window(reg, 0x5E60, 16, iter_reg); |
| 2372 | iter_reg = qla24xx_read_window(reg, 0x5E70, 16, iter_reg); |
| 2373 | iter_reg = qla24xx_read_window(reg, 0x5E80, 16, iter_reg); |
| 2374 | iter_reg = qla24xx_read_window(reg, 0x5E90, 16, iter_reg); |
| 2375 | iter_reg = qla24xx_read_window(reg, 0x5EA0, 16, iter_reg); |
| 2376 | iter_reg = qla24xx_read_window(reg, 0x5EB0, 16, iter_reg); |
| 2377 | iter_reg = qla24xx_read_window(reg, 0x5EC0, 16, iter_reg); |
| 2378 | iter_reg = qla24xx_read_window(reg, 0x5ED0, 16, iter_reg); |
| 2379 | iter_reg = qla24xx_read_window(reg, 0x5EE0, 16, iter_reg); |
| 2380 | qla24xx_read_window(reg, 0x5EF0, 16, iter_reg); |
| 2381 | |
| 2382 | /* RP1 Array registers. */ |
| 2383 | iter_reg = fw->rp1_array_reg; |
| 2384 | iter_reg = qla24xx_read_window(reg, 0x5F00, 16, iter_reg); |
| 2385 | iter_reg = qla24xx_read_window(reg, 0x5F10, 16, iter_reg); |
| 2386 | iter_reg = qla24xx_read_window(reg, 0x5F20, 16, iter_reg); |
| 2387 | iter_reg = qla24xx_read_window(reg, 0x5F30, 16, iter_reg); |
| 2388 | iter_reg = qla24xx_read_window(reg, 0x5F40, 16, iter_reg); |
| 2389 | iter_reg = qla24xx_read_window(reg, 0x5F50, 16, iter_reg); |
| 2390 | iter_reg = qla24xx_read_window(reg, 0x5F60, 16, iter_reg); |
| 2391 | iter_reg = qla24xx_read_window(reg, 0x5F70, 16, iter_reg); |
| 2392 | iter_reg = qla24xx_read_window(reg, 0x5F80, 16, iter_reg); |
| 2393 | iter_reg = qla24xx_read_window(reg, 0x5F90, 16, iter_reg); |
| 2394 | iter_reg = qla24xx_read_window(reg, 0x5FA0, 16, iter_reg); |
| 2395 | iter_reg = qla24xx_read_window(reg, 0x5FB0, 16, iter_reg); |
| 2396 | iter_reg = qla24xx_read_window(reg, 0x5FC0, 16, iter_reg); |
| 2397 | iter_reg = qla24xx_read_window(reg, 0x5FD0, 16, iter_reg); |
| 2398 | iter_reg = qla24xx_read_window(reg, 0x5FE0, 16, iter_reg); |
| 2399 | qla24xx_read_window(reg, 0x5FF0, 16, iter_reg); |
| 2400 | |
| 2401 | iter_reg = fw->at0_array_reg; |
| 2402 | iter_reg = qla24xx_read_window(reg, 0x7080, 16, iter_reg); |
| 2403 | iter_reg = qla24xx_read_window(reg, 0x7090, 16, iter_reg); |
| 2404 | iter_reg = qla24xx_read_window(reg, 0x70A0, 16, iter_reg); |
| 2405 | iter_reg = qla24xx_read_window(reg, 0x70B0, 16, iter_reg); |
| 2406 | iter_reg = qla24xx_read_window(reg, 0x70C0, 16, iter_reg); |
| 2407 | iter_reg = qla24xx_read_window(reg, 0x70D0, 16, iter_reg); |
| 2408 | iter_reg = qla24xx_read_window(reg, 0x70E0, 16, iter_reg); |
| 2409 | qla24xx_read_window(reg, 0x70F0, 16, iter_reg); |
| 2410 | |
| 2411 | /* I/O Queue Control registers. */ |
| 2412 | qla24xx_read_window(reg, 0x7800, 16, fw->queue_control_reg); |
| 2413 | |
| 2414 | /* Frame Buffer registers. */ |
| 2415 | iter_reg = fw->fb_hdw_reg; |
| 2416 | iter_reg = qla24xx_read_window(reg, 0x6000, 16, iter_reg); |
| 2417 | iter_reg = qla24xx_read_window(reg, 0x6010, 16, iter_reg); |
| 2418 | iter_reg = qla24xx_read_window(reg, 0x6020, 16, iter_reg); |
| 2419 | iter_reg = qla24xx_read_window(reg, 0x6030, 16, iter_reg); |
| 2420 | iter_reg = qla24xx_read_window(reg, 0x6040, 16, iter_reg); |
| 2421 | iter_reg = qla24xx_read_window(reg, 0x6060, 16, iter_reg); |
| 2422 | iter_reg = qla24xx_read_window(reg, 0x6070, 16, iter_reg); |
| 2423 | iter_reg = qla24xx_read_window(reg, 0x6100, 16, iter_reg); |
| 2424 | iter_reg = qla24xx_read_window(reg, 0x6130, 16, iter_reg); |
| 2425 | iter_reg = qla24xx_read_window(reg, 0x6150, 16, iter_reg); |
| 2426 | iter_reg = qla24xx_read_window(reg, 0x6170, 16, iter_reg); |
| 2427 | iter_reg = qla24xx_read_window(reg, 0x6190, 16, iter_reg); |
| 2428 | iter_reg = qla24xx_read_window(reg, 0x61B0, 16, iter_reg); |
| 2429 | iter_reg = qla24xx_read_window(reg, 0x61C0, 16, iter_reg); |
| 2430 | iter_reg = qla24xx_read_window(reg, 0x6530, 16, iter_reg); |
| 2431 | iter_reg = qla24xx_read_window(reg, 0x6540, 16, iter_reg); |
| 2432 | iter_reg = qla24xx_read_window(reg, 0x6550, 16, iter_reg); |
| 2433 | iter_reg = qla24xx_read_window(reg, 0x6560, 16, iter_reg); |
| 2434 | iter_reg = qla24xx_read_window(reg, 0x6570, 16, iter_reg); |
| 2435 | iter_reg = qla24xx_read_window(reg, 0x6580, 16, iter_reg); |
| 2436 | iter_reg = qla24xx_read_window(reg, 0x6590, 16, iter_reg); |
| 2437 | iter_reg = qla24xx_read_window(reg, 0x65A0, 16, iter_reg); |
| 2438 | iter_reg = qla24xx_read_window(reg, 0x65B0, 16, iter_reg); |
| 2439 | iter_reg = qla24xx_read_window(reg, 0x65C0, 16, iter_reg); |
| 2440 | iter_reg = qla24xx_read_window(reg, 0x65D0, 16, iter_reg); |
| 2441 | iter_reg = qla24xx_read_window(reg, 0x65E0, 16, iter_reg); |
| 2442 | qla24xx_read_window(reg, 0x6F00, 16, iter_reg); |
| 2443 | |
| 2444 | /* Multi queue registers */ |
| 2445 | nxt_chain = qla25xx_copy_mq(ha, (void *)ha->fw_dump + ha->chain_offset, |
| 2446 | &last_chain); |
| 2447 | |
| 2448 | rval = qla24xx_soft_reset(ha); |
| 2449 | if (rval != QLA_SUCCESS) { |
| 2450 | ql_log(ql_log_warn, vha, 0xd00e, |
| 2451 | "SOFT RESET FAILED, forcing continuation of dump!!!\n"); |
| 2452 | rval = QLA_SUCCESS; |
| 2453 | |
| 2454 | ql_log(ql_log_warn, vha, 0xd00f, "try a bigger hammer!!!\n"); |
| 2455 | |
| 2456 | WRT_REG_DWORD(®->hccr, HCCRX_SET_RISC_RESET); |
| 2457 | RD_REG_DWORD(®->hccr); |
| 2458 | |
| 2459 | WRT_REG_DWORD(®->hccr, HCCRX_REL_RISC_PAUSE); |
| 2460 | RD_REG_DWORD(®->hccr); |
| 2461 | |
| 2462 | WRT_REG_DWORD(®->hccr, HCCRX_CLR_RISC_RESET); |
| 2463 | RD_REG_DWORD(®->hccr); |
| 2464 | |
| 2465 | for (cnt = 30000; cnt && (RD_REG_WORD(®->mailbox0)); cnt--) |
| 2466 | udelay(5); |
| 2467 | |
| 2468 | if (!cnt) { |
| 2469 | nxt = fw->code_ram; |
Saurav Kashyap | 8c0bc70 | 2012-11-21 02:40:35 -0500 | [diff] [blame] | 2470 | nxt += sizeof(fw->code_ram); |
Giridhar Malavali | 6246b8a | 2012-02-09 11:15:34 -0800 | [diff] [blame] | 2471 | nxt += (ha->fw_memory_size - 0x100000 + 1); |
| 2472 | goto copy_queue; |
Hiral Patel | 61f098d | 2014-04-11 16:54:21 -0400 | [diff] [blame] | 2473 | } else { |
| 2474 | set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags); |
Giridhar Malavali | 6246b8a | 2012-02-09 11:15:34 -0800 | [diff] [blame] | 2475 | ql_log(ql_log_warn, vha, 0xd010, |
| 2476 | "bigger hammer success?\n"); |
Hiral Patel | 61f098d | 2014-04-11 16:54:21 -0400 | [diff] [blame] | 2477 | } |
Giridhar Malavali | 6246b8a | 2012-02-09 11:15:34 -0800 | [diff] [blame] | 2478 | } |
| 2479 | |
| 2480 | rval = qla24xx_dump_memory(ha, fw->code_ram, sizeof(fw->code_ram), |
| 2481 | &nxt); |
| 2482 | if (rval != QLA_SUCCESS) |
| 2483 | goto qla83xx_fw_dump_failed_0; |
| 2484 | |
| 2485 | copy_queue: |
| 2486 | nxt = qla2xxx_copy_queues(ha, nxt); |
| 2487 | |
Bart Van Assche | 7f544d0 | 2013-06-25 11:27:27 -0400 | [diff] [blame] | 2488 | qla24xx_copy_eft(ha, nxt); |
Giridhar Malavali | 6246b8a | 2012-02-09 11:15:34 -0800 | [diff] [blame] | 2489 | |
| 2490 | /* Chain entries -- started with MQ. */ |
| 2491 | nxt_chain = qla25xx_copy_fce(ha, nxt_chain, &last_chain); |
| 2492 | nxt_chain = qla25xx_copy_mqueues(ha, nxt_chain, &last_chain); |
Nicholas Bellinger | 2d70c10 | 2012-05-15 14:34:28 -0400 | [diff] [blame] | 2493 | nxt_chain = qla2xxx_copy_atioqueues(ha, nxt_chain, &last_chain); |
Quinn Tran | b945e77 | 2017-06-13 20:47:29 -0700 | [diff] [blame] | 2494 | nxt_chain = qla25xx_copy_exlogin(ha, nxt_chain, &last_chain); |
| 2495 | nxt_chain = qla81xx_copy_exchoffld(ha, nxt_chain, &last_chain); |
Giridhar Malavali | 6246b8a | 2012-02-09 11:15:34 -0800 | [diff] [blame] | 2496 | if (last_chain) { |
Bart Van Assche | ad95036 | 2015-07-09 07:24:08 -0700 | [diff] [blame] | 2497 | ha->fw_dump->version |= htonl(DUMP_CHAIN_VARIANT); |
| 2498 | *last_chain |= htonl(DUMP_CHAIN_LAST); |
Giridhar Malavali | 6246b8a | 2012-02-09 11:15:34 -0800 | [diff] [blame] | 2499 | } |
| 2500 | |
| 2501 | /* Adjust valid length. */ |
| 2502 | ha->fw_dump_len = (nxt_chain - (void *)ha->fw_dump); |
| 2503 | |
| 2504 | qla83xx_fw_dump_failed_0: |
| 2505 | qla2xxx_dump_post_process(base_vha, rval); |
| 2506 | |
| 2507 | qla83xx_fw_dump_failed: |
Bart Van Assche | 8d16366 | 2015-07-09 07:25:46 -0700 | [diff] [blame] | 2508 | #ifndef __CHECKER__ |
Giridhar Malavali | 6246b8a | 2012-02-09 11:15:34 -0800 | [diff] [blame] | 2509 | if (!hardware_locked) |
| 2510 | spin_unlock_irqrestore(&ha->hardware_lock, flags); |
Bart Van Assche | 8d16366 | 2015-07-09 07:25:46 -0700 | [diff] [blame] | 2511 | #else |
| 2512 | ; |
| 2513 | #endif |
Giridhar Malavali | 6246b8a | 2012-02-09 11:15:34 -0800 | [diff] [blame] | 2514 | } |
| 2515 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 2516 | /****************************************************************************/ |
| 2517 | /* Driver Debug Functions. */ |
| 2518 | /****************************************************************************/ |
Chad Dupuis | cfb0919 | 2011-11-18 09:03:07 -0800 | [diff] [blame] | 2519 | |
| 2520 | static inline int |
| 2521 | ql_mask_match(uint32_t level) |
| 2522 | { |
Chad Dupuis | cfb0919 | 2011-11-18 09:03:07 -0800 | [diff] [blame] | 2523 | return (level & ql2xextended_error_logging) == level; |
| 2524 | } |
| 2525 | |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2526 | /* |
| 2527 | * This function is for formatting and logging debug information. |
| 2528 | * It is to be used when vha is available. It formats the message |
| 2529 | * and logs it to the messages file. |
| 2530 | * parameters: |
| 2531 | * level: The level of the debug messages to be printed. |
| 2532 | * If ql2xextended_error_logging value is correctly set, |
| 2533 | * this message will appear in the messages file. |
| 2534 | * vha: Pointer to the scsi_qla_host_t. |
| 2535 | * id: This is a unique identifier for the level. It identifies the |
| 2536 | * part of the code from where the message originated. |
| 2537 | * msg: The message to be displayed. |
| 2538 | */ |
| 2539 | void |
Joe Perches | 086b3e8 | 2011-11-18 09:03:05 -0800 | [diff] [blame] | 2540 | ql_dbg(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...) |
| 2541 | { |
| 2542 | va_list va; |
| 2543 | struct va_format vaf; |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2544 | |
Chad Dupuis | cfb0919 | 2011-11-18 09:03:07 -0800 | [diff] [blame] | 2545 | if (!ql_mask_match(level)) |
Joe Perches | 086b3e8 | 2011-11-18 09:03:05 -0800 | [diff] [blame] | 2546 | return; |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2547 | |
Joe Perches | 086b3e8 | 2011-11-18 09:03:05 -0800 | [diff] [blame] | 2548 | va_start(va, fmt); |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2549 | |
Joe Perches | 086b3e8 | 2011-11-18 09:03:05 -0800 | [diff] [blame] | 2550 | vaf.fmt = fmt; |
| 2551 | vaf.va = &va; |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2552 | |
Joe Perches | 086b3e8 | 2011-11-18 09:03:05 -0800 | [diff] [blame] | 2553 | if (vha != NULL) { |
| 2554 | const struct pci_dev *pdev = vha->hw->pdev; |
| 2555 | /* <module-name> <pci-name> <msg-id>:<host> Message */ |
| 2556 | pr_warn("%s [%s]-%04x:%ld: %pV", |
| 2557 | QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, |
| 2558 | vha->host_no, &vaf); |
| 2559 | } else { |
| 2560 | pr_warn("%s [%s]-%04x: : %pV", |
| 2561 | QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf); |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2562 | } |
| 2563 | |
Joe Perches | 086b3e8 | 2011-11-18 09:03:05 -0800 | [diff] [blame] | 2564 | va_end(va); |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2565 | |
| 2566 | } |
| 2567 | |
| 2568 | /* |
| 2569 | * This function is for formatting and logging debug information. |
Masanari Iida | d6a0358 | 2012-08-22 14:20:58 -0400 | [diff] [blame] | 2570 | * It is to be used when vha is not available and pci is available, |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2571 | * i.e., before host allocation. It formats the message and logs it |
| 2572 | * to the messages file. |
| 2573 | * parameters: |
| 2574 | * level: The level of the debug messages to be printed. |
| 2575 | * If ql2xextended_error_logging value is correctly set, |
| 2576 | * this message will appear in the messages file. |
| 2577 | * pdev: Pointer to the struct pci_dev. |
| 2578 | * id: This is a unique id for the level. It identifies the part |
| 2579 | * of the code from where the message originated. |
| 2580 | * msg: The message to be displayed. |
| 2581 | */ |
| 2582 | void |
Joe Perches | 086b3e8 | 2011-11-18 09:03:05 -0800 | [diff] [blame] | 2583 | ql_dbg_pci(uint32_t level, struct pci_dev *pdev, int32_t id, |
| 2584 | const char *fmt, ...) |
| 2585 | { |
| 2586 | va_list va; |
| 2587 | struct va_format vaf; |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2588 | |
| 2589 | if (pdev == NULL) |
| 2590 | return; |
Chad Dupuis | cfb0919 | 2011-11-18 09:03:07 -0800 | [diff] [blame] | 2591 | if (!ql_mask_match(level)) |
Joe Perches | 086b3e8 | 2011-11-18 09:03:05 -0800 | [diff] [blame] | 2592 | return; |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2593 | |
Joe Perches | 086b3e8 | 2011-11-18 09:03:05 -0800 | [diff] [blame] | 2594 | va_start(va, fmt); |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2595 | |
Joe Perches | 086b3e8 | 2011-11-18 09:03:05 -0800 | [diff] [blame] | 2596 | vaf.fmt = fmt; |
| 2597 | vaf.va = &va; |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2598 | |
Joe Perches | 086b3e8 | 2011-11-18 09:03:05 -0800 | [diff] [blame] | 2599 | /* <module-name> <dev-name>:<msg-id> Message */ |
| 2600 | pr_warn("%s [%s]-%04x: : %pV", |
| 2601 | QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, &vaf); |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2602 | |
Joe Perches | 086b3e8 | 2011-11-18 09:03:05 -0800 | [diff] [blame] | 2603 | va_end(va); |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2604 | } |
| 2605 | |
| 2606 | /* |
| 2607 | * This function is for formatting and logging log messages. |
| 2608 | * It is to be used when vha is available. It formats the message |
| 2609 | * and logs it to the messages file. All the messages will be logged |
| 2610 | * irrespective of value of ql2xextended_error_logging. |
| 2611 | * parameters: |
| 2612 | * level: The level of the log messages to be printed in the |
| 2613 | * messages file. |
| 2614 | * vha: Pointer to the scsi_qla_host_t |
| 2615 | * id: This is a unique id for the level. It identifies the |
| 2616 | * part of the code from where the message originated. |
| 2617 | * msg: The message to be displayed. |
| 2618 | */ |
| 2619 | void |
Joe Perches | 086b3e8 | 2011-11-18 09:03:05 -0800 | [diff] [blame] | 2620 | ql_log(uint32_t level, scsi_qla_host_t *vha, int32_t id, const char *fmt, ...) |
| 2621 | { |
| 2622 | va_list va; |
| 2623 | struct va_format vaf; |
| 2624 | char pbuf[128]; |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2625 | |
Joe Perches | 086b3e8 | 2011-11-18 09:03:05 -0800 | [diff] [blame] | 2626 | if (level > ql_errlev) |
| 2627 | return; |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2628 | |
Joe Perches | 086b3e8 | 2011-11-18 09:03:05 -0800 | [diff] [blame] | 2629 | if (vha != NULL) { |
| 2630 | const struct pci_dev *pdev = vha->hw->pdev; |
| 2631 | /* <module-name> <msg-id>:<host> Message */ |
| 2632 | snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x:%ld: ", |
| 2633 | QL_MSGHDR, dev_name(&(pdev->dev)), id, vha->host_no); |
| 2634 | } else { |
| 2635 | snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ", |
| 2636 | QL_MSGHDR, "0000:00:00.0", id); |
| 2637 | } |
| 2638 | pbuf[sizeof(pbuf) - 1] = 0; |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2639 | |
Joe Perches | 086b3e8 | 2011-11-18 09:03:05 -0800 | [diff] [blame] | 2640 | va_start(va, fmt); |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2641 | |
Joe Perches | 086b3e8 | 2011-11-18 09:03:05 -0800 | [diff] [blame] | 2642 | vaf.fmt = fmt; |
| 2643 | vaf.va = &va; |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2644 | |
Joe Perches | 086b3e8 | 2011-11-18 09:03:05 -0800 | [diff] [blame] | 2645 | switch (level) { |
Chad Dupuis | 70a3fc7 | 2012-02-09 11:15:48 -0800 | [diff] [blame] | 2646 | case ql_log_fatal: /* FATAL LOG */ |
Joe Perches | 086b3e8 | 2011-11-18 09:03:05 -0800 | [diff] [blame] | 2647 | pr_crit("%s%pV", pbuf, &vaf); |
| 2648 | break; |
Chad Dupuis | 70a3fc7 | 2012-02-09 11:15:48 -0800 | [diff] [blame] | 2649 | case ql_log_warn: |
Joe Perches | 086b3e8 | 2011-11-18 09:03:05 -0800 | [diff] [blame] | 2650 | pr_err("%s%pV", pbuf, &vaf); |
| 2651 | break; |
Chad Dupuis | 70a3fc7 | 2012-02-09 11:15:48 -0800 | [diff] [blame] | 2652 | case ql_log_info: |
Joe Perches | 086b3e8 | 2011-11-18 09:03:05 -0800 | [diff] [blame] | 2653 | pr_warn("%s%pV", pbuf, &vaf); |
| 2654 | break; |
| 2655 | default: |
| 2656 | pr_info("%s%pV", pbuf, &vaf); |
| 2657 | break; |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2658 | } |
| 2659 | |
Joe Perches | 086b3e8 | 2011-11-18 09:03:05 -0800 | [diff] [blame] | 2660 | va_end(va); |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2661 | } |
| 2662 | |
| 2663 | /* |
| 2664 | * This function is for formatting and logging log messages. |
Masanari Iida | d6a0358 | 2012-08-22 14:20:58 -0400 | [diff] [blame] | 2665 | * It is to be used when vha is not available and pci is available, |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2666 | * i.e., before host allocation. It formats the message and logs |
| 2667 | * it to the messages file. All the messages are logged irrespective |
| 2668 | * of the value of ql2xextended_error_logging. |
| 2669 | * parameters: |
| 2670 | * level: The level of the log messages to be printed in the |
| 2671 | * messages file. |
| 2672 | * pdev: Pointer to the struct pci_dev. |
| 2673 | * id: This is a unique id for the level. It identifies the |
| 2674 | * part of the code from where the message originated. |
| 2675 | * msg: The message to be displayed. |
| 2676 | */ |
| 2677 | void |
Joe Perches | 086b3e8 | 2011-11-18 09:03:05 -0800 | [diff] [blame] | 2678 | ql_log_pci(uint32_t level, struct pci_dev *pdev, int32_t id, |
| 2679 | const char *fmt, ...) |
| 2680 | { |
| 2681 | va_list va; |
| 2682 | struct va_format vaf; |
| 2683 | char pbuf[128]; |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2684 | |
| 2685 | if (pdev == NULL) |
| 2686 | return; |
Joe Perches | 086b3e8 | 2011-11-18 09:03:05 -0800 | [diff] [blame] | 2687 | if (level > ql_errlev) |
| 2688 | return; |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2689 | |
Joe Perches | 086b3e8 | 2011-11-18 09:03:05 -0800 | [diff] [blame] | 2690 | /* <module-name> <dev-name>:<msg-id> Message */ |
| 2691 | snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ", |
| 2692 | QL_MSGHDR, dev_name(&(pdev->dev)), id); |
| 2693 | pbuf[sizeof(pbuf) - 1] = 0; |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2694 | |
Joe Perches | 086b3e8 | 2011-11-18 09:03:05 -0800 | [diff] [blame] | 2695 | va_start(va, fmt); |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2696 | |
Joe Perches | 086b3e8 | 2011-11-18 09:03:05 -0800 | [diff] [blame] | 2697 | vaf.fmt = fmt; |
| 2698 | vaf.va = &va; |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2699 | |
Joe Perches | 086b3e8 | 2011-11-18 09:03:05 -0800 | [diff] [blame] | 2700 | switch (level) { |
Chad Dupuis | 70a3fc7 | 2012-02-09 11:15:48 -0800 | [diff] [blame] | 2701 | case ql_log_fatal: /* FATAL LOG */ |
Joe Perches | 086b3e8 | 2011-11-18 09:03:05 -0800 | [diff] [blame] | 2702 | pr_crit("%s%pV", pbuf, &vaf); |
| 2703 | break; |
Chad Dupuis | 70a3fc7 | 2012-02-09 11:15:48 -0800 | [diff] [blame] | 2704 | case ql_log_warn: |
Joe Perches | 086b3e8 | 2011-11-18 09:03:05 -0800 | [diff] [blame] | 2705 | pr_err("%s%pV", pbuf, &vaf); |
| 2706 | break; |
Chad Dupuis | 70a3fc7 | 2012-02-09 11:15:48 -0800 | [diff] [blame] | 2707 | case ql_log_info: |
Joe Perches | 086b3e8 | 2011-11-18 09:03:05 -0800 | [diff] [blame] | 2708 | pr_warn("%s%pV", pbuf, &vaf); |
| 2709 | break; |
| 2710 | default: |
| 2711 | pr_info("%s%pV", pbuf, &vaf); |
| 2712 | break; |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2713 | } |
| 2714 | |
Joe Perches | 086b3e8 | 2011-11-18 09:03:05 -0800 | [diff] [blame] | 2715 | va_end(va); |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2716 | } |
| 2717 | |
| 2718 | void |
| 2719 | ql_dump_regs(uint32_t level, scsi_qla_host_t *vha, int32_t id) |
| 2720 | { |
| 2721 | int i; |
| 2722 | struct qla_hw_data *ha = vha->hw; |
| 2723 | struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; |
| 2724 | struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; |
| 2725 | struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82; |
| 2726 | uint16_t __iomem *mbx_reg; |
| 2727 | |
Chad Dupuis | cfb0919 | 2011-11-18 09:03:07 -0800 | [diff] [blame] | 2728 | if (!ql_mask_match(level)) |
| 2729 | return; |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2730 | |
Atul Deshmukh | 7ec0eff | 2013-08-27 01:37:28 -0400 | [diff] [blame] | 2731 | if (IS_P3P_TYPE(ha)) |
Chad Dupuis | cfb0919 | 2011-11-18 09:03:07 -0800 | [diff] [blame] | 2732 | mbx_reg = ®82->mailbox_in[0]; |
| 2733 | else if (IS_FWI2_CAPABLE(ha)) |
| 2734 | mbx_reg = ®24->mailbox0; |
| 2735 | else |
| 2736 | mbx_reg = MAILBOX_REG(ha, reg, 0); |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2737 | |
Chad Dupuis | cfb0919 | 2011-11-18 09:03:07 -0800 | [diff] [blame] | 2738 | ql_dbg(level, vha, id, "Mailbox registers:\n"); |
Joe Carnuccio | 343f7de | 2017-08-23 15:05:15 -0700 | [diff] [blame] | 2739 | for (i = 0; i < 6; i++, mbx_reg++) |
Chad Dupuis | cfb0919 | 2011-11-18 09:03:07 -0800 | [diff] [blame] | 2740 | ql_dbg(level, vha, id, |
Joe Carnuccio | 343f7de | 2017-08-23 15:05:15 -0700 | [diff] [blame] | 2741 | "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg)); |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2742 | } |
| 2743 | |
| 2744 | |
| 2745 | void |
| 2746 | ql_dump_buffer(uint32_t level, scsi_qla_host_t *vha, int32_t id, |
Joe Carnuccio | a7ddd02 | 2016-07-06 11:14:22 -0400 | [diff] [blame] | 2747 | uint8_t *buf, uint size) |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2748 | { |
Joe Carnuccio | a7ddd02 | 2016-07-06 11:14:22 -0400 | [diff] [blame] | 2749 | uint cnt; |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2750 | |
Chad Dupuis | cfb0919 | 2011-11-18 09:03:07 -0800 | [diff] [blame] | 2751 | if (!ql_mask_match(level)) |
| 2752 | return; |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2753 | |
Joe Carnuccio | a7ddd02 | 2016-07-06 11:14:22 -0400 | [diff] [blame] | 2754 | ql_dbg(level, vha, id, |
| 2755 | "%-+5d 0 1 2 3 4 5 6 7 8 9 A B C D E F\n", size); |
| 2756 | ql_dbg(level, vha, id, |
| 2757 | "----- -----------------------------------------------\n"); |
Joe Perches | 2345656 | 2017-03-02 17:14:47 -0800 | [diff] [blame] | 2758 | for (cnt = 0; cnt < size; cnt += 16) { |
| 2759 | ql_dbg(level, vha, id, "%04x: ", cnt); |
| 2760 | print_hex_dump(KERN_CONT, "", DUMP_PREFIX_NONE, 16, 1, |
| 2761 | buf + cnt, min(16U, size - cnt), false); |
Saurav Kashyap | 3ce8866 | 2011-07-14 12:00:12 -0700 | [diff] [blame] | 2762 | } |
| 2763 | } |
Quinn Tran | 22d8472 | 2017-06-13 20:47:25 -0700 | [diff] [blame] | 2764 | |
| 2765 | /* |
| 2766 | * This function is for formatting and logging log messages. |
| 2767 | * It is to be used when vha is available. It formats the message |
| 2768 | * and logs it to the messages file. All the messages will be logged |
| 2769 | * irrespective of value of ql2xextended_error_logging. |
| 2770 | * parameters: |
| 2771 | * level: The level of the log messages to be printed in the |
| 2772 | * messages file. |
| 2773 | * vha: Pointer to the scsi_qla_host_t |
| 2774 | * id: This is a unique id for the level. It identifies the |
| 2775 | * part of the code from where the message originated. |
| 2776 | * msg: The message to be displayed. |
| 2777 | */ |
| 2778 | void |
| 2779 | ql_log_qp(uint32_t level, struct qla_qpair *qpair, int32_t id, |
| 2780 | const char *fmt, ...) |
| 2781 | { |
| 2782 | va_list va; |
| 2783 | struct va_format vaf; |
| 2784 | char pbuf[128]; |
| 2785 | |
| 2786 | if (level > ql_errlev) |
| 2787 | return; |
| 2788 | |
| 2789 | if (qpair != NULL) { |
| 2790 | const struct pci_dev *pdev = qpair->pdev; |
| 2791 | /* <module-name> <msg-id>:<host> Message */ |
| 2792 | snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: ", |
| 2793 | QL_MSGHDR, dev_name(&(pdev->dev)), id); |
| 2794 | } else { |
| 2795 | snprintf(pbuf, sizeof(pbuf), "%s [%s]-%04x: : ", |
| 2796 | QL_MSGHDR, "0000:00:00.0", id); |
| 2797 | } |
| 2798 | pbuf[sizeof(pbuf) - 1] = 0; |
| 2799 | |
| 2800 | va_start(va, fmt); |
| 2801 | |
| 2802 | vaf.fmt = fmt; |
| 2803 | vaf.va = &va; |
| 2804 | |
| 2805 | switch (level) { |
| 2806 | case ql_log_fatal: /* FATAL LOG */ |
| 2807 | pr_crit("%s%pV", pbuf, &vaf); |
| 2808 | break; |
| 2809 | case ql_log_warn: |
| 2810 | pr_err("%s%pV", pbuf, &vaf); |
| 2811 | break; |
| 2812 | case ql_log_info: |
| 2813 | pr_warn("%s%pV", pbuf, &vaf); |
| 2814 | break; |
| 2815 | default: |
| 2816 | pr_info("%s%pV", pbuf, &vaf); |
| 2817 | break; |
| 2818 | } |
| 2819 | |
| 2820 | va_end(va); |
| 2821 | } |
| 2822 | |
| 2823 | /* |
| 2824 | * This function is for formatting and logging debug information. |
| 2825 | * It is to be used when vha is available. It formats the message |
| 2826 | * and logs it to the messages file. |
| 2827 | * parameters: |
| 2828 | * level: The level of the debug messages to be printed. |
| 2829 | * If ql2xextended_error_logging value is correctly set, |
| 2830 | * this message will appear in the messages file. |
| 2831 | * vha: Pointer to the scsi_qla_host_t. |
| 2832 | * id: This is a unique identifier for the level. It identifies the |
| 2833 | * part of the code from where the message originated. |
| 2834 | * msg: The message to be displayed. |
| 2835 | */ |
| 2836 | void |
| 2837 | ql_dbg_qp(uint32_t level, struct qla_qpair *qpair, int32_t id, |
| 2838 | const char *fmt, ...) |
| 2839 | { |
| 2840 | va_list va; |
| 2841 | struct va_format vaf; |
| 2842 | |
| 2843 | if (!ql_mask_match(level)) |
| 2844 | return; |
| 2845 | |
| 2846 | va_start(va, fmt); |
| 2847 | |
| 2848 | vaf.fmt = fmt; |
| 2849 | vaf.va = &va; |
| 2850 | |
| 2851 | if (qpair != NULL) { |
| 2852 | const struct pci_dev *pdev = qpair->pdev; |
| 2853 | /* <module-name> <pci-name> <msg-id>:<host> Message */ |
| 2854 | pr_warn("%s [%s]-%04x: %pV", |
| 2855 | QL_MSGHDR, dev_name(&(pdev->dev)), id + ql_dbg_offset, |
| 2856 | &vaf); |
| 2857 | } else { |
| 2858 | pr_warn("%s [%s]-%04x: : %pV", |
| 2859 | QL_MSGHDR, "0000:00:00.0", id + ql_dbg_offset, &vaf); |
| 2860 | } |
| 2861 | |
| 2862 | va_end(va); |
| 2863 | |
| 2864 | } |