Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/kernel/head.S |
| 3 | * |
| 4 | * Copyright (C) 1994-2002 Russell King |
Russell King | e65f38e | 2005-06-18 09:33:31 +0100 | [diff] [blame] | 5 | * Copyright (c) 2003 ARM Limited |
| 6 | * All Rights Reserved |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | * |
| 12 | * Kernel startup code for all 32-bit CPUs |
| 13 | */ |
| 14 | #include <linux/config.h> |
| 15 | #include <linux/linkage.h> |
| 16 | #include <linux/init.h> |
| 17 | |
| 18 | #include <asm/assembler.h> |
| 19 | #include <asm/domain.h> |
| 20 | #include <asm/mach-types.h> |
| 21 | #include <asm/procinfo.h> |
| 22 | #include <asm/ptrace.h> |
Sam Ravnborg | e6ae744 | 2005-09-09 21:08:59 +0200 | [diff] [blame^] | 23 | #include <asm/asm-offsets.h> |
Russell King | 4f7a181 | 2005-05-05 13:11:00 +0100 | [diff] [blame] | 24 | #include <asm/thread_info.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 25 | #include <asm/system.h> |
| 26 | |
| 27 | #define PROCINFO_MMUFLAGS 8 |
| 28 | #define PROCINFO_INITFUNC 12 |
| 29 | |
| 30 | #define MACHINFO_TYPE 0 |
| 31 | #define MACHINFO_PHYSRAM 4 |
| 32 | #define MACHINFO_PHYSIO 8 |
| 33 | #define MACHINFO_PGOFFIO 12 |
| 34 | #define MACHINFO_NAME 16 |
| 35 | |
| 36 | #ifndef CONFIG_XIP_KERNEL |
| 37 | /* |
| 38 | * We place the page tables 16K below TEXTADDR. Therefore, we must make sure |
| 39 | * that TEXTADDR is correctly set. Currently, we expect the least significant |
| 40 | * 16 bits to be 0x8000, but we could probably relax this restriction to |
| 41 | * TEXTADDR >= PAGE_OFFSET + 0x4000 |
| 42 | * |
| 43 | * Note that swapper_pg_dir is the virtual address of the page tables, and |
| 44 | * pgtbl gives us a position-independent reference to these tables. We can |
| 45 | * do this because stext == TEXTADDR |
| 46 | */ |
| 47 | #if (TEXTADDR & 0xffff) != 0x8000 |
| 48 | #error TEXTADDR must start at 0xXXXX8000 |
| 49 | #endif |
| 50 | |
| 51 | .globl swapper_pg_dir |
| 52 | .equ swapper_pg_dir, TEXTADDR - 0x4000 |
| 53 | |
| 54 | .macro pgtbl, rd, phys |
| 55 | adr \rd, stext |
| 56 | sub \rd, \rd, #0x4000 |
| 57 | .endm |
| 58 | #else |
| 59 | /* |
| 60 | * XIP Kernel: |
| 61 | * |
| 62 | * We place the page tables 16K below DATAADDR. Therefore, we must make sure |
| 63 | * that DATAADDR is correctly set. Currently, we expect the least significant |
| 64 | * 16 bits to be 0x8000, but we could probably relax this restriction to |
| 65 | * DATAADDR >= PAGE_OFFSET + 0x4000 |
| 66 | * |
| 67 | * Note that pgtbl is meant to return the physical address of swapper_pg_dir. |
| 68 | * We can't make it relative to the kernel position in this case since |
| 69 | * the kernel can physically be anywhere. |
| 70 | */ |
| 71 | #if (DATAADDR & 0xffff) != 0x8000 |
| 72 | #error DATAADDR must start at 0xXXXX8000 |
| 73 | #endif |
| 74 | |
| 75 | .globl swapper_pg_dir |
| 76 | .equ swapper_pg_dir, DATAADDR - 0x4000 |
| 77 | |
| 78 | .macro pgtbl, rd, phys |
| 79 | ldr \rd, =((DATAADDR - 0x4000) - VIRT_OFFSET) |
| 80 | add \rd, \rd, \phys |
| 81 | .endm |
| 82 | #endif |
| 83 | |
| 84 | /* |
| 85 | * Kernel startup entry point. |
| 86 | * --------------------------- |
| 87 | * |
| 88 | * This is normally called from the decompressor code. The requirements |
| 89 | * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0, |
| 90 | * r1 = machine nr. |
| 91 | * |
| 92 | * This code is mostly position independent, so if you link the kernel at |
| 93 | * 0xc0008000, you call this at __pa(0xc0008000). |
| 94 | * |
| 95 | * See linux/arch/arm/tools/mach-types for the complete list of machine |
| 96 | * numbers for r1. |
| 97 | * |
| 98 | * We're trying to keep crap to a minimum; DO NOT add any machine specific |
| 99 | * crap here - that's what the boot loader (or in extreme, well justified |
| 100 | * circumstances, zImage) is for. |
| 101 | */ |
| 102 | __INIT |
| 103 | .type stext, %function |
| 104 | ENTRY(stext) |
| 105 | msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC @ ensure svc mode |
| 106 | @ and irqs disabled |
| 107 | bl __lookup_processor_type @ r5=procinfo r9=cpuid |
| 108 | movs r10, r5 @ invalid processor (r5=0)? |
| 109 | beq __error_p @ yes, error 'p' |
| 110 | bl __lookup_machine_type @ r5=machinfo |
| 111 | movs r8, r5 @ invalid machine (r5=0)? |
| 112 | beq __error_a @ yes, error 'a' |
| 113 | bl __create_page_tables |
| 114 | |
| 115 | /* |
| 116 | * The following calls CPU specific code in a position independent |
| 117 | * manner. See arch/arm/mm/proc-*.S for details. r10 = base of |
| 118 | * xxx_proc_info structure selected by __lookup_machine_type |
| 119 | * above. On return, the CPU will be ready for the MMU to be |
| 120 | * turned on, and r0 will hold the CPU control register value. |
| 121 | */ |
| 122 | ldr r13, __switch_data @ address to jump to after |
| 123 | @ mmu has been enabled |
| 124 | adr lr, __enable_mmu @ return (PIC) address |
| 125 | add pc, r10, #PROCINFO_INITFUNC |
| 126 | |
| 127 | .type __switch_data, %object |
| 128 | __switch_data: |
| 129 | .long __mmap_switched |
| 130 | .long __data_loc @ r4 |
| 131 | .long __data_start @ r5 |
| 132 | .long __bss_start @ r6 |
| 133 | .long _end @ r7 |
| 134 | .long processor_id @ r4 |
| 135 | .long __machine_arch_type @ r5 |
| 136 | .long cr_alignment @ r6 |
Russell King | 4f7a181 | 2005-05-05 13:11:00 +0100 | [diff] [blame] | 137 | .long init_thread_union + THREAD_START_SP @ sp |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 138 | |
| 139 | /* |
| 140 | * The following fragment of code is executed with the MMU on, and uses |
| 141 | * absolute addresses; this is not position independent. |
| 142 | * |
| 143 | * r0 = cp#15 control register |
| 144 | * r1 = machine ID |
| 145 | * r9 = processor ID |
| 146 | */ |
| 147 | .type __mmap_switched, %function |
| 148 | __mmap_switched: |
| 149 | adr r3, __switch_data + 4 |
| 150 | |
| 151 | ldmia r3!, {r4, r5, r6, r7} |
| 152 | cmp r4, r5 @ Copy data segment if needed |
| 153 | 1: cmpne r5, r6 |
| 154 | ldrne fp, [r4], #4 |
| 155 | strne fp, [r5], #4 |
| 156 | bne 1b |
| 157 | |
| 158 | mov fp, #0 @ Clear BSS (and zero fp) |
| 159 | 1: cmp r6, r7 |
| 160 | strcc fp, [r6],#4 |
| 161 | bcc 1b |
| 162 | |
| 163 | ldmia r3, {r4, r5, r6, sp} |
| 164 | str r9, [r4] @ Save processor ID |
| 165 | str r1, [r5] @ Save machine type |
| 166 | bic r4, r0, #CR_A @ Clear 'A' bit |
| 167 | stmia r6, {r0, r4} @ Save control register values |
| 168 | b start_kernel |
| 169 | |
Russell King | e65f38e | 2005-06-18 09:33:31 +0100 | [diff] [blame] | 170 | #if defined(CONFIG_SMP) |
| 171 | .type secondary_startup, #function |
| 172 | ENTRY(secondary_startup) |
| 173 | /* |
| 174 | * Common entry point for secondary CPUs. |
| 175 | * |
| 176 | * Ensure that we're in SVC mode, and IRQs are disabled. Lookup |
| 177 | * the processor type - there is no need to check the machine type |
| 178 | * as it has already been validated by the primary processor. |
| 179 | */ |
| 180 | msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC |
| 181 | bl __lookup_processor_type |
| 182 | movs r10, r5 @ invalid processor? |
| 183 | moveq r0, #'p' @ yes, error 'p' |
| 184 | beq __error |
| 185 | |
| 186 | /* |
| 187 | * Use the page tables supplied from __cpu_up. |
| 188 | */ |
| 189 | adr r4, __secondary_data |
| 190 | ldmia r4, {r5, r6, r13} @ address to jump to after |
| 191 | sub r4, r4, r5 @ mmu has been enabled |
| 192 | ldr r4, [r6, r4] @ get secondary_data.pgdir |
| 193 | adr lr, __enable_mmu @ return address |
| 194 | add pc, r10, #12 @ initialise processor |
| 195 | @ (return control reg) |
| 196 | |
| 197 | /* |
| 198 | * r6 = &secondary_data |
| 199 | */ |
| 200 | ENTRY(__secondary_switched) |
| 201 | ldr sp, [r6, #4] @ get secondary_data.stack |
| 202 | mov fp, #0 |
| 203 | b secondary_start_kernel |
| 204 | |
| 205 | .type __secondary_data, %object |
| 206 | __secondary_data: |
| 207 | .long . |
| 208 | .long secondary_data |
| 209 | .long __secondary_switched |
| 210 | #endif /* defined(CONFIG_SMP) */ |
| 211 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 212 | |
| 213 | |
| 214 | /* |
| 215 | * Setup common bits before finally enabling the MMU. Essentially |
| 216 | * this is just loading the page table pointer and domain access |
| 217 | * registers. |
| 218 | */ |
| 219 | .type __enable_mmu, %function |
| 220 | __enable_mmu: |
| 221 | #ifdef CONFIG_ALIGNMENT_TRAP |
| 222 | orr r0, r0, #CR_A |
| 223 | #else |
| 224 | bic r0, r0, #CR_A |
| 225 | #endif |
| 226 | #ifdef CONFIG_CPU_DCACHE_DISABLE |
| 227 | bic r0, r0, #CR_C |
| 228 | #endif |
| 229 | #ifdef CONFIG_CPU_BPREDICT_DISABLE |
| 230 | bic r0, r0, #CR_Z |
| 231 | #endif |
| 232 | #ifdef CONFIG_CPU_ICACHE_DISABLE |
| 233 | bic r0, r0, #CR_I |
| 234 | #endif |
| 235 | mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \ |
| 236 | domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \ |
| 237 | domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \ |
| 238 | domain_val(DOMAIN_IO, DOMAIN_CLIENT)) |
| 239 | mcr p15, 0, r5, c3, c0, 0 @ load domain access register |
| 240 | mcr p15, 0, r4, c2, c0, 0 @ load page table pointer |
| 241 | b __turn_mmu_on |
| 242 | |
| 243 | /* |
| 244 | * Enable the MMU. This completely changes the structure of the visible |
| 245 | * memory space. You will not be able to trace execution through this. |
| 246 | * If you have an enquiry about this, *please* check the linux-arm-kernel |
| 247 | * mailing list archives BEFORE sending another post to the list. |
| 248 | * |
| 249 | * r0 = cp#15 control register |
| 250 | * r13 = *virtual* address to jump to upon completion |
| 251 | * |
| 252 | * other registers depend on the function called upon completion |
| 253 | */ |
| 254 | .align 5 |
| 255 | .type __turn_mmu_on, %function |
| 256 | __turn_mmu_on: |
| 257 | mov r0, r0 |
| 258 | mcr p15, 0, r0, c1, c0, 0 @ write control reg |
| 259 | mrc p15, 0, r3, c0, c0, 0 @ read id reg |
| 260 | mov r3, r3 |
| 261 | mov r3, r3 |
| 262 | mov pc, r13 |
| 263 | |
| 264 | |
| 265 | |
| 266 | /* |
| 267 | * Setup the initial page tables. We only setup the barest |
| 268 | * amount which are required to get the kernel running, which |
| 269 | * generally means mapping in the kernel code. |
| 270 | * |
| 271 | * r8 = machinfo |
| 272 | * r9 = cpuid |
| 273 | * r10 = procinfo |
| 274 | * |
| 275 | * Returns: |
| 276 | * r0, r3, r5, r6, r7 corrupted |
| 277 | * r4 = physical page table address |
| 278 | */ |
| 279 | .type __create_page_tables, %function |
| 280 | __create_page_tables: |
| 281 | ldr r5, [r8, #MACHINFO_PHYSRAM] @ physram |
| 282 | pgtbl r4, r5 @ page table address |
| 283 | |
| 284 | /* |
| 285 | * Clear the 16K level 1 swapper page table |
| 286 | */ |
| 287 | mov r0, r4 |
| 288 | mov r3, #0 |
| 289 | add r6, r0, #0x4000 |
| 290 | 1: str r3, [r0], #4 |
| 291 | str r3, [r0], #4 |
| 292 | str r3, [r0], #4 |
| 293 | str r3, [r0], #4 |
| 294 | teq r0, r6 |
| 295 | bne 1b |
| 296 | |
| 297 | ldr r7, [r10, #PROCINFO_MMUFLAGS] @ mmuflags |
| 298 | |
| 299 | /* |
| 300 | * Create identity mapping for first MB of kernel to |
| 301 | * cater for the MMU enable. This identity mapping |
| 302 | * will be removed by paging_init(). We use our current program |
| 303 | * counter to determine corresponding section base address. |
| 304 | */ |
| 305 | mov r6, pc, lsr #20 @ start of kernel section |
| 306 | orr r3, r7, r6, lsl #20 @ flags + kernel base |
| 307 | str r3, [r4, r6, lsl #2] @ identity mapping |
| 308 | |
| 309 | /* |
| 310 | * Now setup the pagetables for our kernel direct |
| 311 | * mapped region. We round TEXTADDR down to the |
| 312 | * nearest megabyte boundary. It is assumed that |
| 313 | * the kernel fits within 4 contigous 1MB sections. |
| 314 | */ |
| 315 | add r0, r4, #(TEXTADDR & 0xff000000) >> 18 @ start of kernel |
| 316 | str r3, [r0, #(TEXTADDR & 0x00f00000) >> 18]! |
| 317 | add r3, r3, #1 << 20 |
| 318 | str r3, [r0, #4]! @ KERNEL + 1MB |
| 319 | add r3, r3, #1 << 20 |
| 320 | str r3, [r0, #4]! @ KERNEL + 2MB |
| 321 | add r3, r3, #1 << 20 |
| 322 | str r3, [r0, #4] @ KERNEL + 3MB |
| 323 | |
| 324 | /* |
| 325 | * Then map first 1MB of ram in case it contains our boot params. |
| 326 | */ |
| 327 | add r0, r4, #VIRT_OFFSET >> 18 |
| 328 | orr r6, r5, r7 |
| 329 | str r6, [r0] |
| 330 | |
| 331 | #ifdef CONFIG_XIP_KERNEL |
| 332 | /* |
| 333 | * Map some ram to cover our .data and .bss areas. |
| 334 | * Mapping 3MB should be plenty. |
| 335 | */ |
| 336 | sub r3, r4, r5 |
| 337 | mov r3, r3, lsr #20 |
| 338 | add r0, r0, r3, lsl #2 |
| 339 | add r6, r6, r3, lsl #20 |
| 340 | str r6, [r0], #4 |
| 341 | add r6, r6, #(1 << 20) |
| 342 | str r6, [r0], #4 |
| 343 | add r6, r6, #(1 << 20) |
| 344 | str r6, [r0] |
| 345 | #endif |
| 346 | |
Russell King | c77b042 | 2005-07-01 11:56:55 +0100 | [diff] [blame] | 347 | #ifdef CONFIG_DEBUG_LL |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 348 | bic r7, r7, #0x0c @ turn off cacheable |
| 349 | @ and bufferable bits |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 350 | /* |
| 351 | * Map in IO space for serial debugging. |
| 352 | * This allows debug messages to be output |
| 353 | * via a serial console before paging_init. |
| 354 | */ |
| 355 | ldr r3, [r8, #MACHINFO_PGOFFIO] |
| 356 | add r0, r4, r3 |
| 357 | rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long) |
| 358 | cmp r3, #0x0800 @ limit to 512MB |
| 359 | movhi r3, #0x0800 |
| 360 | add r6, r0, r3 |
| 361 | ldr r3, [r8, #MACHINFO_PHYSIO] |
| 362 | orr r3, r3, r7 |
| 363 | 1: str r3, [r0], #4 |
| 364 | add r3, r3, #1 << 20 |
| 365 | teq r0, r6 |
| 366 | bne 1b |
| 367 | #if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS) |
| 368 | /* |
| 369 | * If we're using the NetWinder, we need to map in |
| 370 | * the 16550-type serial port for the debug messages |
| 371 | */ |
| 372 | teq r1, #MACH_TYPE_NETWINDER |
| 373 | teqne r1, #MACH_TYPE_CATS |
| 374 | bne 1f |
Russell King | c77b042 | 2005-07-01 11:56:55 +0100 | [diff] [blame] | 375 | add r0, r4, #0xff000000 >> 18 |
| 376 | orr r3, r7, #0x7c000000 |
| 377 | str r3, [r0] |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 378 | 1: |
| 379 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 380 | #ifdef CONFIG_ARCH_RPC |
| 381 | /* |
| 382 | * Map in screen at 0x02000000 & SCREEN2_BASE |
| 383 | * Similar reasons here - for debug. This is |
| 384 | * only for Acorn RiscPC architectures. |
| 385 | */ |
Russell King | c77b042 | 2005-07-01 11:56:55 +0100 | [diff] [blame] | 386 | add r0, r4, #0x02000000 >> 18 |
| 387 | orr r3, r7, #0x02000000 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 388 | str r3, [r0] |
Russell King | c77b042 | 2005-07-01 11:56:55 +0100 | [diff] [blame] | 389 | add r0, r4, #0xd8000000 >> 18 |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 390 | str r3, [r0] |
| 391 | #endif |
Russell King | c77b042 | 2005-07-01 11:56:55 +0100 | [diff] [blame] | 392 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 393 | mov pc, lr |
| 394 | .ltorg |
| 395 | |
| 396 | |
| 397 | |
| 398 | /* |
| 399 | * Exception handling. Something went wrong and we can't proceed. We |
| 400 | * ought to tell the user, but since we don't have any guarantee that |
| 401 | * we're even running on the right architecture, we do virtually nothing. |
| 402 | * |
| 403 | * If CONFIG_DEBUG_LL is set we try to print out something about the error |
| 404 | * and hope for the best (useful if bootloader fails to pass a proper |
| 405 | * machine ID for example). |
| 406 | */ |
| 407 | |
| 408 | .type __error_p, %function |
| 409 | __error_p: |
| 410 | #ifdef CONFIG_DEBUG_LL |
| 411 | adr r0, str_p1 |
| 412 | bl printascii |
| 413 | b __error |
| 414 | str_p1: .asciz "\nError: unrecognized/unsupported processor variant.\n" |
| 415 | .align |
| 416 | #endif |
| 417 | |
| 418 | .type __error_a, %function |
| 419 | __error_a: |
| 420 | #ifdef CONFIG_DEBUG_LL |
| 421 | mov r4, r1 @ preserve machine ID |
| 422 | adr r0, str_a1 |
| 423 | bl printascii |
| 424 | mov r0, r4 |
| 425 | bl printhex8 |
| 426 | adr r0, str_a2 |
| 427 | bl printascii |
| 428 | adr r3, 3f |
| 429 | ldmia r3, {r4, r5, r6} @ get machine desc list |
| 430 | sub r4, r3, r4 @ get offset between virt&phys |
| 431 | add r5, r5, r4 @ convert virt addresses to |
| 432 | add r6, r6, r4 @ physical address space |
| 433 | 1: ldr r0, [r5, #MACHINFO_TYPE] @ get machine type |
| 434 | bl printhex8 |
| 435 | mov r0, #'\t' |
| 436 | bl printch |
| 437 | ldr r0, [r5, #MACHINFO_NAME] @ get machine name |
| 438 | add r0, r0, r4 |
| 439 | bl printascii |
| 440 | mov r0, #'\n' |
| 441 | bl printch |
| 442 | add r5, r5, #SIZEOF_MACHINE_DESC @ next machine_desc |
| 443 | cmp r5, r6 |
| 444 | blo 1b |
| 445 | adr r0, str_a3 |
| 446 | bl printascii |
| 447 | b __error |
| 448 | str_a1: .asciz "\nError: unrecognized/unsupported machine ID (r1 = 0x" |
| 449 | str_a2: .asciz ").\n\nAvailable machine support:\n\nID (hex)\tNAME\n" |
| 450 | str_a3: .asciz "\nPlease check your kernel config and/or bootloader.\n" |
| 451 | .align |
| 452 | #endif |
| 453 | |
| 454 | .type __error, %function |
| 455 | __error: |
| 456 | #ifdef CONFIG_ARCH_RPC |
| 457 | /* |
| 458 | * Turn the screen red on a error - RiscPC only. |
| 459 | */ |
| 460 | mov r0, #0x02000000 |
| 461 | mov r3, #0x11 |
| 462 | orr r3, r3, r3, lsl #8 |
| 463 | orr r3, r3, r3, lsl #16 |
| 464 | str r3, [r0], #4 |
| 465 | str r3, [r0], #4 |
| 466 | str r3, [r0], #4 |
| 467 | str r3, [r0], #4 |
| 468 | #endif |
| 469 | 1: mov r0, r0 |
| 470 | b 1b |
| 471 | |
| 472 | |
| 473 | /* |
| 474 | * Read processor ID register (CP#15, CR0), and look up in the linker-built |
| 475 | * supported processor list. Note that we can't use the absolute addresses |
| 476 | * for the __proc_info lists since we aren't running with the MMU on |
| 477 | * (and therefore, we are not in the correct address space). We have to |
| 478 | * calculate the offset. |
| 479 | * |
| 480 | * Returns: |
| 481 | * r3, r4, r6 corrupted |
| 482 | * r5 = proc_info pointer in physical address space |
| 483 | * r9 = cpuid |
| 484 | */ |
| 485 | .type __lookup_processor_type, %function |
| 486 | __lookup_processor_type: |
| 487 | adr r3, 3f |
| 488 | ldmda r3, {r5, r6, r9} |
| 489 | sub r3, r3, r9 @ get offset between virt&phys |
| 490 | add r5, r5, r3 @ convert virt addresses to |
| 491 | add r6, r6, r3 @ physical address space |
| 492 | mrc p15, 0, r9, c0, c0 @ get processor id |
| 493 | 1: ldmia r5, {r3, r4} @ value, mask |
| 494 | and r4, r4, r9 @ mask wanted bits |
| 495 | teq r3, r4 |
| 496 | beq 2f |
| 497 | add r5, r5, #PROC_INFO_SZ @ sizeof(proc_info_list) |
| 498 | cmp r5, r6 |
| 499 | blo 1b |
| 500 | mov r5, #0 @ unknown processor |
| 501 | 2: mov pc, lr |
| 502 | |
| 503 | /* |
| 504 | * This provides a C-API version of the above function. |
| 505 | */ |
| 506 | ENTRY(lookup_processor_type) |
| 507 | stmfd sp!, {r4 - r6, r9, lr} |
| 508 | bl __lookup_processor_type |
| 509 | mov r0, r5 |
| 510 | ldmfd sp!, {r4 - r6, r9, pc} |
| 511 | |
| 512 | /* |
| 513 | * Look in include/asm-arm/procinfo.h and arch/arm/kernel/arch.[ch] for |
| 514 | * more information about the __proc_info and __arch_info structures. |
| 515 | */ |
| 516 | .long __proc_info_begin |
| 517 | .long __proc_info_end |
| 518 | 3: .long . |
| 519 | .long __arch_info_begin |
| 520 | .long __arch_info_end |
| 521 | |
| 522 | /* |
| 523 | * Lookup machine architecture in the linker-build list of architectures. |
| 524 | * Note that we can't use the absolute addresses for the __arch_info |
| 525 | * lists since we aren't running with the MMU on (and therefore, we are |
| 526 | * not in the correct address space). We have to calculate the offset. |
| 527 | * |
| 528 | * r1 = machine architecture number |
| 529 | * Returns: |
| 530 | * r3, r4, r6 corrupted |
| 531 | * r5 = mach_info pointer in physical address space |
| 532 | */ |
| 533 | .type __lookup_machine_type, %function |
| 534 | __lookup_machine_type: |
| 535 | adr r3, 3b |
| 536 | ldmia r3, {r4, r5, r6} |
| 537 | sub r3, r3, r4 @ get offset between virt&phys |
| 538 | add r5, r5, r3 @ convert virt addresses to |
| 539 | add r6, r6, r3 @ physical address space |
| 540 | 1: ldr r3, [r5, #MACHINFO_TYPE] @ get machine type |
| 541 | teq r3, r1 @ matches loader number? |
| 542 | beq 2f @ found |
| 543 | add r5, r5, #SIZEOF_MACHINE_DESC @ next machine_desc |
| 544 | cmp r5, r6 |
| 545 | blo 1b |
| 546 | mov r5, #0 @ unknown machine |
| 547 | 2: mov pc, lr |
| 548 | |
| 549 | /* |
| 550 | * This provides a C-API version of the above function. |
| 551 | */ |
| 552 | ENTRY(lookup_machine_type) |
| 553 | stmfd sp!, {r4 - r6, lr} |
| 554 | mov r1, r0 |
| 555 | bl __lookup_machine_type |
| 556 | mov r0, r5 |
| 557 | ldmfd sp!, {r4 - r6, pc} |