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Roy Huang088eec12007-06-21 11:34:16 +08001/*
Mike Frysingeraf5d7fc2009-11-15 18:18:41 -05002 * DO NOT EDIT THIS FILE
3 * This file is under version control at
4 * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
5 * and can be replaced with that version at any time
6 * DO NOT EDIT THIS FILE
Roy Huang088eec12007-06-21 11:34:16 +08007 *
Mike Frysinger93f17422011-05-06 02:26:38 -04008 * Copyright 2004-2011 Analog Devices Inc.
Sonic Zhangde450832012-05-17 14:45:27 +08009 * Licensed under the Clear BSD license.
Roy Huang088eec12007-06-21 11:34:16 +080010 */
11
Mike Frysingera4136472009-05-08 07:40:25 +000012/* This file should be up to date with:
Mike Frysinger979365b2011-06-08 18:15:18 -040013 * - Revision K, 05/23/2011; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
Mike Frysinger1aafd902007-07-25 11:19:14 +080014 */
15
Roy Huang088eec12007-06-21 11:34:16 +080016#ifndef _MACH_ANOMALY_H_
17#define _MACH_ANOMALY_H_
Mike Frysinger287050f2007-07-24 15:23:20 +080018
Mike Frysingera4136472009-05-08 07:40:25 +000019/* We do not support 0.0 or 0.1 silicon - sorry */
20#if __SILICON_REVISION__ < 2
21# error will not work on BF548 silicon version 0.0, or 0.1
22#endif
23
Mike Frysingera200ad22009-06-13 06:37:14 -040024/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
Mike Frysinger1aafd902007-07-25 11:19:14 +080025#define ANOMALY_05000074 (1)
26/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
27#define ANOMALY_05000119 (1)
28/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
29#define ANOMALY_05000122 (1)
Mike Frysingerdc7101b2010-05-27 21:47:31 +000030/* Data Corruption/Core Hang with L2/L3 Configured in Writeback Cache Mode */
Mike Frysinger979365b2011-06-08 18:15:18 -040031#define ANOMALY_05000220 (__SILICON_REVISION__ < 4)
Mike Frysingera4136472009-05-08 07:40:25 +000032/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
Mike Frysinger1aafd902007-07-25 11:19:14 +080033#define ANOMALY_05000245 (1)
Mike Frysinger1aafd902007-07-25 11:19:14 +080034/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
35#define ANOMALY_05000265 (1)
36/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
37#define ANOMALY_05000272 (1)
Mike Frysinger979365b2011-06-08 18:15:18 -040038/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
39#define ANOMALY_05000310 (1)
40/* FIFO Boot Mode Not Functional */
41#define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
42/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
43/*
44 * Note: anomaly sheet says this is fixed with bf54x-0.2+, but testing
45 * shows that the fix itself does not cover all cases.
46 */
47#define ANOMALY_05000353 (1)
48/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
49#define ANOMALY_05000357 (1)
50/* External Memory Read Access Hangs Core With PLL Bypass */
51#define ANOMALY_05000360 (1)
52/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
53#define ANOMALY_05000365 (1)
54/* Addressing Conflict between Boot ROM and Asynchronous Memory */
55#define ANOMALY_05000369 (1)
56/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
57#define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
58/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
59#define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
60/* 16-Bit NAND FLASH Boot Mode Is Not Functional */
61#define ANOMALY_05000379 (1)
62/* Lockbox SESR Disallows Certain User Interrupts */
63#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
64/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
65#define ANOMALY_05000405 (1)
66/* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */
67#define ANOMALY_05000406 (__SILICON_REVISION__ < 2)
68/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
69#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
70/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
71#define ANOMALY_05000408 (1)
72/* Lockbox firmware leaves MDMA0 channel enabled */
73#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
74/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
75#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
76/* NAND Boot Mode Not Compatible With Some NAND Flash Devices */
77#define ANOMALY_05000413 (__SILICON_REVISION__ < 2)
78/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
79#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
80/* Speculative Fetches Can Cause Undesired External FIFO Operations */
81#define ANOMALY_05000416 (1)
82/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
83#define ANOMALY_05000425 (__SILICON_REVISION__ < 4)
84/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
85#define ANOMALY_05000426 (1)
86/* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
87#define ANOMALY_05000427 (__SILICON_REVISION__ < 2)
88/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
89#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
90/* Software System Reset Corrupts PLL_LOCKCNT Register */
91#define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
92/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
93#define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
94/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
95#define ANOMALY_05000434 (1)
96/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
97#define ANOMALY_05000443 (1)
98/* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */
99#define ANOMALY_05000446 (1)
100/* UART IrDA Receiver Fails on Extended Bit Pulses */
101#define ANOMALY_05000447 (1)
102/* DDR Clock Duty Cycle Spec Violation (tCH, tCL) */
103#define ANOMALY_05000448 (__SILICON_REVISION__ == 1)
104/* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
105#define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
106/* USB DMA Short Packet Data Corruption */
107#define ANOMALY_05000450 (1)
108/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
109#define ANOMALY_05000456 (1)
110/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
111#define ANOMALY_05000457 (1)
112/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
113#define ANOMALY_05000460 (__SILICON_REVISION__ < 4)
114/* False Hardware Error when RETI Points to Invalid Memory */
115#define ANOMALY_05000461 (1)
116/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
117#define ANOMALY_05000462 (__SILICON_REVISION__ < 4)
118/* USB DMA RX Data Corruption */
119#define ANOMALY_05000463 (__SILICON_REVISION__ < 4)
120/* USB TX DMA Hang */
121#define ANOMALY_05000464 (__SILICON_REVISION__ < 4)
122/* USB Rx DMA Hang */
123#define ANOMALY_05000465 (1)
124/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
125#define ANOMALY_05000466 (__SILICON_REVISION__ < 4)
126/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
127#define ANOMALY_05000467 (__SILICON_REVISION__ < 4)
128/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
129#define ANOMALY_05000473 (1)
130/* Access to DDR SDRAM Causes System Hang with Certain PLL Settings */
131#define ANOMALY_05000474 (__SILICON_REVISION__ < 4)
132/* TESTSET Instruction Cannot Be Interrupted */
133#define ANOMALY_05000477 (1)
134/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
135#define ANOMALY_05000481 (1)
136/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
137#define ANOMALY_05000483 (1)
138/* DDR Trim May Not Be Performed for Certain VLEV Values in OTP Page PBS00L */
139#define ANOMALY_05000484 (__SILICON_REVISION__ < 3)
140/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
141#define ANOMALY_05000485 (__SILICON_REVISION__ > 1 && __SILICON_REVISION__ < 4)
142/* PLL May Latch Incorrect Values Coming Out of Reset */
143#define ANOMALY_05000489 (1)
144/* SPI Master Boot Can Fail Under Certain Conditions */
145#define ANOMALY_05000490 (1)
146/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
147#define ANOMALY_05000491 (1)
148/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
149#define ANOMALY_05000494 (1)
150/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
151#define ANOMALY_05000498 (1)
152/* Nand Flash Controller Hangs When the AMC Requests the Async Pins During the last 16 Bytes of a Page Write Operation. */
153#define ANOMALY_05000500 (1)
154/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
155#define ANOMALY_05000501 (1)
156/* Async Memory Writes May Be Skipped When Using Odd Clock Ratios */
157#define ANOMALY_05000502 (1)
158
159/*
160 * These anomalies have been "phased" out of analog.com anomaly sheets and are
161 * here to show running on older silicon just isn't feasible.
162 */
163
164/* False Hardware Error when ISR Context Is Not Restored */
Mike Frysinger7cc1c4b2007-12-24 20:05:09 +0800165#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
Mike Frysingerbc8c84c2007-08-05 17:32:25 +0800166/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
Mike Frysinger7cc1c4b2007-12-24 20:05:09 +0800167#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
Mike Frysingera200ad22009-06-13 06:37:14 -0400168/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
Mike Frysinger7cc1c4b2007-12-24 20:05:09 +0800169#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
Mike Frysinger1aafd902007-07-25 11:19:14 +0800170/* TWI Slave Boot Mode Is Not Functional */
Mike Frysinger7cc1c4b2007-12-24 20:05:09 +0800171#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
Mike Frysinger1aafd902007-07-25 11:19:14 +0800172/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
Mike Frysinger7cc1c4b2007-12-24 20:05:09 +0800173#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
Mike Frysinger1aafd902007-07-25 11:19:14 +0800174/* Incorrect Access of OTP_STATUS During otp_write() Function */
Mike Frysinger7cc1c4b2007-12-24 20:05:09 +0800175#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
Mike Frysinger1aafd902007-07-25 11:19:14 +0800176/* Synchronous Burst Flash Boot Mode Is Not Functional */
Mike Frysinger7cc1c4b2007-12-24 20:05:09 +0800177#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
Mike Frysinger4e8086d2008-10-10 21:07:55 +0800178/* Host DMA Boot Modes Are Not Functional */
Mike Frysinger7cc1c4b2007-12-24 20:05:09 +0800179#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
Mike Frysinger1aafd902007-07-25 11:19:14 +0800180/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
Mike Frysinger7cc1c4b2007-12-24 20:05:09 +0800181#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
Mike Frysinger1aafd902007-07-25 11:19:14 +0800182/* Inadequate Rotary Debounce Logic Duration */
Mike Frysinger7cc1c4b2007-12-24 20:05:09 +0800183#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
Mike Frysinger1aafd902007-07-25 11:19:14 +0800184/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
Mike Frysinger7cc1c4b2007-12-24 20:05:09 +0800185#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
Mike Frysinger1aafd902007-07-25 11:19:14 +0800186/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
Mike Frysinger7cc1c4b2007-12-24 20:05:09 +0800187#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
Mike Frysinger1aafd902007-07-25 11:19:14 +0800188/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
Mike Frysinger7cc1c4b2007-12-24 20:05:09 +0800189#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
Mike Frysingerbc8c84c2007-08-05 17:32:25 +0800190/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
Mike Frysinger7cc1c4b2007-12-24 20:05:09 +0800191#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
Mike Frysingerbc8c84c2007-08-05 17:32:25 +0800192/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
Mike Frysinger7cc1c4b2007-12-24 20:05:09 +0800193#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
Mike Frysingera4136472009-05-08 07:40:25 +0000194/* USB Calibration Value Is Not Initialized */
Mike Frysinger7cc1c4b2007-12-24 20:05:09 +0800195#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
Robin Getz202d7bd2008-10-09 11:59:46 +0800196/* USB Calibration Value to use */
197#define ANOMALY_05000346_value 0x5411
Mike Frysinger4e8086d2008-10-10 21:07:55 +0800198/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
Mike Frysinger7cc1c4b2007-12-24 20:05:09 +0800199#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
Mike Frysingerbc8c84c2007-08-05 17:32:25 +0800200/* Data Lost when Core Reads SDH Data FIFO */
Mike Frysinger7cc1c4b2007-12-24 20:05:09 +0800201#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
Mike Frysingerbc8c84c2007-08-05 17:32:25 +0800202/* PLL Status Register Is Inaccurate */
Mike Frysinger7cc1c4b2007-12-24 20:05:09 +0800203#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
Mike Frysinger4e8086d2008-10-10 21:07:55 +0800204/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
205#define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
206/* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
207#define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
Mike Frysinger4e8086d2008-10-10 21:07:55 +0800208/* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
209#define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
Mike Frysinger4e8086d2008-10-10 21:07:55 +0800210/* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
211#define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
Mike Frysinger4e8086d2008-10-10 21:07:55 +0800212/* USB DP/DM Data Pins May Lose State When Entering Hibernate */
213#define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
Mike Frysinger4e8086d2008-10-10 21:07:55 +0800214/* 8-Bit NAND Flash Boot Mode Not Functional */
215#define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
Mike Frysinger4e8086d2008-10-10 21:07:55 +0800216/* Boot from OTP Memory Not Functional */
217#define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
218/* bfrom_SysControl() Firmware Routine Not Functional */
219#define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
220/* Programmable Preboot Settings Not Functional */
221#define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
222/* CRC32 Checksum Support Not Functional */
223#define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
224/* Reset Vector Must Not Be in SDRAM Memory Space */
225#define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
226/* Changed Meaning of BCODE Field in SYSCR Register */
227#define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
228/* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
229#define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
230/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
231#define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
232/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
233#define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
234/* Log Buffer Not Functional */
235#define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
236/* Hook Routine Not Functional */
237#define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
238/* Header Indirect Bit Not Functional */
239#define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
240/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
241#define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
Mike Frysingerc18e99c2009-03-04 17:36:49 +0800242/* OTP Write Accesses Not Supported */
243#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
Yi Libd411b12009-08-05 10:02:14 +0000244/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
245#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
Roy Huang088eec12007-06-21 11:34:16 +0800246
Mike Frysinger1aafd902007-07-25 11:19:14 +0800247/* Anomalies that don't exist on this proc */
Mike Frysingera4136472009-05-08 07:40:25 +0000248#define ANOMALY_05000099 (0)
249#define ANOMALY_05000120 (0)
Mike Frysinger1aafd902007-07-25 11:19:14 +0800250#define ANOMALY_05000125 (0)
Mike Frysingera4136472009-05-08 07:40:25 +0000251#define ANOMALY_05000149 (0)
Bryan Wu2cbfe102007-08-05 15:31:16 +0800252#define ANOMALY_05000158 (0)
Mike Frysingera4136472009-05-08 07:40:25 +0000253#define ANOMALY_05000171 (0)
254#define ANOMALY_05000179 (0)
Mike Frysingera200ad22009-06-13 06:37:14 -0400255#define ANOMALY_05000182 (0)
Mike Frysinger1aafd902007-07-25 11:19:14 +0800256#define ANOMALY_05000183 (0)
Graf Yang976119b2009-07-01 07:05:40 +0000257#define ANOMALY_05000189 (0)
Mike Frysinger1aafd902007-07-25 11:19:14 +0800258#define ANOMALY_05000198 (0)
Mike Frysingera200ad22009-06-13 06:37:14 -0400259#define ANOMALY_05000202 (0)
Mike Frysingera4136472009-05-08 07:40:25 +0000260#define ANOMALY_05000215 (0)
Mike Frysingerdc7101b2010-05-27 21:47:31 +0000261#define ANOMALY_05000219 (0)
Mike Frysingera4136472009-05-08 07:40:25 +0000262#define ANOMALY_05000227 (0)
Mike Frysinger0174dd52007-08-05 16:53:10 +0800263#define ANOMALY_05000230 (0)
Mike Frysingera4136472009-05-08 07:40:25 +0000264#define ANOMALY_05000231 (0)
265#define ANOMALY_05000233 (0)
Mike Frysingera200ad22009-06-13 06:37:14 -0400266#define ANOMALY_05000234 (0)
Mike Frysingera4136472009-05-08 07:40:25 +0000267#define ANOMALY_05000242 (0)
Mike Frysinger1aafd902007-07-25 11:19:14 +0800268#define ANOMALY_05000244 (0)
Mike Frysingera4136472009-05-08 07:40:25 +0000269#define ANOMALY_05000248 (0)
270#define ANOMALY_05000250 (0)
271#define ANOMALY_05000254 (0)
Mike Frysingera200ad22009-06-13 06:37:14 -0400272#define ANOMALY_05000257 (0)
Mike Frysinger60e93562007-07-25 11:56:01 +0800273#define ANOMALY_05000261 (0)
Mike Frysinger1aafd902007-07-25 11:19:14 +0800274#define ANOMALY_05000263 (0)
275#define ANOMALY_05000266 (0)
276#define ANOMALY_05000273 (0)
Mike Frysingera4136472009-05-08 07:40:25 +0000277#define ANOMALY_05000274 (0)
Mike Frysingeree554be2009-03-03 16:52:55 +0800278#define ANOMALY_05000278 (0)
Mike Frysingera200ad22009-06-13 06:37:14 -0400279#define ANOMALY_05000283 (0)
Mike Frysingera4136472009-05-08 07:40:25 +0000280#define ANOMALY_05000287 (0)
281#define ANOMALY_05000301 (0)
Mike Frysingerc18e99c2009-03-04 17:36:49 +0800282#define ANOMALY_05000305 (0)
Mike Frysinger4e8086d2008-10-10 21:07:55 +0800283#define ANOMALY_05000307 (0)
Mike Frysinger1aafd902007-07-25 11:19:14 +0800284#define ANOMALY_05000311 (0)
Mike Frysingera200ad22009-06-13 06:37:14 -0400285#define ANOMALY_05000315 (0)
Michael Hennerich2b393312007-10-10 16:58:49 +0800286#define ANOMALY_05000323 (0)
Mike Frysingera4136472009-05-08 07:40:25 +0000287#define ANOMALY_05000362 (1)
Sonic Zhang4d555632008-04-25 03:28:10 +0800288#define ANOMALY_05000363 (0)
Graf Yang976119b2009-07-01 07:05:40 +0000289#define ANOMALY_05000364 (0)
Bryan Wu1c302b62009-02-04 16:49:45 +0800290#define ANOMALY_05000380 (0)
Mike Frysingera4136472009-05-08 07:40:25 +0000291#define ANOMALY_05000400 (0)
Yi Libd411b12009-08-05 10:02:14 +0000292#define ANOMALY_05000402 (0)
Mike Frysinger6651ece2009-01-07 23:14:38 +0800293#define ANOMALY_05000412 (0)
294#define ANOMALY_05000432 (0)
Mike Frysinger94b28212008-11-18 17:48:21 +0800295#define ANOMALY_05000435 (0)
Mike Frysinger93f17422011-05-06 02:26:38 -0400296#define ANOMALY_05000440 (0)
Mike Frysingerdc7101b2010-05-27 21:47:31 +0000297#define ANOMALY_05000475 (0)
Mike Frysinger93f17422011-05-06 02:26:38 -0400298#define ANOMALY_05000480 (0)
Sonic Zhangf1a1d522012-10-29 13:50:05 +0800299#define ANOMALY_16000030 (0)
Mike Frysinger1aafd902007-07-25 11:19:14 +0800300
301#endif