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Rafael J. Wysockief8b03f2008-02-09 23:24:09 +01001/*
Sergio Luis6d48bec2009-04-28 00:27:18 +02002 * Suspend support specific for i386/x86-64.
Rafael J. Wysockief8b03f2008-02-09 23:24:09 +01003 *
4 * Distribute under GPLv2
5 *
6 * Copyright (c) 2007 Rafael J. Wysocki <rjw@sisk.pl>
Pavel Macheka2531292010-07-18 14:27:13 +02007 * Copyright (c) 2002 Pavel Machek <pavel@ucw.cz>
Rafael J. Wysockief8b03f2008-02-09 23:24:09 +01008 * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org>
9 */
10
Rafael J. Wysockief8b03f2008-02-09 23:24:09 +010011#include <linux/suspend.h>
Paul Gortmaker69c60c82011-05-26 12:22:53 -040012#include <linux/export.h>
Sergio Luisf6783d22009-04-28 00:26:22 +020013#include <linux/smp.h>
Stephane Eranian1d9d8632013-03-15 14:26:07 +010014#include <linux/perf_event.h>
Rafael J. Wysocki406f9922016-07-14 03:55:23 +020015#include <linux/tboot.h>
Sergio Luisf6783d22009-04-28 00:26:22 +020016
Rafael J. Wysockief8b03f2008-02-09 23:24:09 +010017#include <asm/pgtable.h>
Sergio Luisf6783d22009-04-28 00:26:22 +020018#include <asm/proto.h>
Rafael J. Wysockief8b03f2008-02-09 23:24:09 +010019#include <asm/mtrr.h>
Sergio Luisf6783d22009-04-28 00:26:22 +020020#include <asm/page.h>
21#include <asm/mce.h>
Magnus Damma8af7892009-03-31 15:23:37 -070022#include <asm/suspend.h>
Ingo Molnar952f07e2015-04-26 16:56:05 +020023#include <asm/fpu/internal.h>
K.Prasad1e350062009-06-01 23:44:26 +053024#include <asm/debugreg.h>
Fenghua Yua71c8bc2012-11-13 11:32:51 -080025#include <asm/cpu.h>
Andy Lutomirski37868fe2015-07-30 14:31:32 -070026#include <asm/mmu_context.h>
Chen Yu7a9c2dd2015-11-25 01:03:41 +080027#include <linux/dmi.h>
Rafael J. Wysockief8b03f2008-02-09 23:24:09 +010028
Sergio Luis833b2ca2009-04-28 00:26:50 +020029#ifdef CONFIG_X86_32
Andi Kleend6efc2f2013-08-05 15:02:49 -070030__visible unsigned long saved_context_ebx;
31__visible unsigned long saved_context_esp, saved_context_ebp;
32__visible unsigned long saved_context_esi, saved_context_edi;
33__visible unsigned long saved_context_eflags;
Sergio Luis833b2ca2009-04-28 00:26:50 +020034#endif
Konrad Rzeszutek Wilkcc456c42013-05-01 21:53:30 -040035struct saved_context saved_context;
Rafael J. Wysockief8b03f2008-02-09 23:24:09 +010036
Chen Yu7a9c2dd2015-11-25 01:03:41 +080037static void msr_save_context(struct saved_context *ctxt)
38{
39 struct saved_msr *msr = ctxt->saved_msrs.array;
40 struct saved_msr *end = msr + ctxt->saved_msrs.num;
41
42 while (msr < end) {
43 msr->valid = !rdmsrl_safe(msr->info.msr_no, &msr->info.reg.q);
44 msr++;
45 }
46}
47
48static void msr_restore_context(struct saved_context *ctxt)
49{
50 struct saved_msr *msr = ctxt->saved_msrs.array;
51 struct saved_msr *end = msr + ctxt->saved_msrs.num;
52
53 while (msr < end) {
54 if (msr->valid)
55 wrmsrl(msr->info.msr_no, msr->info.reg.q);
56 msr++;
57 }
58}
59
Rafael J. Wysockief8b03f2008-02-09 23:24:09 +010060/**
61 * __save_processor_state - save CPU registers before creating a
62 * hibernation image and before restoring the memory state from it
63 * @ctxt - structure to store the registers contents in
64 *
65 * NOTE: If there is a CPU register the modification of which by the
66 * boot kernel (ie. the kernel used for loading the hibernation image)
67 * might affect the operations of the restored target kernel (ie. the one
68 * saved in the hibernation image), then its contents must be saved by this
69 * function. In other words, if kernel A is hibernated and different
70 * kernel B is used for loading the hibernation image into memory, the
71 * kernel A's __save_processor_state() function must save all registers
72 * needed by kernel A, so that it can operate correctly after the resume
73 * regardless of what kernel B does in the meantime.
74 */
75static void __save_processor_state(struct saved_context *ctxt)
76{
Sergio Luisf9ebbe52009-04-28 00:27:00 +020077#ifdef CONFIG_X86_32
78 mtrr_save_fixed_ranges(NULL);
79#endif
Rafael J. Wysockief8b03f2008-02-09 23:24:09 +010080 kernel_fpu_begin();
81
82 /*
83 * descriptor tables
84 */
Sergio Luisf9ebbe52009-04-28 00:27:00 +020085#ifdef CONFIG_X86_32
Sergio Luisf9ebbe52009-04-28 00:27:00 +020086 store_idt(&ctxt->idt);
87#else
88/* CONFIG_X86_64 */
Rafael J. Wysockief8b03f2008-02-09 23:24:09 +010089 store_idt((struct desc_ptr *)&ctxt->idt_limit);
Sergio Luisf9ebbe52009-04-28 00:27:00 +020090#endif
Konrad Rzeszutek Wilkcc456c42013-05-01 21:53:30 -040091 /*
92 * We save it here, but restore it only in the hibernate case.
93 * For ACPI S3 resume, this is loaded via 'early_gdt_desc' in 64-bit
94 * mode in "secondary_startup_64". In 32-bit mode it is done via
95 * 'pmode_gdt' in wakeup_start.
96 */
97 ctxt->gdt_desc.size = GDT_SIZE - 1;
98 ctxt->gdt_desc.address = (unsigned long)get_cpu_gdt_table(smp_processor_id());
99
Rafael J. Wysockief8b03f2008-02-09 23:24:09 +0100100 store_tr(ctxt->tr);
101
102 /* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
103 /*
104 * segment registers
105 */
Sergio Luisf9ebbe52009-04-28 00:27:00 +0200106#ifdef CONFIG_X86_32
107 savesegment(es, ctxt->es);
108 savesegment(fs, ctxt->fs);
109 savesegment(gs, ctxt->gs);
110 savesegment(ss, ctxt->ss);
111#else
112/* CONFIG_X86_64 */
Rafael J. Wysockief8b03f2008-02-09 23:24:09 +0100113 asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds));
114 asm volatile ("movw %%es, %0" : "=m" (ctxt->es));
115 asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs));
116 asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs));
117 asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss));
118
119 rdmsrl(MSR_FS_BASE, ctxt->fs_base);
120 rdmsrl(MSR_GS_BASE, ctxt->gs_base);
121 rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
122 mtrr_save_fixed_ranges(NULL);
123
Sergio Luisf9ebbe52009-04-28 00:27:00 +0200124 rdmsrl(MSR_EFER, ctxt->efer);
125#endif
126
Rafael J. Wysockief8b03f2008-02-09 23:24:09 +0100127 /*
128 * control registers
129 */
Rafael J. Wysockief8b03f2008-02-09 23:24:09 +0100130 ctxt->cr0 = read_cr0();
131 ctxt->cr2 = read_cr2();
132 ctxt->cr3 = read_cr3();
Andy Lutomirski1ef55be12016-09-29 12:48:12 -0700133 ctxt->cr4 = __read_cr4();
Andy Lutomirski1e02ce42014-10-24 15:58:08 -0700134#ifdef CONFIG_X86_64
Rafael J. Wysockief8b03f2008-02-09 23:24:09 +0100135 ctxt->cr8 = read_cr8();
Sergio Luisf9ebbe52009-04-28 00:27:00 +0200136#endif
Ondrej Zary85a0e752010-06-08 00:32:49 +0200137 ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE,
138 &ctxt->misc_enable);
Chen Yu7a9c2dd2015-11-25 01:03:41 +0800139 msr_save_context(ctxt);
Rafael J. Wysockief8b03f2008-02-09 23:24:09 +0100140}
141
Sergio Luisf9ebbe52009-04-28 00:27:00 +0200142/* Needed by apm.c */
Rafael J. Wysockief8b03f2008-02-09 23:24:09 +0100143void save_processor_state(void)
144{
145 __save_processor_state(&saved_context);
Marcelo Tosattib74f05d62012-02-13 11:07:27 -0200146 x86_platform.save_sched_clock_state();
Rafael J. Wysockief8b03f2008-02-09 23:24:09 +0100147}
Sergio Luisf9ebbe52009-04-28 00:27:00 +0200148#ifdef CONFIG_X86_32
149EXPORT_SYMBOL(save_processor_state);
150#endif
Rafael J. Wysockief8b03f2008-02-09 23:24:09 +0100151
152static void do_fpu_end(void)
153{
154 /*
Sergio Luis3134d042009-04-28 00:27:05 +0200155 * Restore FPU regs if necessary.
Rafael J. Wysockief8b03f2008-02-09 23:24:09 +0100156 */
157 kernel_fpu_end();
158}
159
Sergio Luis3134d042009-04-28 00:27:05 +0200160static void fix_processor_context(void)
161{
162 int cpu = smp_processor_id();
Andy Lutomirski24933b82015-03-05 19:19:05 -0800163 struct tss_struct *t = &per_cpu(cpu_tss, cpu);
konrad@kernel.org4d681be2013-04-05 16:42:24 -0400164#ifdef CONFIG_X86_64
165 struct desc_struct *desc = get_cpu_gdt_table(cpu);
166 tss_desc tss;
167#endif
Sergio Luis3134d042009-04-28 00:27:05 +0200168 set_tss_desc(cpu, t); /*
169 * This just modifies memory; should not be
170 * necessary. But... This is necessary, because
171 * 386 hardware has concept of busy TSS or some
172 * similar stupidity.
173 */
174
175#ifdef CONFIG_X86_64
konrad@kernel.org4d681be2013-04-05 16:42:24 -0400176 memcpy(&tss, &desc[GDT_ENTRY_TSS], sizeof(tss_desc));
177 tss.type = 0x9; /* The available 64-bit TSS (see AMD vol 2, pg 91 */
178 write_gdt_entry(desc, GDT_ENTRY_TSS, &tss, DESC_TSS);
Sergio Luis3134d042009-04-28 00:27:05 +0200179
180 syscall_init(); /* This sets MSR_*STAR and related */
181#endif
182 load_TR_desc(); /* This does ltr */
Andy Lutomirski37868fe2015-07-30 14:31:32 -0700183 load_mm_ldt(current->active_mm); /* This does lldt */
Ingo Molnar9254aaa2015-04-24 10:02:32 +0200184
185 fpu__resume_cpu();
Sergio Luis3134d042009-04-28 00:27:05 +0200186}
187
Rafael J. Wysockief8b03f2008-02-09 23:24:09 +0100188/**
189 * __restore_processor_state - restore the contents of CPU registers saved
190 * by __save_processor_state()
191 * @ctxt - structure to load the registers contents from
192 */
Steven Rostedt (Red Hat)b8f99b32014-06-24 20:58:26 -0400193static void notrace __restore_processor_state(struct saved_context *ctxt)
Rafael J. Wysockief8b03f2008-02-09 23:24:09 +0100194{
Ondrej Zary85a0e752010-06-08 00:32:49 +0200195 if (ctxt->misc_enable_saved)
196 wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable);
Rafael J. Wysockief8b03f2008-02-09 23:24:09 +0100197 /*
198 * control registers
199 */
Sergio Luis3134d042009-04-28 00:27:05 +0200200 /* cr4 was introduced in the Pentium CPU */
201#ifdef CONFIG_X86_32
202 if (ctxt->cr4)
Andy Lutomirski1e02ce42014-10-24 15:58:08 -0700203 __write_cr4(ctxt->cr4);
Sergio Luis3134d042009-04-28 00:27:05 +0200204#else
205/* CONFIG X86_64 */
Rafael J. Wysockief8b03f2008-02-09 23:24:09 +0100206 wrmsrl(MSR_EFER, ctxt->efer);
207 write_cr8(ctxt->cr8);
Andy Lutomirski1e02ce42014-10-24 15:58:08 -0700208 __write_cr4(ctxt->cr4);
Sergio Luis3134d042009-04-28 00:27:05 +0200209#endif
Rafael J. Wysockief8b03f2008-02-09 23:24:09 +0100210 write_cr3(ctxt->cr3);
211 write_cr2(ctxt->cr2);
212 write_cr0(ctxt->cr0);
213
214 /*
215 * now restore the descriptor tables to their proper values
216 * ltr is done i fix_processor_context().
217 */
Sergio Luis3134d042009-04-28 00:27:05 +0200218#ifdef CONFIG_X86_32
Sergio Luis3134d042009-04-28 00:27:05 +0200219 load_idt(&ctxt->idt);
220#else
221/* CONFIG_X86_64 */
Rafael J. Wysockief8b03f2008-02-09 23:24:09 +0100222 load_idt((const struct desc_ptr *)&ctxt->idt_limit);
Sergio Luis3134d042009-04-28 00:27:05 +0200223#endif
Rafael J. Wysockief8b03f2008-02-09 23:24:09 +0100224
225 /*
226 * segment registers
227 */
Sergio Luis3134d042009-04-28 00:27:05 +0200228#ifdef CONFIG_X86_32
229 loadsegment(es, ctxt->es);
230 loadsegment(fs, ctxt->fs);
231 loadsegment(gs, ctxt->gs);
232 loadsegment(ss, ctxt->ss);
233
234 /*
235 * sysenter MSRs
236 */
237 if (boot_cpu_has(X86_FEATURE_SEP))
238 enable_sep_cpu();
239#else
240/* CONFIG_X86_64 */
Rafael J. Wysockief8b03f2008-02-09 23:24:09 +0100241 asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds));
242 asm volatile ("movw %0, %%es" :: "r" (ctxt->es));
243 asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs));
244 load_gs_index(ctxt->gs);
245 asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss));
246
247 wrmsrl(MSR_FS_BASE, ctxt->fs_base);
248 wrmsrl(MSR_GS_BASE, ctxt->gs_base);
249 wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
Sergio Luis3134d042009-04-28 00:27:05 +0200250#endif
Rafael J. Wysockief8b03f2008-02-09 23:24:09 +0100251
Rafael J. Wysockief8b03f2008-02-09 23:24:09 +0100252 fix_processor_context();
253
254 do_fpu_end();
Thomas Gleixner6a369582016-12-13 13:14:17 +0000255 tsc_verify_tsc_adjust(true);
Marcelo Tosattidba69d12012-04-01 13:53:36 -0300256 x86_platform.restore_sched_clock_state();
Suresh Siddhad0af9ee2009-08-19 18:05:36 -0700257 mtrr_bp_restore();
Stephane Eranian1d9d8632013-03-15 14:26:07 +0100258 perf_restore_debug_store();
Chen Yu7a9c2dd2015-11-25 01:03:41 +0800259 msr_restore_context(ctxt);
Rafael J. Wysockief8b03f2008-02-09 23:24:09 +0100260}
261
Sergio Luis3134d042009-04-28 00:27:05 +0200262/* Needed by apm.c */
Steven Rostedt (Red Hat)b8f99b32014-06-24 20:58:26 -0400263void notrace restore_processor_state(void)
Rafael J. Wysockief8b03f2008-02-09 23:24:09 +0100264{
265 __restore_processor_state(&saved_context);
266}
Sergio Luis3134d042009-04-28 00:27:05 +0200267#ifdef CONFIG_X86_32
268EXPORT_SYMBOL(restore_processor_state);
269#endif
Fenghua Yu209efae2012-11-13 11:32:42 -0800270
Rafael J. Wysocki406f9922016-07-14 03:55:23 +0200271#if defined(CONFIG_HIBERNATION) && defined(CONFIG_HOTPLUG_CPU)
272static void resume_play_dead(void)
273{
274 play_dead_common();
275 tboot_shutdown(TB_SHUTDOWN_WFS);
276 hlt_play_dead();
277}
278
279int hibernate_resume_nonboot_cpu_disable(void)
280{
281 void (*play_dead)(void) = smp_ops.play_dead;
282 int ret;
283
284 /*
285 * Ensure that MONITOR/MWAIT will not be used in the "play dead" loop
286 * during hibernate image restoration, because it is likely that the
287 * monitored address will be actually written to at that time and then
288 * the "dead" CPU will attempt to execute instructions again, but the
289 * address in its instruction pointer may not be possible to resolve
290 * any more at that point (the page tables used by it previously may
291 * have been overwritten by hibernate image data).
292 */
293 smp_ops.play_dead = resume_play_dead;
294 ret = disable_nonboot_cpus();
295 smp_ops.play_dead = play_dead;
296 return ret;
297}
298#endif
299
Fenghua Yu209efae2012-11-13 11:32:42 -0800300/*
301 * When bsp_check() is called in hibernate and suspend, cpu hotplug
302 * is disabled already. So it's unnessary to handle race condition between
303 * cpumask query and cpu hotplug.
304 */
305static int bsp_check(void)
306{
307 if (cpumask_first(cpu_online_mask) != 0) {
308 pr_warn("CPU0 is offline.\n");
309 return -ENODEV;
310 }
311
312 return 0;
313}
314
315static int bsp_pm_callback(struct notifier_block *nb, unsigned long action,
316 void *ptr)
317{
318 int ret = 0;
319
320 switch (action) {
321 case PM_SUSPEND_PREPARE:
322 case PM_HIBERNATION_PREPARE:
323 ret = bsp_check();
324 break;
Fenghua Yua71c8bc2012-11-13 11:32:51 -0800325#ifdef CONFIG_DEBUG_HOTPLUG_CPU0
326 case PM_RESTORE_PREPARE:
327 /*
328 * When system resumes from hibernation, online CPU0 because
329 * 1. it's required for resume and
330 * 2. the CPU was online before hibernation
331 */
332 if (!cpu_online(0))
333 _debug_hotplug_cpu(0, 1);
334 break;
335 case PM_POST_RESTORE:
336 /*
337 * When a resume really happens, this code won't be called.
338 *
339 * This code is called only when user space hibernation software
340 * prepares for snapshot device during boot time. So we just
341 * call _debug_hotplug_cpu() to restore to CPU0's state prior to
342 * preparing the snapshot device.
343 *
344 * This works for normal boot case in our CPU0 hotplug debug
345 * mode, i.e. CPU0 is offline and user mode hibernation
346 * software initializes during boot time.
347 *
348 * If CPU0 is online and user application accesses snapshot
349 * device after boot time, this will offline CPU0 and user may
350 * see different CPU0 state before and after accessing
351 * the snapshot device. But hopefully this is not a case when
352 * user debugging CPU0 hotplug. Even if users hit this case,
353 * they can easily online CPU0 back.
354 *
355 * To simplify this debug code, we only consider normal boot
356 * case. Otherwise we need to remember CPU0's state and restore
357 * to that state and resolve racy conditions etc.
358 */
359 _debug_hotplug_cpu(0, 0);
360 break;
361#endif
Fenghua Yu209efae2012-11-13 11:32:42 -0800362 default:
363 break;
364 }
365 return notifier_from_errno(ret);
366}
367
368static int __init bsp_pm_check_init(void)
369{
370 /*
371 * Set this bsp_pm_callback as lower priority than
372 * cpu_hotplug_pm_callback. So cpu_hotplug_pm_callback will be called
373 * earlier to disable cpu hotplug before bsp online check.
374 */
375 pm_notifier(bsp_pm_callback, -INT_MAX);
376 return 0;
377}
378
379core_initcall(bsp_pm_check_init);
Chen Yu7a9c2dd2015-11-25 01:03:41 +0800380
381static int msr_init_context(const u32 *msr_id, const int total_num)
382{
383 int i = 0;
384 struct saved_msr *msr_array;
385
386 if (saved_context.saved_msrs.array || saved_context.saved_msrs.num > 0) {
387 pr_err("x86/pm: MSR quirk already applied, please check your DMI match table.\n");
388 return -EINVAL;
389 }
390
391 msr_array = kmalloc_array(total_num, sizeof(struct saved_msr), GFP_KERNEL);
392 if (!msr_array) {
393 pr_err("x86/pm: Can not allocate memory to save/restore MSRs during suspend.\n");
394 return -ENOMEM;
395 }
396
397 for (i = 0; i < total_num; i++) {
398 msr_array[i].info.msr_no = msr_id[i];
399 msr_array[i].valid = false;
400 msr_array[i].info.reg.q = 0;
401 }
402 saved_context.saved_msrs.num = total_num;
403 saved_context.saved_msrs.array = msr_array;
404
405 return 0;
406}
407
408/*
409 * The following section is a quirk framework for problematic BIOSen:
410 * Sometimes MSRs are modified by the BIOSen after suspended to
411 * RAM, this might cause unexpected behavior after wakeup.
412 * Thus we save/restore these specified MSRs across suspend/resume
413 * in order to work around it.
414 *
415 * For any further problematic BIOSen/platforms,
416 * please add your own function similar to msr_initialize_bdw.
417 */
418static int msr_initialize_bdw(const struct dmi_system_id *d)
419{
420 /* Add any extra MSR ids into this array. */
421 u32 bdw_msr_id[] = { MSR_IA32_THERM_CONTROL };
422
423 pr_info("x86/pm: %s detected, MSR saving is needed during suspending.\n", d->ident);
424 return msr_init_context(bdw_msr_id, ARRAY_SIZE(bdw_msr_id));
425}
426
427static struct dmi_system_id msr_save_dmi_table[] = {
428 {
429 .callback = msr_initialize_bdw,
430 .ident = "BROADWELL BDX_EP",
431 .matches = {
432 DMI_MATCH(DMI_PRODUCT_NAME, "GRANTLEY"),
433 DMI_MATCH(DMI_PRODUCT_VERSION, "E63448-400"),
434 },
435 },
436 {}
437};
438
439static int pm_check_save_msr(void)
440{
441 dmi_check_system(msr_save_dmi_table);
442 return 0;
443}
444
445device_initcall(pm_check_save_msr);