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Paul Mackerras14cf11a2005-09-26 16:04:21 +10001/*
2 * FPU support code, moved here from head.S so that it can be used
3 * by chips which use other head-whatever.S files.
4 *
Paul Mackerrasfea23bf2006-08-30 14:45:35 +10005 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Copyright (C) 1996 Paul Mackerras.
8 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
9 *
Paul Mackerras14cf11a2005-09-26 16:04:21 +100010 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 *
15 */
16
Paul Mackerrasb3b8dc62005-10-10 22:20:10 +100017#include <asm/reg.h>
Paul Mackerras14cf11a2005-09-26 16:04:21 +100018#include <asm/page.h>
19#include <asm/mmu.h>
20#include <asm/pgtable.h>
21#include <asm/cputable.h>
22#include <asm/cache.h>
23#include <asm/thread_info.h>
24#include <asm/ppc_asm.h>
25#include <asm/asm-offsets.h>
Stephen Rothwell46f52212010-11-18 15:06:17 +000026#include <asm/ptrace.h>
Al Viro9445aa12016-01-13 23:33:46 -050027#include <asm/export.h>
Christophe Leroyec0c4642018-07-05 16:24:57 +000028#include <asm/asm-compat.h>
Christophe Leroy2c86cd12018-07-05 16:25:01 +000029#include <asm/feature-fixups.h>
Paul Mackerras14cf11a2005-09-26 16:04:21 +100030
Michael Neuling72ffff52008-06-25 14:07:18 +100031#ifdef CONFIG_VSX
Michael Neuling0b7673c2012-06-25 13:33:23 +000032#define __REST_32FPVSRS(n,c,base) \
Michael Neuling72ffff52008-06-25 14:07:18 +100033BEGIN_FTR_SECTION \
34 b 2f; \
35END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
36 REST_32FPRS(n,base); \
37 b 3f; \
382: REST_32VSRS(n,c,base); \
393:
40
Michael Neuling0b7673c2012-06-25 13:33:23 +000041#define __SAVE_32FPVSRS(n,c,base) \
Michael Neuling72ffff52008-06-25 14:07:18 +100042BEGIN_FTR_SECTION \
43 b 2f; \
44END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
45 SAVE_32FPRS(n,base); \
46 b 3f; \
472: SAVE_32VSRS(n,c,base); \
483:
49#else
Michael Neuling0b7673c2012-06-25 13:33:23 +000050#define __REST_32FPVSRS(n,b,base) REST_32FPRS(n, base)
51#define __SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base)
Michael Neuling72ffff52008-06-25 14:07:18 +100052#endif
Michael Neuling0b7673c2012-06-25 13:33:23 +000053#define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base)
54#define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base)
Michael Neuling72ffff52008-06-25 14:07:18 +100055
Paul Mackerras14cf11a2005-09-26 16:04:21 +100056/*
Paul Mackerras18461962013-09-10 20:21:10 +100057 * Load state from memory into FP registers including FPSCR.
58 * Assumes the caller has enabled FP in the MSR.
59 */
60_GLOBAL(load_fp_state)
61 lfd fr0,FPSTATE_FPSCR(r3)
62 MTFSF_L(fr0)
63 REST_32FPVSRS(0, R4, R3)
64 blr
Al Viro9445aa12016-01-13 23:33:46 -050065EXPORT_SYMBOL(load_fp_state)
Paul Mackerras18461962013-09-10 20:21:10 +100066
67/*
68 * Store FP state into memory, including FPSCR
69 * Assumes the caller has enabled FP in the MSR.
70 */
71_GLOBAL(store_fp_state)
72 SAVE_32FPVSRS(0, R4, R3)
73 mffs fr0
74 stfd fr0,FPSTATE_FPSCR(r3)
75 blr
Al Viro9445aa12016-01-13 23:33:46 -050076EXPORT_SYMBOL(store_fp_state)
Paul Mackerras18461962013-09-10 20:21:10 +100077
78/*
Paul Mackerras14cf11a2005-09-26 16:04:21 +100079 * This task wants to use the FPU now.
80 * On UP, disable FP for the task which had the FPU previously,
81 * and save its floating-point registers in its thread_struct.
82 * Load up this task's FP registers from its thread_struct,
83 * enable the FPU for the current task and return to the task.
Paul Mackerras955c1ca2013-10-23 09:40:02 +010084 * Note that on 32-bit this can only use registers that will be
85 * restored by fast_exception_return, i.e. r3 - r6, r10 and r11.
Paul Mackerras14cf11a2005-09-26 16:04:21 +100086 */
Paul Mackerrasb85a0462005-10-06 10:59:19 +100087_GLOBAL(load_up_fpu)
Paul Mackerras14cf11a2005-09-26 16:04:21 +100088 mfmsr r5
89 ori r5,r5,MSR_FP
Michael Neulingce48b212008-06-25 14:07:18 +100090#ifdef CONFIG_VSX
91BEGIN_FTR_SECTION
92 oris r5,r5,MSR_VSX@h
93END_FTR_SECTION_IFSET(CPU_FTR_VSX)
94#endif
Paul Mackerras14cf11a2005-09-26 16:04:21 +100095 SYNC
96 MTMSRD(r5) /* enable use of fpu now */
97 isync
Paul Mackerras14cf11a2005-09-26 16:04:21 +100098 /* enable use of FP after return */
Paul Mackerrasb85a0462005-10-06 10:59:19 +100099#ifdef CONFIG_PPC32
Paul Mackerrasde79f7b2013-09-10 20:20:42 +1000100 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000101 lwz r4,THREAD_FPEXC_MODE(r5)
102 ori r9,r9,MSR_FP /* enable FP for current */
103 or r9,r9,r4
Paul Mackerrasb85a0462005-10-06 10:59:19 +1000104#else
105 ld r4,PACACURRENT(r13)
106 addi r5,r4,THREAD /* Get THREAD */
Paul Mackerrase2f5a3c2006-02-07 13:55:30 +1100107 lwz r4,THREAD_FPEXC_MODE(r5)
Paul Mackerrasb85a0462005-10-06 10:59:19 +1000108 ori r12,r12,MSR_FP
109 or r12,r12,r4
110 std r12,_MSR(r1)
111#endif
Cyril Bur70fe3d92016-02-29 17:53:47 +1100112 /* Don't care if r4 overflows, this is desired behaviour */
113 lbz r4,THREAD_LOAD_FP(r5)
114 addi r4,r4,1
115 stb r4,THREAD_LOAD_FP(r5)
Paul Mackerras955c1ca2013-10-23 09:40:02 +0100116 addi r10,r5,THREAD_FPSTATE
117 lfd fr0,FPSTATE_FPSCR(r10)
Anton Blanchard3a2c48c2006-06-10 20:18:39 +1000118 MTFSF_L(fr0)
Paul Mackerras955c1ca2013-10-23 09:40:02 +0100119 REST_32FPVSRS(0, R4, R10)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000120 /* restore registers and return */
121 /* we haven't used ctr or xer or lr */
Michael Neuling6f3d8e62008-06-25 14:07:18 +1000122 blr
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000123
124/*
Cyril Bur87924682016-02-29 17:53:49 +1100125 * save_fpu(tsk)
126 * Save the floating-point registers in its thread_struct.
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000127 * Enables the FPU for use in the kernel on return.
128 */
Cyril Bur87924682016-02-29 17:53:49 +1100129_GLOBAL(save_fpu)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000130 addi r3,r3,THREAD /* want THREAD of task */
Paul Mackerras18461962013-09-10 20:21:10 +1000131 PPC_LL r6,THREAD_FPSAVEAREA(r3)
David Gibson3ddfbcf2005-11-10 12:56:55 +1100132 PPC_LL r5,PT_REGS(r3)
Paul Mackerras18461962013-09-10 20:21:10 +1000133 PPC_LCMPI 0,r6,0
134 bne 2f
Paul Mackerrasde79f7b2013-09-10 20:20:42 +1000135 addi r6,r3,THREAD_FPSTATE
Cyril Bur87924682016-02-29 17:53:49 +11001362: SAVE_32FPVSRS(0, R4, R6)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000137 mffs fr0
Paul Mackerrasde79f7b2013-09-10 20:20:42 +1000138 stfd fr0,FPSTATE_FPSCR(r6)
Paul Mackerras14cf11a2005-09-26 16:04:21 +1000139 blr
David Gibson25c8a782005-10-27 16:27:25 +1000140
141/*
142 * These are used in the alignment trap handler when emulating
143 * single-precision loads and stores.
David Gibson25c8a782005-10-27 16:27:25 +1000144 */
145
146_GLOBAL(cvt_fd)
David Gibson25c8a782005-10-27 16:27:25 +1000147 lfs 0,0(r3)
148 stfd 0,0(r4)
David Gibson25c8a782005-10-27 16:27:25 +1000149 blr
150
151_GLOBAL(cvt_df)
David Gibson25c8a782005-10-27 16:27:25 +1000152 lfd 0,0(r3)
153 stfs 0,0(r4)
David Gibson25c8a782005-10-27 16:27:25 +1000154 blr