Dan Murphy | 2a10154 | 2015-06-02 09:34:37 -0500 | [diff] [blame] | 1 | * Texas Instruments - dp83867 Giga bit ethernet phy |
| 2 | |
| 3 | Required properties: |
| 4 | - reg - The ID number for the phy, usually a small integer |
Eric Engestrom | dd346f27 | 2016-04-25 01:24:15 +0100 | [diff] [blame] | 5 | - ti,rx-internal-delay - RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h |
Karicheri, Muralidharan | 34c55cf | 2017-01-13 09:32:34 -0500 | [diff] [blame] | 6 | for applicable values. Required only if interface type is |
| 7 | PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID |
Dan Murphy | ac7ba51 | 2015-06-08 14:30:55 -0500 | [diff] [blame] | 8 | - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h |
Karicheri, Muralidharan | 34c55cf | 2017-01-13 09:32:34 -0500 | [diff] [blame] | 9 | for applicable values. Required only if interface type is |
| 10 | PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_TXID |
Dan Murphy | ac7ba51 | 2015-06-08 14:30:55 -0500 | [diff] [blame] | 11 | - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h |
Dan Murphy | 2a10154 | 2015-06-02 09:34:37 -0500 | [diff] [blame] | 12 | for applicable values |
| 13 | |
Mugunthan V N | d6081de7 | 2016-10-18 16:50:17 +0530 | [diff] [blame] | 14 | Optional property: |
| 15 | - ti,min-output-impedance - MAC Interface Impedance control to set |
| 16 | the programmable output impedance to |
| 17 | minimum value (35 ohms). |
| 18 | - ti,max-output-impedance - MAC Interface Impedance control to set |
| 19 | the programmable output impedance to |
| 20 | maximum value (70 ohms). |
Murali Karicheri | 908a773 | 2017-07-04 16:23:23 +0530 | [diff] [blame] | 21 | - ti,dp83867-rxctrl-strap-quirk - This denotes the fact that the |
| 22 | board has RX_DV/RX_CTRL pin strapped in |
| 23 | mode 1 or 2. To ensure PHY operation, |
| 24 | there are specific actions that |
| 25 | software needs to take when this pin is |
| 26 | strapped in these modes. See data manual |
| 27 | for details. |
Wadim Egorov | 0e47079 | 2018-02-14 17:07:12 +0100 | [diff] [blame] | 28 | - ti,clk-output-sel - Muxing option for CLK_OUT pin - see dt-bindings/net/ti-dp83867.h |
| 29 | for applicable values. |
Mugunthan V N | d6081de7 | 2016-10-18 16:50:17 +0530 | [diff] [blame] | 30 | |
| 31 | Note: ti,min-output-impedance and ti,max-output-impedance are mutually |
| 32 | exclusive. When both properties are present ti,max-output-impedance |
| 33 | takes precedence. |
| 34 | |
Dan Murphy | ac7ba51 | 2015-06-08 14:30:55 -0500 | [diff] [blame] | 35 | Default child nodes are standard Ethernet PHY device |
| 36 | nodes as described in Documentation/devicetree/bindings/net/phy.txt |
| 37 | |
Dan Murphy | 2a10154 | 2015-06-02 09:34:37 -0500 | [diff] [blame] | 38 | Example: |
| 39 | |
| 40 | ethernet-phy@0 { |
| 41 | reg = <0>; |
Dan Murphy | ac7ba51 | 2015-06-08 14:30:55 -0500 | [diff] [blame] | 42 | ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; |
| 43 | ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>; |
| 44 | ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; |
Dan Murphy | 2a10154 | 2015-06-02 09:34:37 -0500 | [diff] [blame] | 45 | }; |
Dan Murphy | ac7ba51 | 2015-06-08 14:30:55 -0500 | [diff] [blame] | 46 | |
| 47 | Datasheet can be found: |
| 48 | http://www.ti.com/product/DP83867IR/datasheet |