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Dan Murphy2a101542015-06-02 09:34:37 -05001* Texas Instruments - dp83867 Giga bit ethernet phy
2
3Required properties:
4 - reg - The ID number for the phy, usually a small integer
Eric Engestromdd346f272016-04-25 01:24:15 +01005 - ti,rx-internal-delay - RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h
Karicheri, Muralidharan34c55cf2017-01-13 09:32:34 -05006 for applicable values. Required only if interface type is
7 PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID
Dan Murphyac7ba512015-06-08 14:30:55 -05008 - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
Karicheri, Muralidharan34c55cf2017-01-13 09:32:34 -05009 for applicable values. Required only if interface type is
10 PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_TXID
Dan Murphyac7ba512015-06-08 14:30:55 -050011 - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
Dan Murphy2a101542015-06-02 09:34:37 -050012 for applicable values
13
Mugunthan V Nd6081de72016-10-18 16:50:17 +053014Optional property:
15 - ti,min-output-impedance - MAC Interface Impedance control to set
16 the programmable output impedance to
17 minimum value (35 ohms).
18 - ti,max-output-impedance - MAC Interface Impedance control to set
19 the programmable output impedance to
20 maximum value (70 ohms).
Murali Karicheri908a7732017-07-04 16:23:23 +053021 - ti,dp83867-rxctrl-strap-quirk - This denotes the fact that the
22 board has RX_DV/RX_CTRL pin strapped in
23 mode 1 or 2. To ensure PHY operation,
24 there are specific actions that
25 software needs to take when this pin is
26 strapped in these modes. See data manual
27 for details.
Wadim Egorov0e470792018-02-14 17:07:12 +010028 - ti,clk-output-sel - Muxing option for CLK_OUT pin - see dt-bindings/net/ti-dp83867.h
29 for applicable values.
Mugunthan V Nd6081de72016-10-18 16:50:17 +053030
31Note: ti,min-output-impedance and ti,max-output-impedance are mutually
32 exclusive. When both properties are present ti,max-output-impedance
33 takes precedence.
34
Dan Murphyac7ba512015-06-08 14:30:55 -050035Default child nodes are standard Ethernet PHY device
36nodes as described in Documentation/devicetree/bindings/net/phy.txt
37
Dan Murphy2a101542015-06-02 09:34:37 -050038Example:
39
40 ethernet-phy@0 {
41 reg = <0>;
Dan Murphyac7ba512015-06-08 14:30:55 -050042 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
43 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
44 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
Dan Murphy2a101542015-06-02 09:34:37 -050045 };
Dan Murphyac7ba512015-06-08 14:30:55 -050046
47Datasheet can be found:
48http://www.ti.com/product/DP83867IR/datasheet