Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* $Id: pci_psycho.c,v 1.33 2002/02/01 00:58:33 davem Exp $ |
| 2 | * pci_psycho.c: PSYCHO/U2P specific PCI controller support. |
| 3 | * |
| 4 | * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@caipfs.rutgers.edu) |
| 5 | * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be) |
| 6 | * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com) |
| 7 | */ |
| 8 | |
| 9 | #include <linux/kernel.h> |
| 10 | #include <linux/types.h> |
| 11 | #include <linux/pci.h> |
| 12 | #include <linux/init.h> |
| 13 | #include <linux/slab.h> |
| 14 | #include <linux/interrupt.h> |
| 15 | |
| 16 | #include <asm/pbm.h> |
| 17 | #include <asm/iommu.h> |
| 18 | #include <asm/irq.h> |
| 19 | #include <asm/starfire.h> |
| 20 | |
| 21 | #include "pci_impl.h" |
| 22 | #include "iommu_common.h" |
| 23 | |
| 24 | /* All PSYCHO registers are 64-bits. The following accessor |
| 25 | * routines are how they are accessed. The REG parameter |
| 26 | * is a physical address. |
| 27 | */ |
| 28 | #define psycho_read(__reg) \ |
| 29 | ({ u64 __ret; \ |
| 30 | __asm__ __volatile__("ldxa [%1] %2, %0" \ |
| 31 | : "=r" (__ret) \ |
| 32 | : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \ |
| 33 | : "memory"); \ |
| 34 | __ret; \ |
| 35 | }) |
| 36 | #define psycho_write(__reg, __val) \ |
| 37 | __asm__ __volatile__("stxa %0, [%1] %2" \ |
| 38 | : /* no outputs */ \ |
| 39 | : "r" (__val), "r" (__reg), \ |
| 40 | "i" (ASI_PHYS_BYPASS_EC_E) \ |
| 41 | : "memory") |
| 42 | |
| 43 | /* Misc. PSYCHO PCI controller register offsets and definitions. */ |
| 44 | #define PSYCHO_CONTROL 0x0010UL |
| 45 | #define PSYCHO_CONTROL_IMPL 0xf000000000000000UL /* Implementation of this PSYCHO*/ |
| 46 | #define PSYCHO_CONTROL_VER 0x0f00000000000000UL /* Version of this PSYCHO */ |
| 47 | #define PSYCHO_CONTROL_MID 0x00f8000000000000UL /* UPA Module ID of PSYCHO */ |
| 48 | #define PSYCHO_CONTROL_IGN 0x0007c00000000000UL /* Interrupt Group Number */ |
| 49 | #define PSYCHO_CONTROL_RESV 0x00003ffffffffff0UL /* Reserved */ |
| 50 | #define PSYCHO_CONTROL_APCKEN 0x0000000000000008UL /* Address Parity Check Enable */ |
| 51 | #define PSYCHO_CONTROL_APERR 0x0000000000000004UL /* Incoming System Addr Parerr */ |
| 52 | #define PSYCHO_CONTROL_IAP 0x0000000000000002UL /* Invert UPA Parity */ |
| 53 | #define PSYCHO_CONTROL_MODE 0x0000000000000001UL /* PSYCHO clock mode */ |
| 54 | #define PSYCHO_PCIA_CTRL 0x2000UL |
| 55 | #define PSYCHO_PCIB_CTRL 0x4000UL |
| 56 | #define PSYCHO_PCICTRL_RESV1 0xfffffff000000000UL /* Reserved */ |
| 57 | #define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000UL /* Streaming byte hole error */ |
| 58 | #define PSYCHO_PCICTRL_SERR 0x0000000400000000UL /* SERR signal asserted */ |
| 59 | #define PSYCHO_PCICTRL_SPEED 0x0000000200000000UL /* PCI speed (1 is U2P clock) */ |
| 60 | #define PSYCHO_PCICTRL_RESV2 0x00000001ffc00000UL /* Reserved */ |
| 61 | #define PSYCHO_PCICTRL_ARB_PARK 0x0000000000200000UL /* PCI arbitration parking */ |
| 62 | #define PSYCHO_PCICTRL_RESV3 0x00000000001ff800UL /* Reserved */ |
| 63 | #define PSYCHO_PCICTRL_SBH_INT 0x0000000000000400UL /* Streaming byte hole int enab */ |
| 64 | #define PSYCHO_PCICTRL_WEN 0x0000000000000200UL /* Power Mgmt Wake Enable */ |
| 65 | #define PSYCHO_PCICTRL_EEN 0x0000000000000100UL /* PCI Error Interrupt Enable */ |
| 66 | #define PSYCHO_PCICTRL_RESV4 0x00000000000000c0UL /* Reserved */ |
| 67 | #define PSYCHO_PCICTRL_AEN 0x000000000000003fUL /* PCI DVMA Arbitration Enable */ |
| 68 | |
| 69 | /* U2P Programmer's Manual, page 13-55, configuration space |
| 70 | * address format: |
| 71 | * |
| 72 | * 32 24 23 16 15 11 10 8 7 2 1 0 |
| 73 | * --------------------------------------------------------- |
| 74 | * |0 0 0 0 0 0 0 0 1| bus | device | function | reg | 0 0 | |
| 75 | * --------------------------------------------------------- |
| 76 | */ |
| 77 | #define PSYCHO_CONFIG_BASE(PBM) \ |
| 78 | ((PBM)->config_space | (1UL << 24)) |
| 79 | #define PSYCHO_CONFIG_ENCODE(BUS, DEVFN, REG) \ |
| 80 | (((unsigned long)(BUS) << 16) | \ |
| 81 | ((unsigned long)(DEVFN) << 8) | \ |
| 82 | ((unsigned long)(REG))) |
| 83 | |
| 84 | static void *psycho_pci_config_mkaddr(struct pci_pbm_info *pbm, |
| 85 | unsigned char bus, |
| 86 | unsigned int devfn, |
| 87 | int where) |
| 88 | { |
| 89 | if (!pbm) |
| 90 | return NULL; |
| 91 | return (void *) |
| 92 | (PSYCHO_CONFIG_BASE(pbm) | |
| 93 | PSYCHO_CONFIG_ENCODE(bus, devfn, where)); |
| 94 | } |
| 95 | |
| 96 | static int psycho_out_of_range(struct pci_pbm_info *pbm, |
| 97 | unsigned char bus, |
| 98 | unsigned char devfn) |
| 99 | { |
| 100 | return ((pbm->parent == 0) || |
| 101 | ((pbm == &pbm->parent->pbm_B) && |
| 102 | (bus == pbm->pci_first_busno) && |
| 103 | PCI_SLOT(devfn) > 8) || |
| 104 | ((pbm == &pbm->parent->pbm_A) && |
| 105 | (bus == pbm->pci_first_busno) && |
| 106 | PCI_SLOT(devfn) > 8)); |
| 107 | } |
| 108 | |
| 109 | /* PSYCHO PCI configuration space accessors. */ |
| 110 | |
| 111 | static int psycho_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn, |
| 112 | int where, int size, u32 *value) |
| 113 | { |
| 114 | struct pci_pbm_info *pbm = bus_dev->sysdata; |
| 115 | unsigned char bus = bus_dev->number; |
| 116 | u32 *addr; |
| 117 | u16 tmp16; |
| 118 | u8 tmp8; |
| 119 | |
| 120 | switch (size) { |
| 121 | case 1: |
| 122 | *value = 0xff; |
| 123 | break; |
| 124 | case 2: |
| 125 | *value = 0xffff; |
| 126 | break; |
| 127 | case 4: |
| 128 | *value = 0xffffffff; |
| 129 | break; |
| 130 | } |
| 131 | |
| 132 | addr = psycho_pci_config_mkaddr(pbm, bus, devfn, where); |
| 133 | if (!addr) |
| 134 | return PCIBIOS_SUCCESSFUL; |
| 135 | |
| 136 | if (psycho_out_of_range(pbm, bus, devfn)) |
| 137 | return PCIBIOS_SUCCESSFUL; |
| 138 | switch (size) { |
| 139 | case 1: |
| 140 | pci_config_read8((u8 *)addr, &tmp8); |
| 141 | *value = (u32) tmp8; |
| 142 | break; |
| 143 | |
| 144 | case 2: |
| 145 | if (where & 0x01) { |
| 146 | printk("pci_read_config_word: misaligned reg [%x]\n", |
| 147 | where); |
| 148 | return PCIBIOS_SUCCESSFUL; |
| 149 | } |
| 150 | pci_config_read16((u16 *)addr, &tmp16); |
| 151 | *value = (u32) tmp16; |
| 152 | break; |
| 153 | |
| 154 | case 4: |
| 155 | if (where & 0x03) { |
| 156 | printk("pci_read_config_dword: misaligned reg [%x]\n", |
| 157 | where); |
| 158 | return PCIBIOS_SUCCESSFUL; |
| 159 | } |
| 160 | pci_config_read32(addr, value); |
| 161 | break; |
| 162 | } |
| 163 | return PCIBIOS_SUCCESSFUL; |
| 164 | } |
| 165 | |
| 166 | static int psycho_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn, |
| 167 | int where, int size, u32 value) |
| 168 | { |
| 169 | struct pci_pbm_info *pbm = bus_dev->sysdata; |
| 170 | unsigned char bus = bus_dev->number; |
| 171 | u32 *addr; |
| 172 | |
| 173 | addr = psycho_pci_config_mkaddr(pbm, bus, devfn, where); |
| 174 | if (!addr) |
| 175 | return PCIBIOS_SUCCESSFUL; |
| 176 | |
| 177 | if (psycho_out_of_range(pbm, bus, devfn)) |
| 178 | return PCIBIOS_SUCCESSFUL; |
| 179 | |
| 180 | switch (size) { |
| 181 | case 1: |
| 182 | pci_config_write8((u8 *)addr, value); |
| 183 | break; |
| 184 | |
| 185 | case 2: |
| 186 | if (where & 0x01) { |
| 187 | printk("pci_write_config_word: misaligned reg [%x]\n", |
| 188 | where); |
| 189 | return PCIBIOS_SUCCESSFUL; |
| 190 | } |
| 191 | pci_config_write16((u16 *)addr, value); |
| 192 | break; |
| 193 | |
| 194 | case 4: |
| 195 | if (where & 0x03) { |
| 196 | printk("pci_write_config_dword: misaligned reg [%x]\n", |
| 197 | where); |
| 198 | return PCIBIOS_SUCCESSFUL; |
| 199 | } |
| 200 | pci_config_write32(addr, value); |
| 201 | } |
| 202 | return PCIBIOS_SUCCESSFUL; |
| 203 | } |
| 204 | |
| 205 | static struct pci_ops psycho_ops = { |
| 206 | .read = psycho_read_pci_cfg, |
| 207 | .write = psycho_write_pci_cfg, |
| 208 | }; |
| 209 | |
| 210 | /* PSYCHO interrupt mapping support. */ |
| 211 | #define PSYCHO_IMAP_A_SLOT0 0x0c00UL |
| 212 | #define PSYCHO_IMAP_B_SLOT0 0x0c20UL |
| 213 | static unsigned long psycho_pcislot_imap_offset(unsigned long ino) |
| 214 | { |
| 215 | unsigned int bus = (ino & 0x10) >> 4; |
| 216 | unsigned int slot = (ino & 0x0c) >> 2; |
| 217 | |
| 218 | if (bus == 0) |
| 219 | return PSYCHO_IMAP_A_SLOT0 + (slot * 8); |
| 220 | else |
| 221 | return PSYCHO_IMAP_B_SLOT0 + (slot * 8); |
| 222 | } |
| 223 | |
| 224 | #define PSYCHO_IMAP_SCSI 0x1000UL |
| 225 | #define PSYCHO_IMAP_ETH 0x1008UL |
| 226 | #define PSYCHO_IMAP_BPP 0x1010UL |
| 227 | #define PSYCHO_IMAP_AU_REC 0x1018UL |
| 228 | #define PSYCHO_IMAP_AU_PLAY 0x1020UL |
| 229 | #define PSYCHO_IMAP_PFAIL 0x1028UL |
| 230 | #define PSYCHO_IMAP_KMS 0x1030UL |
| 231 | #define PSYCHO_IMAP_FLPY 0x1038UL |
| 232 | #define PSYCHO_IMAP_SHW 0x1040UL |
| 233 | #define PSYCHO_IMAP_KBD 0x1048UL |
| 234 | #define PSYCHO_IMAP_MS 0x1050UL |
| 235 | #define PSYCHO_IMAP_SER 0x1058UL |
| 236 | #define PSYCHO_IMAP_TIM0 0x1060UL |
| 237 | #define PSYCHO_IMAP_TIM1 0x1068UL |
| 238 | #define PSYCHO_IMAP_UE 0x1070UL |
| 239 | #define PSYCHO_IMAP_CE 0x1078UL |
| 240 | #define PSYCHO_IMAP_A_ERR 0x1080UL |
| 241 | #define PSYCHO_IMAP_B_ERR 0x1088UL |
| 242 | #define PSYCHO_IMAP_PMGMT 0x1090UL |
| 243 | #define PSYCHO_IMAP_GFX 0x1098UL |
| 244 | #define PSYCHO_IMAP_EUPA 0x10a0UL |
| 245 | |
| 246 | static unsigned long __onboard_imap_off[] = { |
| 247 | /*0x20*/ PSYCHO_IMAP_SCSI, |
| 248 | /*0x21*/ PSYCHO_IMAP_ETH, |
| 249 | /*0x22*/ PSYCHO_IMAP_BPP, |
| 250 | /*0x23*/ PSYCHO_IMAP_AU_REC, |
| 251 | /*0x24*/ PSYCHO_IMAP_AU_PLAY, |
| 252 | /*0x25*/ PSYCHO_IMAP_PFAIL, |
| 253 | /*0x26*/ PSYCHO_IMAP_KMS, |
| 254 | /*0x27*/ PSYCHO_IMAP_FLPY, |
| 255 | /*0x28*/ PSYCHO_IMAP_SHW, |
| 256 | /*0x29*/ PSYCHO_IMAP_KBD, |
| 257 | /*0x2a*/ PSYCHO_IMAP_MS, |
| 258 | /*0x2b*/ PSYCHO_IMAP_SER, |
| 259 | /*0x2c*/ PSYCHO_IMAP_TIM0, |
| 260 | /*0x2d*/ PSYCHO_IMAP_TIM1, |
| 261 | /*0x2e*/ PSYCHO_IMAP_UE, |
| 262 | /*0x2f*/ PSYCHO_IMAP_CE, |
| 263 | /*0x30*/ PSYCHO_IMAP_A_ERR, |
| 264 | /*0x31*/ PSYCHO_IMAP_B_ERR, |
| 265 | /*0x32*/ PSYCHO_IMAP_PMGMT |
| 266 | }; |
| 267 | #define PSYCHO_ONBOARD_IRQ_BASE 0x20 |
| 268 | #define PSYCHO_ONBOARD_IRQ_LAST 0x32 |
| 269 | #define psycho_onboard_imap_offset(__ino) \ |
| 270 | __onboard_imap_off[(__ino) - PSYCHO_ONBOARD_IRQ_BASE] |
| 271 | |
| 272 | #define PSYCHO_ICLR_A_SLOT0 0x1400UL |
| 273 | #define PSYCHO_ICLR_SCSI 0x1800UL |
| 274 | |
| 275 | #define psycho_iclr_offset(ino) \ |
| 276 | ((ino & 0x20) ? (PSYCHO_ICLR_SCSI + (((ino) & 0x1f) << 3)) : \ |
| 277 | (PSYCHO_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3))) |
| 278 | |
| 279 | /* PCI PSYCHO INO number to Sparc PIL level. */ |
| 280 | static unsigned char psycho_pil_table[] = { |
| 281 | /*0x00*/0, 0, 0, 0, /* PCI A slot 0 Int A, B, C, D */ |
| 282 | /*0x04*/0, 0, 0, 0, /* PCI A slot 1 Int A, B, C, D */ |
| 283 | /*0x08*/0, 0, 0, 0, /* PCI A slot 2 Int A, B, C, D */ |
| 284 | /*0x0c*/0, 0, 0, 0, /* PCI A slot 3 Int A, B, C, D */ |
| 285 | /*0x10*/0, 0, 0, 0, /* PCI B slot 0 Int A, B, C, D */ |
| 286 | /*0x14*/0, 0, 0, 0, /* PCI B slot 1 Int A, B, C, D */ |
| 287 | /*0x18*/0, 0, 0, 0, /* PCI B slot 2 Int A, B, C, D */ |
| 288 | /*0x1c*/0, 0, 0, 0, /* PCI B slot 3 Int A, B, C, D */ |
| 289 | /*0x20*/4, /* SCSI */ |
| 290 | /*0x21*/5, /* Ethernet */ |
| 291 | /*0x22*/8, /* Parallel Port */ |
| 292 | /*0x23*/13, /* Audio Record */ |
| 293 | /*0x24*/14, /* Audio Playback */ |
| 294 | /*0x25*/15, /* PowerFail */ |
| 295 | /*0x26*/4, /* second SCSI */ |
| 296 | /*0x27*/11, /* Floppy */ |
| 297 | /*0x28*/4, /* Spare Hardware */ |
| 298 | /*0x29*/9, /* Keyboard */ |
| 299 | /*0x2a*/4, /* Mouse */ |
| 300 | /*0x2b*/12, /* Serial */ |
| 301 | /*0x2c*/10, /* Timer 0 */ |
| 302 | /*0x2d*/11, /* Timer 1 */ |
| 303 | /*0x2e*/15, /* Uncorrectable ECC */ |
| 304 | /*0x2f*/15, /* Correctable ECC */ |
| 305 | /*0x30*/15, /* PCI Bus A Error */ |
| 306 | /*0x31*/15, /* PCI Bus B Error */ |
| 307 | /*0x32*/15, /* Power Management */ |
| 308 | }; |
| 309 | |
| 310 | static int __init psycho_ino_to_pil(struct pci_dev *pdev, unsigned int ino) |
| 311 | { |
| 312 | int ret; |
| 313 | |
| 314 | ret = psycho_pil_table[ino]; |
| 315 | if (ret == 0 && pdev == NULL) { |
| 316 | ret = 4; |
| 317 | } else if (ret == 0) { |
| 318 | switch ((pdev->class >> 16) & 0xff) { |
| 319 | case PCI_BASE_CLASS_STORAGE: |
| 320 | ret = 4; |
| 321 | break; |
| 322 | |
| 323 | case PCI_BASE_CLASS_NETWORK: |
| 324 | ret = 6; |
| 325 | break; |
| 326 | |
| 327 | case PCI_BASE_CLASS_DISPLAY: |
| 328 | ret = 9; |
| 329 | break; |
| 330 | |
| 331 | case PCI_BASE_CLASS_MULTIMEDIA: |
| 332 | case PCI_BASE_CLASS_MEMORY: |
| 333 | case PCI_BASE_CLASS_BRIDGE: |
| 334 | case PCI_BASE_CLASS_SERIAL: |
| 335 | ret = 10; |
| 336 | break; |
| 337 | |
| 338 | default: |
| 339 | ret = 4; |
| 340 | break; |
| 341 | }; |
| 342 | } |
| 343 | |
| 344 | return ret; |
| 345 | } |
| 346 | |
| 347 | static unsigned int __init psycho_irq_build(struct pci_pbm_info *pbm, |
| 348 | struct pci_dev *pdev, |
| 349 | unsigned int ino) |
| 350 | { |
| 351 | struct ino_bucket *bucket; |
| 352 | unsigned long imap, iclr; |
| 353 | unsigned long imap_off, iclr_off; |
| 354 | int pil, inofixup = 0; |
| 355 | |
| 356 | ino &= PCI_IRQ_INO; |
| 357 | if (ino < PSYCHO_ONBOARD_IRQ_BASE) { |
| 358 | /* PCI slot */ |
| 359 | imap_off = psycho_pcislot_imap_offset(ino); |
| 360 | } else { |
| 361 | /* Onboard device */ |
| 362 | if (ino > PSYCHO_ONBOARD_IRQ_LAST) { |
| 363 | prom_printf("psycho_irq_build: Wacky INO [%x]\n", ino); |
| 364 | prom_halt(); |
| 365 | } |
| 366 | imap_off = psycho_onboard_imap_offset(ino); |
| 367 | } |
| 368 | |
| 369 | /* Now build the IRQ bucket. */ |
| 370 | pil = psycho_ino_to_pil(pdev, ino); |
| 371 | |
| 372 | if (PIL_RESERVED(pil)) |
| 373 | BUG(); |
| 374 | |
| 375 | imap = pbm->controller_regs + imap_off; |
| 376 | imap += 4; |
| 377 | |
| 378 | iclr_off = psycho_iclr_offset(ino); |
| 379 | iclr = pbm->controller_regs + iclr_off; |
| 380 | iclr += 4; |
| 381 | |
| 382 | if ((ino & 0x20) == 0) |
| 383 | inofixup = ino & 0x03; |
| 384 | |
| 385 | bucket = __bucket(build_irq(pil, inofixup, iclr, imap)); |
| 386 | bucket->flags |= IBF_PCI; |
| 387 | |
| 388 | return __irq(bucket); |
| 389 | } |
| 390 | |
| 391 | /* PSYCHO error handling support. */ |
| 392 | enum psycho_error_type { |
| 393 | UE_ERR, CE_ERR, PCI_ERR |
| 394 | }; |
| 395 | |
| 396 | /* Helper function of IOMMU error checking, which checks out |
| 397 | * the state of the streaming buffers. The IOMMU lock is |
| 398 | * held when this is called. |
| 399 | * |
| 400 | * For the PCI error case we know which PBM (and thus which |
| 401 | * streaming buffer) caused the error, but for the uncorrectable |
| 402 | * error case we do not. So we always check both streaming caches. |
| 403 | */ |
| 404 | #define PSYCHO_STRBUF_CONTROL_A 0x2800UL |
| 405 | #define PSYCHO_STRBUF_CONTROL_B 0x4800UL |
| 406 | #define PSYCHO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */ |
| 407 | #define PSYCHO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */ |
| 408 | #define PSYCHO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */ |
| 409 | #define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */ |
| 410 | #define PSYCHO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */ |
| 411 | #define PSYCHO_STRBUF_FLUSH_A 0x2808UL |
| 412 | #define PSYCHO_STRBUF_FLUSH_B 0x4808UL |
| 413 | #define PSYCHO_STRBUF_FSYNC_A 0x2810UL |
| 414 | #define PSYCHO_STRBUF_FSYNC_B 0x4810UL |
| 415 | #define PSYCHO_STC_DATA_A 0xb000UL |
| 416 | #define PSYCHO_STC_DATA_B 0xc000UL |
| 417 | #define PSYCHO_STC_ERR_A 0xb400UL |
| 418 | #define PSYCHO_STC_ERR_B 0xc400UL |
| 419 | #define PSYCHO_STCERR_WRITE 0x0000000000000002UL /* Write Error */ |
| 420 | #define PSYCHO_STCERR_READ 0x0000000000000001UL /* Read Error */ |
| 421 | #define PSYCHO_STC_TAG_A 0xb800UL |
| 422 | #define PSYCHO_STC_TAG_B 0xc800UL |
| 423 | #define PSYCHO_STCTAG_PPN 0x0fffffff00000000UL /* Physical Page Number */ |
| 424 | #define PSYCHO_STCTAG_VPN 0x00000000ffffe000UL /* Virtual Page Number */ |
| 425 | #define PSYCHO_STCTAG_VALID 0x0000000000000002UL /* Valid */ |
| 426 | #define PSYCHO_STCTAG_WRITE 0x0000000000000001UL /* Writable */ |
| 427 | #define PSYCHO_STC_LINE_A 0xb900UL |
| 428 | #define PSYCHO_STC_LINE_B 0xc900UL |
| 429 | #define PSYCHO_STCLINE_LINDX 0x0000000001e00000UL /* LRU Index */ |
| 430 | #define PSYCHO_STCLINE_SPTR 0x00000000001f8000UL /* Dirty Data Start Pointer */ |
| 431 | #define PSYCHO_STCLINE_LADDR 0x0000000000007f00UL /* Line Address */ |
| 432 | #define PSYCHO_STCLINE_EPTR 0x00000000000000fcUL /* Dirty Data End Pointer */ |
| 433 | #define PSYCHO_STCLINE_VALID 0x0000000000000002UL /* Valid */ |
| 434 | #define PSYCHO_STCLINE_FOFN 0x0000000000000001UL /* Fetch Outstanding / Flush Necessary */ |
| 435 | |
| 436 | static DEFINE_SPINLOCK(stc_buf_lock); |
| 437 | static unsigned long stc_error_buf[128]; |
| 438 | static unsigned long stc_tag_buf[16]; |
| 439 | static unsigned long stc_line_buf[16]; |
| 440 | |
| 441 | static void __psycho_check_one_stc(struct pci_controller_info *p, |
| 442 | struct pci_pbm_info *pbm, |
| 443 | int is_pbm_a) |
| 444 | { |
| 445 | struct pci_strbuf *strbuf = &pbm->stc; |
| 446 | unsigned long regbase = p->pbm_A.controller_regs; |
| 447 | unsigned long err_base, tag_base, line_base; |
| 448 | u64 control; |
| 449 | int i; |
| 450 | |
| 451 | if (is_pbm_a) { |
| 452 | err_base = regbase + PSYCHO_STC_ERR_A; |
| 453 | tag_base = regbase + PSYCHO_STC_TAG_A; |
| 454 | line_base = regbase + PSYCHO_STC_LINE_A; |
| 455 | } else { |
| 456 | err_base = regbase + PSYCHO_STC_ERR_B; |
| 457 | tag_base = regbase + PSYCHO_STC_TAG_B; |
| 458 | line_base = regbase + PSYCHO_STC_LINE_B; |
| 459 | } |
| 460 | |
| 461 | spin_lock(&stc_buf_lock); |
| 462 | |
| 463 | /* This is __REALLY__ dangerous. When we put the |
| 464 | * streaming buffer into diagnostic mode to probe |
| 465 | * it's tags and error status, we _must_ clear all |
| 466 | * of the line tag valid bits before re-enabling |
| 467 | * the streaming buffer. If any dirty data lives |
| 468 | * in the STC when we do this, we will end up |
| 469 | * invalidating it before it has a chance to reach |
| 470 | * main memory. |
| 471 | */ |
| 472 | control = psycho_read(strbuf->strbuf_control); |
| 473 | psycho_write(strbuf->strbuf_control, |
| 474 | (control | PSYCHO_STRBUF_CTRL_DENAB)); |
| 475 | for (i = 0; i < 128; i++) { |
| 476 | unsigned long val; |
| 477 | |
| 478 | val = psycho_read(err_base + (i * 8UL)); |
| 479 | psycho_write(err_base + (i * 8UL), 0UL); |
| 480 | stc_error_buf[i] = val; |
| 481 | } |
| 482 | for (i = 0; i < 16; i++) { |
| 483 | stc_tag_buf[i] = psycho_read(tag_base + (i * 8UL)); |
| 484 | stc_line_buf[i] = psycho_read(line_base + (i * 8UL)); |
| 485 | psycho_write(tag_base + (i * 8UL), 0UL); |
| 486 | psycho_write(line_base + (i * 8UL), 0UL); |
| 487 | } |
| 488 | |
| 489 | /* OK, state is logged, exit diagnostic mode. */ |
| 490 | psycho_write(strbuf->strbuf_control, control); |
| 491 | |
| 492 | for (i = 0; i < 16; i++) { |
| 493 | int j, saw_error, first, last; |
| 494 | |
| 495 | saw_error = 0; |
| 496 | first = i * 8; |
| 497 | last = first + 8; |
| 498 | for (j = first; j < last; j++) { |
| 499 | unsigned long errval = stc_error_buf[j]; |
| 500 | if (errval != 0) { |
| 501 | saw_error++; |
| 502 | printk("PSYCHO%d(PBM%c): STC_ERR(%d)[wr(%d)rd(%d)]\n", |
| 503 | p->index, |
| 504 | (is_pbm_a ? 'A' : 'B'), |
| 505 | j, |
| 506 | (errval & PSYCHO_STCERR_WRITE) ? 1 : 0, |
| 507 | (errval & PSYCHO_STCERR_READ) ? 1 : 0); |
| 508 | } |
| 509 | } |
| 510 | if (saw_error != 0) { |
| 511 | unsigned long tagval = stc_tag_buf[i]; |
| 512 | unsigned long lineval = stc_line_buf[i]; |
| 513 | printk("PSYCHO%d(PBM%c): STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)W(%d)]\n", |
| 514 | p->index, |
| 515 | (is_pbm_a ? 'A' : 'B'), |
| 516 | i, |
| 517 | ((tagval & PSYCHO_STCTAG_PPN) >> 19UL), |
| 518 | (tagval & PSYCHO_STCTAG_VPN), |
| 519 | ((tagval & PSYCHO_STCTAG_VALID) ? 1 : 0), |
| 520 | ((tagval & PSYCHO_STCTAG_WRITE) ? 1 : 0)); |
| 521 | printk("PSYCHO%d(PBM%c): STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)" |
| 522 | "V(%d)FOFN(%d)]\n", |
| 523 | p->index, |
| 524 | (is_pbm_a ? 'A' : 'B'), |
| 525 | i, |
| 526 | ((lineval & PSYCHO_STCLINE_LINDX) >> 21UL), |
| 527 | ((lineval & PSYCHO_STCLINE_SPTR) >> 15UL), |
| 528 | ((lineval & PSYCHO_STCLINE_LADDR) >> 8UL), |
| 529 | ((lineval & PSYCHO_STCLINE_EPTR) >> 2UL), |
| 530 | ((lineval & PSYCHO_STCLINE_VALID) ? 1 : 0), |
| 531 | ((lineval & PSYCHO_STCLINE_FOFN) ? 1 : 0)); |
| 532 | } |
| 533 | } |
| 534 | |
| 535 | spin_unlock(&stc_buf_lock); |
| 536 | } |
| 537 | |
| 538 | static void __psycho_check_stc_error(struct pci_controller_info *p, |
| 539 | unsigned long afsr, |
| 540 | unsigned long afar, |
| 541 | enum psycho_error_type type) |
| 542 | { |
| 543 | struct pci_pbm_info *pbm; |
| 544 | |
| 545 | pbm = &p->pbm_A; |
| 546 | if (pbm->stc.strbuf_enabled) |
| 547 | __psycho_check_one_stc(p, pbm, 1); |
| 548 | |
| 549 | pbm = &p->pbm_B; |
| 550 | if (pbm->stc.strbuf_enabled) |
| 551 | __psycho_check_one_stc(p, pbm, 0); |
| 552 | } |
| 553 | |
| 554 | /* When an Uncorrectable Error or a PCI Error happens, we |
| 555 | * interrogate the IOMMU state to see if it is the cause. |
| 556 | */ |
| 557 | #define PSYCHO_IOMMU_CONTROL 0x0200UL |
| 558 | #define PSYCHO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */ |
| 559 | #define PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */ |
| 560 | #define PSYCHO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */ |
| 561 | #define PSYCHO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */ |
| 562 | #define PSYCHO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */ |
| 563 | #define PSYCHO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */ |
| 564 | #define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */ |
| 565 | #define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */ |
| 566 | #define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */ |
| 567 | #define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */ |
| 568 | #define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */ |
| 569 | #define PSYCHO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */ |
| 570 | #define PSYCHO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */ |
| 571 | #define PSYCHO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */ |
| 572 | #define PSYCHO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */ |
| 573 | #define PSYCHO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */ |
| 574 | #define PSYCHO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */ |
| 575 | #define PSYCHO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */ |
| 576 | #define PSYCHO_IOMMU_TSBBASE 0x0208UL |
| 577 | #define PSYCHO_IOMMU_FLUSH 0x0210UL |
| 578 | #define PSYCHO_IOMMU_TAG 0xa580UL |
| 579 | #define PSYCHO_IOMMU_TAG_ERRSTS (0x3UL << 23UL) |
| 580 | #define PSYCHO_IOMMU_TAG_ERR (0x1UL << 22UL) |
| 581 | #define PSYCHO_IOMMU_TAG_WRITE (0x1UL << 21UL) |
| 582 | #define PSYCHO_IOMMU_TAG_STREAM (0x1UL << 20UL) |
| 583 | #define PSYCHO_IOMMU_TAG_SIZE (0x1UL << 19UL) |
| 584 | #define PSYCHO_IOMMU_TAG_VPAGE 0x7ffffUL |
| 585 | #define PSYCHO_IOMMU_DATA 0xa600UL |
| 586 | #define PSYCHO_IOMMU_DATA_VALID (1UL << 30UL) |
| 587 | #define PSYCHO_IOMMU_DATA_CACHE (1UL << 28UL) |
| 588 | #define PSYCHO_IOMMU_DATA_PPAGE 0xfffffffUL |
| 589 | static void psycho_check_iommu_error(struct pci_controller_info *p, |
| 590 | unsigned long afsr, |
| 591 | unsigned long afar, |
| 592 | enum psycho_error_type type) |
| 593 | { |
| 594 | struct pci_iommu *iommu = p->pbm_A.iommu; |
| 595 | unsigned long iommu_tag[16]; |
| 596 | unsigned long iommu_data[16]; |
| 597 | unsigned long flags; |
| 598 | u64 control; |
| 599 | int i; |
| 600 | |
| 601 | spin_lock_irqsave(&iommu->lock, flags); |
| 602 | control = psycho_read(iommu->iommu_control); |
| 603 | if (control & PSYCHO_IOMMU_CTRL_XLTEERR) { |
| 604 | char *type_string; |
| 605 | |
| 606 | /* Clear the error encountered bit. */ |
| 607 | control &= ~PSYCHO_IOMMU_CTRL_XLTEERR; |
| 608 | psycho_write(iommu->iommu_control, control); |
| 609 | |
| 610 | switch((control & PSYCHO_IOMMU_CTRL_XLTESTAT) >> 25UL) { |
| 611 | case 0: |
| 612 | type_string = "Protection Error"; |
| 613 | break; |
| 614 | case 1: |
| 615 | type_string = "Invalid Error"; |
| 616 | break; |
| 617 | case 2: |
| 618 | type_string = "TimeOut Error"; |
| 619 | break; |
| 620 | case 3: |
| 621 | default: |
| 622 | type_string = "ECC Error"; |
| 623 | break; |
| 624 | }; |
| 625 | printk("PSYCHO%d: IOMMU Error, type[%s]\n", |
| 626 | p->index, type_string); |
| 627 | |
| 628 | /* Put the IOMMU into diagnostic mode and probe |
| 629 | * it's TLB for entries with error status. |
| 630 | * |
| 631 | * It is very possible for another DVMA to occur |
| 632 | * while we do this probe, and corrupt the system |
| 633 | * further. But we are so screwed at this point |
| 634 | * that we are likely to crash hard anyways, so |
| 635 | * get as much diagnostic information to the |
| 636 | * console as we can. |
| 637 | */ |
| 638 | psycho_write(iommu->iommu_control, |
| 639 | control | PSYCHO_IOMMU_CTRL_DENAB); |
| 640 | for (i = 0; i < 16; i++) { |
| 641 | unsigned long base = p->pbm_A.controller_regs; |
| 642 | |
| 643 | iommu_tag[i] = |
| 644 | psycho_read(base + PSYCHO_IOMMU_TAG + (i * 8UL)); |
| 645 | iommu_data[i] = |
| 646 | psycho_read(base + PSYCHO_IOMMU_DATA + (i * 8UL)); |
| 647 | |
| 648 | /* Now clear out the entry. */ |
| 649 | psycho_write(base + PSYCHO_IOMMU_TAG + (i * 8UL), 0); |
| 650 | psycho_write(base + PSYCHO_IOMMU_DATA + (i * 8UL), 0); |
| 651 | } |
| 652 | |
| 653 | /* Leave diagnostic mode. */ |
| 654 | psycho_write(iommu->iommu_control, control); |
| 655 | |
| 656 | for (i = 0; i < 16; i++) { |
| 657 | unsigned long tag, data; |
| 658 | |
| 659 | tag = iommu_tag[i]; |
| 660 | if (!(tag & PSYCHO_IOMMU_TAG_ERR)) |
| 661 | continue; |
| 662 | |
| 663 | data = iommu_data[i]; |
| 664 | switch((tag & PSYCHO_IOMMU_TAG_ERRSTS) >> 23UL) { |
| 665 | case 0: |
| 666 | type_string = "Protection Error"; |
| 667 | break; |
| 668 | case 1: |
| 669 | type_string = "Invalid Error"; |
| 670 | break; |
| 671 | case 2: |
| 672 | type_string = "TimeOut Error"; |
| 673 | break; |
| 674 | case 3: |
| 675 | default: |
| 676 | type_string = "ECC Error"; |
| 677 | break; |
| 678 | }; |
| 679 | printk("PSYCHO%d: IOMMU TAG(%d)[error(%s) wr(%d) str(%d) sz(%dK) vpg(%08lx)]\n", |
| 680 | p->index, i, type_string, |
| 681 | ((tag & PSYCHO_IOMMU_TAG_WRITE) ? 1 : 0), |
| 682 | ((tag & PSYCHO_IOMMU_TAG_STREAM) ? 1 : 0), |
| 683 | ((tag & PSYCHO_IOMMU_TAG_SIZE) ? 64 : 8), |
| 684 | (tag & PSYCHO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT); |
| 685 | printk("PSYCHO%d: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n", |
| 686 | p->index, i, |
| 687 | ((data & PSYCHO_IOMMU_DATA_VALID) ? 1 : 0), |
| 688 | ((data & PSYCHO_IOMMU_DATA_CACHE) ? 1 : 0), |
| 689 | (data & PSYCHO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT); |
| 690 | } |
| 691 | } |
| 692 | __psycho_check_stc_error(p, afsr, afar, type); |
| 693 | spin_unlock_irqrestore(&iommu->lock, flags); |
| 694 | } |
| 695 | |
| 696 | /* Uncorrectable Errors. Cause of the error and the address are |
| 697 | * recorded in the UE_AFSR and UE_AFAR of PSYCHO. They are errors |
| 698 | * relating to UPA interface transactions. |
| 699 | */ |
| 700 | #define PSYCHO_UE_AFSR 0x0030UL |
| 701 | #define PSYCHO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */ |
| 702 | #define PSYCHO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */ |
| 703 | #define PSYCHO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */ |
| 704 | #define PSYCHO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */ |
| 705 | #define PSYCHO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */ |
| 706 | #define PSYCHO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/ |
| 707 | #define PSYCHO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */ |
| 708 | #define PSYCHO_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */ |
| 709 | #define PSYCHO_UEAFSR_DOFF 0x00000000e0000000UL /* Doubleword Offset */ |
| 710 | #define PSYCHO_UEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */ |
| 711 | #define PSYCHO_UEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */ |
| 712 | #define PSYCHO_UEAFSR_RESV2 0x00000000007fffffUL /* Reserved */ |
| 713 | #define PSYCHO_UE_AFAR 0x0038UL |
| 714 | |
| 715 | static irqreturn_t psycho_ue_intr(int irq, void *dev_id, struct pt_regs *regs) |
| 716 | { |
| 717 | struct pci_controller_info *p = dev_id; |
| 718 | unsigned long afsr_reg = p->pbm_A.controller_regs + PSYCHO_UE_AFSR; |
| 719 | unsigned long afar_reg = p->pbm_A.controller_regs + PSYCHO_UE_AFAR; |
| 720 | unsigned long afsr, afar, error_bits; |
| 721 | int reported; |
| 722 | |
| 723 | /* Latch uncorrectable error status. */ |
| 724 | afar = psycho_read(afar_reg); |
| 725 | afsr = psycho_read(afsr_reg); |
| 726 | |
| 727 | /* Clear the primary/secondary error status bits. */ |
| 728 | error_bits = afsr & |
| 729 | (PSYCHO_UEAFSR_PPIO | PSYCHO_UEAFSR_PDRD | PSYCHO_UEAFSR_PDWR | |
| 730 | PSYCHO_UEAFSR_SPIO | PSYCHO_UEAFSR_SDRD | PSYCHO_UEAFSR_SDWR); |
| 731 | if (!error_bits) |
| 732 | return IRQ_NONE; |
| 733 | psycho_write(afsr_reg, error_bits); |
| 734 | |
| 735 | /* Log the error. */ |
| 736 | printk("PSYCHO%d: Uncorrectable Error, primary error type[%s]\n", |
| 737 | p->index, |
| 738 | (((error_bits & PSYCHO_UEAFSR_PPIO) ? |
| 739 | "PIO" : |
| 740 | ((error_bits & PSYCHO_UEAFSR_PDRD) ? |
| 741 | "DMA Read" : |
| 742 | ((error_bits & PSYCHO_UEAFSR_PDWR) ? |
| 743 | "DMA Write" : "???"))))); |
| 744 | printk("PSYCHO%d: bytemask[%04lx] dword_offset[%lx] UPA_MID[%02lx] was_block(%d)\n", |
| 745 | p->index, |
| 746 | (afsr & PSYCHO_UEAFSR_BMSK) >> 32UL, |
| 747 | (afsr & PSYCHO_UEAFSR_DOFF) >> 29UL, |
| 748 | (afsr & PSYCHO_UEAFSR_MID) >> 24UL, |
| 749 | ((afsr & PSYCHO_UEAFSR_BLK) ? 1 : 0)); |
| 750 | printk("PSYCHO%d: UE AFAR [%016lx]\n", p->index, afar); |
| 751 | printk("PSYCHO%d: UE Secondary errors [", p->index); |
| 752 | reported = 0; |
| 753 | if (afsr & PSYCHO_UEAFSR_SPIO) { |
| 754 | reported++; |
| 755 | printk("(PIO)"); |
| 756 | } |
| 757 | if (afsr & PSYCHO_UEAFSR_SDRD) { |
| 758 | reported++; |
| 759 | printk("(DMA Read)"); |
| 760 | } |
| 761 | if (afsr & PSYCHO_UEAFSR_SDWR) { |
| 762 | reported++; |
| 763 | printk("(DMA Write)"); |
| 764 | } |
| 765 | if (!reported) |
| 766 | printk("(none)"); |
| 767 | printk("]\n"); |
| 768 | |
| 769 | /* Interrogate IOMMU for error status. */ |
| 770 | psycho_check_iommu_error(p, afsr, afar, UE_ERR); |
| 771 | |
| 772 | return IRQ_HANDLED; |
| 773 | } |
| 774 | |
| 775 | /* Correctable Errors. */ |
| 776 | #define PSYCHO_CE_AFSR 0x0040UL |
| 777 | #define PSYCHO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */ |
| 778 | #define PSYCHO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */ |
| 779 | #define PSYCHO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */ |
| 780 | #define PSYCHO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */ |
| 781 | #define PSYCHO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */ |
| 782 | #define PSYCHO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/ |
| 783 | #define PSYCHO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */ |
| 784 | #define PSYCHO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */ |
| 785 | #define PSYCHO_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */ |
| 786 | #define PSYCHO_CEAFSR_DOFF 0x00000000e0000000UL /* Double Offset */ |
| 787 | #define PSYCHO_CEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */ |
| 788 | #define PSYCHO_CEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */ |
| 789 | #define PSYCHO_CEAFSR_RESV2 0x00000000007fffffUL /* Reserved */ |
| 790 | #define PSYCHO_CE_AFAR 0x0040UL |
| 791 | |
| 792 | static irqreturn_t psycho_ce_intr(int irq, void *dev_id, struct pt_regs *regs) |
| 793 | { |
| 794 | struct pci_controller_info *p = dev_id; |
| 795 | unsigned long afsr_reg = p->pbm_A.controller_regs + PSYCHO_CE_AFSR; |
| 796 | unsigned long afar_reg = p->pbm_A.controller_regs + PSYCHO_CE_AFAR; |
| 797 | unsigned long afsr, afar, error_bits; |
| 798 | int reported; |
| 799 | |
| 800 | /* Latch error status. */ |
| 801 | afar = psycho_read(afar_reg); |
| 802 | afsr = psycho_read(afsr_reg); |
| 803 | |
| 804 | /* Clear primary/secondary error status bits. */ |
| 805 | error_bits = afsr & |
| 806 | (PSYCHO_CEAFSR_PPIO | PSYCHO_CEAFSR_PDRD | PSYCHO_CEAFSR_PDWR | |
| 807 | PSYCHO_CEAFSR_SPIO | PSYCHO_CEAFSR_SDRD | PSYCHO_CEAFSR_SDWR); |
| 808 | if (!error_bits) |
| 809 | return IRQ_NONE; |
| 810 | psycho_write(afsr_reg, error_bits); |
| 811 | |
| 812 | /* Log the error. */ |
| 813 | printk("PSYCHO%d: Correctable Error, primary error type[%s]\n", |
| 814 | p->index, |
| 815 | (((error_bits & PSYCHO_CEAFSR_PPIO) ? |
| 816 | "PIO" : |
| 817 | ((error_bits & PSYCHO_CEAFSR_PDRD) ? |
| 818 | "DMA Read" : |
| 819 | ((error_bits & PSYCHO_CEAFSR_PDWR) ? |
| 820 | "DMA Write" : "???"))))); |
| 821 | |
| 822 | /* XXX Use syndrome and afar to print out module string just like |
| 823 | * XXX UDB CE trap handler does... -DaveM |
| 824 | */ |
| 825 | printk("PSYCHO%d: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] " |
| 826 | "UPA_MID[%02lx] was_block(%d)\n", |
| 827 | p->index, |
| 828 | (afsr & PSYCHO_CEAFSR_ESYND) >> 48UL, |
| 829 | (afsr & PSYCHO_CEAFSR_BMSK) >> 32UL, |
| 830 | (afsr & PSYCHO_CEAFSR_DOFF) >> 29UL, |
| 831 | (afsr & PSYCHO_CEAFSR_MID) >> 24UL, |
| 832 | ((afsr & PSYCHO_CEAFSR_BLK) ? 1 : 0)); |
| 833 | printk("PSYCHO%d: CE AFAR [%016lx]\n", p->index, afar); |
| 834 | printk("PSYCHO%d: CE Secondary errors [", p->index); |
| 835 | reported = 0; |
| 836 | if (afsr & PSYCHO_CEAFSR_SPIO) { |
| 837 | reported++; |
| 838 | printk("(PIO)"); |
| 839 | } |
| 840 | if (afsr & PSYCHO_CEAFSR_SDRD) { |
| 841 | reported++; |
| 842 | printk("(DMA Read)"); |
| 843 | } |
| 844 | if (afsr & PSYCHO_CEAFSR_SDWR) { |
| 845 | reported++; |
| 846 | printk("(DMA Write)"); |
| 847 | } |
| 848 | if (!reported) |
| 849 | printk("(none)"); |
| 850 | printk("]\n"); |
| 851 | |
| 852 | return IRQ_HANDLED; |
| 853 | } |
| 854 | |
| 855 | /* PCI Errors. They are signalled by the PCI bus module since they |
| 856 | * are associated with a specific bus segment. |
| 857 | */ |
| 858 | #define PSYCHO_PCI_AFSR_A 0x2010UL |
| 859 | #define PSYCHO_PCI_AFSR_B 0x4010UL |
| 860 | #define PSYCHO_PCIAFSR_PMA 0x8000000000000000UL /* Primary Master Abort Error */ |
| 861 | #define PSYCHO_PCIAFSR_PTA 0x4000000000000000UL /* Primary Target Abort Error */ |
| 862 | #define PSYCHO_PCIAFSR_PRTRY 0x2000000000000000UL /* Primary Excessive Retries */ |
| 863 | #define PSYCHO_PCIAFSR_PPERR 0x1000000000000000UL /* Primary Parity Error */ |
| 864 | #define PSYCHO_PCIAFSR_SMA 0x0800000000000000UL /* Secondary Master Abort Error */ |
| 865 | #define PSYCHO_PCIAFSR_STA 0x0400000000000000UL /* Secondary Target Abort Error */ |
| 866 | #define PSYCHO_PCIAFSR_SRTRY 0x0200000000000000UL /* Secondary Excessive Retries */ |
| 867 | #define PSYCHO_PCIAFSR_SPERR 0x0100000000000000UL /* Secondary Parity Error */ |
| 868 | #define PSYCHO_PCIAFSR_RESV1 0x00ff000000000000UL /* Reserved */ |
| 869 | #define PSYCHO_PCIAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */ |
| 870 | #define PSYCHO_PCIAFSR_BLK 0x0000000080000000UL /* Trans was block operation */ |
| 871 | #define PSYCHO_PCIAFSR_RESV2 0x0000000040000000UL /* Reserved */ |
| 872 | #define PSYCHO_PCIAFSR_MID 0x000000003e000000UL /* MID causing the error */ |
| 873 | #define PSYCHO_PCIAFSR_RESV3 0x0000000001ffffffUL /* Reserved */ |
| 874 | #define PSYCHO_PCI_AFAR_A 0x2018UL |
| 875 | #define PSYCHO_PCI_AFAR_B 0x4018UL |
| 876 | |
| 877 | static irqreturn_t psycho_pcierr_intr_other(struct pci_pbm_info *pbm, int is_pbm_a) |
| 878 | { |
| 879 | unsigned long csr_reg, csr, csr_error_bits; |
| 880 | irqreturn_t ret = IRQ_NONE; |
| 881 | u16 stat; |
| 882 | |
| 883 | if (is_pbm_a) { |
| 884 | csr_reg = pbm->controller_regs + PSYCHO_PCIA_CTRL; |
| 885 | } else { |
| 886 | csr_reg = pbm->controller_regs + PSYCHO_PCIB_CTRL; |
| 887 | } |
| 888 | csr = psycho_read(csr_reg); |
| 889 | csr_error_bits = |
| 890 | csr & (PSYCHO_PCICTRL_SBH_ERR | PSYCHO_PCICTRL_SERR); |
| 891 | if (csr_error_bits) { |
| 892 | /* Clear the errors. */ |
| 893 | psycho_write(csr_reg, csr); |
| 894 | |
| 895 | /* Log 'em. */ |
| 896 | if (csr_error_bits & PSYCHO_PCICTRL_SBH_ERR) |
| 897 | printk("%s: PCI streaming byte hole error asserted.\n", |
| 898 | pbm->name); |
| 899 | if (csr_error_bits & PSYCHO_PCICTRL_SERR) |
| 900 | printk("%s: PCI SERR signal asserted.\n", pbm->name); |
| 901 | ret = IRQ_HANDLED; |
| 902 | } |
| 903 | pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat); |
| 904 | if (stat & (PCI_STATUS_PARITY | |
| 905 | PCI_STATUS_SIG_TARGET_ABORT | |
| 906 | PCI_STATUS_REC_TARGET_ABORT | |
| 907 | PCI_STATUS_REC_MASTER_ABORT | |
| 908 | PCI_STATUS_SIG_SYSTEM_ERROR)) { |
| 909 | printk("%s: PCI bus error, PCI_STATUS[%04x]\n", |
| 910 | pbm->name, stat); |
| 911 | pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff); |
| 912 | ret = IRQ_HANDLED; |
| 913 | } |
| 914 | return ret; |
| 915 | } |
| 916 | |
| 917 | static irqreturn_t psycho_pcierr_intr(int irq, void *dev_id, struct pt_regs *regs) |
| 918 | { |
| 919 | struct pci_pbm_info *pbm = dev_id; |
| 920 | struct pci_controller_info *p = pbm->parent; |
| 921 | unsigned long afsr_reg, afar_reg; |
| 922 | unsigned long afsr, afar, error_bits; |
| 923 | int is_pbm_a, reported; |
| 924 | |
| 925 | is_pbm_a = (pbm == &pbm->parent->pbm_A); |
| 926 | if (is_pbm_a) { |
| 927 | afsr_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFSR_A; |
| 928 | afar_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFAR_A; |
| 929 | } else { |
| 930 | afsr_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFSR_B; |
| 931 | afar_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFAR_B; |
| 932 | } |
| 933 | |
| 934 | /* Latch error status. */ |
| 935 | afar = psycho_read(afar_reg); |
| 936 | afsr = psycho_read(afsr_reg); |
| 937 | |
| 938 | /* Clear primary/secondary error status bits. */ |
| 939 | error_bits = afsr & |
| 940 | (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_PTA | |
| 941 | PSYCHO_PCIAFSR_PRTRY | PSYCHO_PCIAFSR_PPERR | |
| 942 | PSYCHO_PCIAFSR_SMA | PSYCHO_PCIAFSR_STA | |
| 943 | PSYCHO_PCIAFSR_SRTRY | PSYCHO_PCIAFSR_SPERR); |
| 944 | if (!error_bits) |
| 945 | return psycho_pcierr_intr_other(pbm, is_pbm_a); |
| 946 | psycho_write(afsr_reg, error_bits); |
| 947 | |
| 948 | /* Log the error. */ |
| 949 | printk("PSYCHO%d(PBM%c): PCI Error, primary error type[%s]\n", |
| 950 | p->index, (is_pbm_a ? 'A' : 'B'), |
| 951 | (((error_bits & PSYCHO_PCIAFSR_PMA) ? |
| 952 | "Master Abort" : |
| 953 | ((error_bits & PSYCHO_PCIAFSR_PTA) ? |
| 954 | "Target Abort" : |
| 955 | ((error_bits & PSYCHO_PCIAFSR_PRTRY) ? |
| 956 | "Excessive Retries" : |
| 957 | ((error_bits & PSYCHO_PCIAFSR_PPERR) ? |
| 958 | "Parity Error" : "???")))))); |
| 959 | printk("PSYCHO%d(PBM%c): bytemask[%04lx] UPA_MID[%02lx] was_block(%d)\n", |
| 960 | p->index, (is_pbm_a ? 'A' : 'B'), |
| 961 | (afsr & PSYCHO_PCIAFSR_BMSK) >> 32UL, |
| 962 | (afsr & PSYCHO_PCIAFSR_MID) >> 25UL, |
| 963 | (afsr & PSYCHO_PCIAFSR_BLK) ? 1 : 0); |
| 964 | printk("PSYCHO%d(PBM%c): PCI AFAR [%016lx]\n", |
| 965 | p->index, (is_pbm_a ? 'A' : 'B'), afar); |
| 966 | printk("PSYCHO%d(PBM%c): PCI Secondary errors [", |
| 967 | p->index, (is_pbm_a ? 'A' : 'B')); |
| 968 | reported = 0; |
| 969 | if (afsr & PSYCHO_PCIAFSR_SMA) { |
| 970 | reported++; |
| 971 | printk("(Master Abort)"); |
| 972 | } |
| 973 | if (afsr & PSYCHO_PCIAFSR_STA) { |
| 974 | reported++; |
| 975 | printk("(Target Abort)"); |
| 976 | } |
| 977 | if (afsr & PSYCHO_PCIAFSR_SRTRY) { |
| 978 | reported++; |
| 979 | printk("(Excessive Retries)"); |
| 980 | } |
| 981 | if (afsr & PSYCHO_PCIAFSR_SPERR) { |
| 982 | reported++; |
| 983 | printk("(Parity Error)"); |
| 984 | } |
| 985 | if (!reported) |
| 986 | printk("(none)"); |
| 987 | printk("]\n"); |
| 988 | |
| 989 | /* For the error types shown, scan PBM's PCI bus for devices |
| 990 | * which have logged that error type. |
| 991 | */ |
| 992 | |
| 993 | /* If we see a Target Abort, this could be the result of an |
| 994 | * IOMMU translation error of some sort. It is extremely |
| 995 | * useful to log this information as usually it indicates |
| 996 | * a bug in the IOMMU support code or a PCI device driver. |
| 997 | */ |
| 998 | if (error_bits & (PSYCHO_PCIAFSR_PTA | PSYCHO_PCIAFSR_STA)) { |
| 999 | psycho_check_iommu_error(p, afsr, afar, PCI_ERR); |
| 1000 | pci_scan_for_target_abort(p, pbm, pbm->pci_bus); |
| 1001 | } |
| 1002 | if (error_bits & (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_SMA)) |
| 1003 | pci_scan_for_master_abort(p, pbm, pbm->pci_bus); |
| 1004 | |
| 1005 | /* For excessive retries, PSYCHO/PBM will abort the device |
| 1006 | * and there is no way to specifically check for excessive |
| 1007 | * retries in the config space status registers. So what |
| 1008 | * we hope is that we'll catch it via the master/target |
| 1009 | * abort events. |
| 1010 | */ |
| 1011 | |
| 1012 | if (error_bits & (PSYCHO_PCIAFSR_PPERR | PSYCHO_PCIAFSR_SPERR)) |
| 1013 | pci_scan_for_parity_error(p, pbm, pbm->pci_bus); |
| 1014 | |
| 1015 | return IRQ_HANDLED; |
| 1016 | } |
| 1017 | |
| 1018 | /* XXX What about PowerFail/PowerManagement??? -DaveM */ |
| 1019 | #define PSYCHO_ECC_CTRL 0x0020 |
| 1020 | #define PSYCHO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */ |
| 1021 | #define PSYCHO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */ |
| 1022 | #define PSYCHO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */ |
| 1023 | #define PSYCHO_UE_INO 0x2e |
| 1024 | #define PSYCHO_CE_INO 0x2f |
| 1025 | #define PSYCHO_PCIERR_A_INO 0x30 |
| 1026 | #define PSYCHO_PCIERR_B_INO 0x31 |
| 1027 | static void __init psycho_register_error_handlers(struct pci_controller_info *p) |
| 1028 | { |
| 1029 | struct pci_pbm_info *pbm = &p->pbm_A; /* arbitrary */ |
| 1030 | unsigned long base = p->pbm_A.controller_regs; |
| 1031 | unsigned int irq, portid = pbm->portid; |
| 1032 | u64 tmp; |
| 1033 | |
| 1034 | /* Build IRQs and register handlers. */ |
| 1035 | irq = psycho_irq_build(pbm, NULL, (portid << 6) | PSYCHO_UE_INO); |
| 1036 | if (request_irq(irq, psycho_ue_intr, |
| 1037 | SA_SHIRQ, "PSYCHO UE", p) < 0) { |
| 1038 | prom_printf("PSYCHO%d: Cannot register UE interrupt.\n", |
| 1039 | p->index); |
| 1040 | prom_halt(); |
| 1041 | } |
| 1042 | |
| 1043 | irq = psycho_irq_build(pbm, NULL, (portid << 6) | PSYCHO_CE_INO); |
| 1044 | if (request_irq(irq, psycho_ce_intr, |
| 1045 | SA_SHIRQ, "PSYCHO CE", p) < 0) { |
| 1046 | prom_printf("PSYCHO%d: Cannot register CE interrupt.\n", |
| 1047 | p->index); |
| 1048 | prom_halt(); |
| 1049 | } |
| 1050 | |
| 1051 | pbm = &p->pbm_A; |
| 1052 | irq = psycho_irq_build(pbm, NULL, (portid << 6) | PSYCHO_PCIERR_A_INO); |
| 1053 | if (request_irq(irq, psycho_pcierr_intr, |
| 1054 | SA_SHIRQ, "PSYCHO PCIERR", &p->pbm_A) < 0) { |
| 1055 | prom_printf("PSYCHO%d(PBMA): Cannot register PciERR interrupt.\n", |
| 1056 | p->index); |
| 1057 | prom_halt(); |
| 1058 | } |
| 1059 | |
| 1060 | pbm = &p->pbm_B; |
| 1061 | irq = psycho_irq_build(pbm, NULL, (portid << 6) | PSYCHO_PCIERR_B_INO); |
| 1062 | if (request_irq(irq, psycho_pcierr_intr, |
| 1063 | SA_SHIRQ, "PSYCHO PCIERR", &p->pbm_B) < 0) { |
| 1064 | prom_printf("PSYCHO%d(PBMB): Cannot register PciERR interrupt.\n", |
| 1065 | p->index); |
| 1066 | prom_halt(); |
| 1067 | } |
| 1068 | |
| 1069 | /* Enable UE and CE interrupts for controller. */ |
| 1070 | psycho_write(base + PSYCHO_ECC_CTRL, |
| 1071 | (PSYCHO_ECCCTRL_EE | |
| 1072 | PSYCHO_ECCCTRL_UE | |
| 1073 | PSYCHO_ECCCTRL_CE)); |
| 1074 | |
| 1075 | /* Enable PCI Error interrupts and clear error |
| 1076 | * bits for each PBM. |
| 1077 | */ |
| 1078 | tmp = psycho_read(base + PSYCHO_PCIA_CTRL); |
| 1079 | tmp |= (PSYCHO_PCICTRL_SERR | |
| 1080 | PSYCHO_PCICTRL_SBH_ERR | |
| 1081 | PSYCHO_PCICTRL_EEN); |
| 1082 | tmp &= ~(PSYCHO_PCICTRL_SBH_INT); |
| 1083 | psycho_write(base + PSYCHO_PCIA_CTRL, tmp); |
| 1084 | |
| 1085 | tmp = psycho_read(base + PSYCHO_PCIB_CTRL); |
| 1086 | tmp |= (PSYCHO_PCICTRL_SERR | |
| 1087 | PSYCHO_PCICTRL_SBH_ERR | |
| 1088 | PSYCHO_PCICTRL_EEN); |
| 1089 | tmp &= ~(PSYCHO_PCICTRL_SBH_INT); |
| 1090 | psycho_write(base + PSYCHO_PCIB_CTRL, tmp); |
| 1091 | } |
| 1092 | |
| 1093 | /* PSYCHO boot time probing and initialization. */ |
| 1094 | static void __init psycho_resource_adjust(struct pci_dev *pdev, |
| 1095 | struct resource *res, |
| 1096 | struct resource *root) |
| 1097 | { |
| 1098 | res->start += root->start; |
| 1099 | res->end += root->start; |
| 1100 | } |
| 1101 | |
| 1102 | static void __init psycho_base_address_update(struct pci_dev *pdev, int resource) |
| 1103 | { |
| 1104 | struct pcidev_cookie *pcp = pdev->sysdata; |
| 1105 | struct pci_pbm_info *pbm = pcp->pbm; |
| 1106 | struct resource *res, *root; |
| 1107 | u32 reg; |
| 1108 | int where, size, is_64bit; |
| 1109 | |
| 1110 | res = &pdev->resource[resource]; |
| 1111 | if (resource < 6) { |
| 1112 | where = PCI_BASE_ADDRESS_0 + (resource * 4); |
| 1113 | } else if (resource == PCI_ROM_RESOURCE) { |
| 1114 | where = pdev->rom_base_reg; |
| 1115 | } else { |
| 1116 | /* Somebody might have asked allocation of a non-standard resource */ |
| 1117 | return; |
| 1118 | } |
| 1119 | |
| 1120 | is_64bit = 0; |
| 1121 | if (res->flags & IORESOURCE_IO) |
| 1122 | root = &pbm->io_space; |
| 1123 | else { |
| 1124 | root = &pbm->mem_space; |
| 1125 | if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK) |
| 1126 | == PCI_BASE_ADDRESS_MEM_TYPE_64) |
| 1127 | is_64bit = 1; |
| 1128 | } |
| 1129 | |
| 1130 | size = res->end - res->start; |
| 1131 | pci_read_config_dword(pdev, where, ®); |
| 1132 | reg = ((reg & size) | |
| 1133 | (((u32)(res->start - root->start)) & ~size)); |
| 1134 | if (resource == PCI_ROM_RESOURCE) { |
| 1135 | reg |= PCI_ROM_ADDRESS_ENABLE; |
| 1136 | res->flags |= IORESOURCE_ROM_ENABLE; |
| 1137 | } |
| 1138 | pci_write_config_dword(pdev, where, reg); |
| 1139 | |
| 1140 | /* This knows that the upper 32-bits of the address |
| 1141 | * must be zero. Our PCI common layer enforces this. |
| 1142 | */ |
| 1143 | if (is_64bit) |
| 1144 | pci_write_config_dword(pdev, where + 4, 0); |
| 1145 | } |
| 1146 | |
| 1147 | static void __init pbm_config_busmastering(struct pci_pbm_info *pbm) |
| 1148 | { |
| 1149 | u8 *addr; |
| 1150 | |
| 1151 | /* Set cache-line size to 64 bytes, this is actually |
| 1152 | * a nop but I do it for completeness. |
| 1153 | */ |
| 1154 | addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno, |
| 1155 | 0, PCI_CACHE_LINE_SIZE); |
| 1156 | pci_config_write8(addr, 64 / sizeof(u32)); |
| 1157 | |
| 1158 | /* Set PBM latency timer to 64 PCI clocks. */ |
| 1159 | addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno, |
| 1160 | 0, PCI_LATENCY_TIMER); |
| 1161 | pci_config_write8(addr, 64); |
| 1162 | } |
| 1163 | |
| 1164 | static void __init pbm_scan_bus(struct pci_controller_info *p, |
| 1165 | struct pci_pbm_info *pbm) |
| 1166 | { |
| 1167 | struct pcidev_cookie *cookie = kmalloc(sizeof(*cookie), GFP_KERNEL); |
| 1168 | |
| 1169 | if (!cookie) { |
| 1170 | prom_printf("PSYCHO: Critical allocation failure.\n"); |
| 1171 | prom_halt(); |
| 1172 | } |
| 1173 | |
| 1174 | /* All we care about is the PBM. */ |
| 1175 | memset(cookie, 0, sizeof(*cookie)); |
| 1176 | cookie->pbm = pbm; |
| 1177 | |
| 1178 | pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno, |
| 1179 | p->pci_ops, |
| 1180 | pbm); |
| 1181 | pci_fixup_host_bridge_self(pbm->pci_bus); |
| 1182 | pbm->pci_bus->self->sysdata = cookie; |
| 1183 | |
| 1184 | pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node); |
| 1185 | pci_record_assignments(pbm, pbm->pci_bus); |
| 1186 | pci_assign_unassigned(pbm, pbm->pci_bus); |
| 1187 | pci_fixup_irq(pbm, pbm->pci_bus); |
| 1188 | pci_determine_66mhz_disposition(pbm, pbm->pci_bus); |
| 1189 | pci_setup_busmastering(pbm, pbm->pci_bus); |
| 1190 | } |
| 1191 | |
| 1192 | static void __init psycho_scan_bus(struct pci_controller_info *p) |
| 1193 | { |
| 1194 | pbm_config_busmastering(&p->pbm_B); |
| 1195 | p->pbm_B.is_66mhz_capable = 0; |
| 1196 | pbm_config_busmastering(&p->pbm_A); |
| 1197 | p->pbm_A.is_66mhz_capable = 1; |
| 1198 | pbm_scan_bus(p, &p->pbm_B); |
| 1199 | pbm_scan_bus(p, &p->pbm_A); |
| 1200 | |
| 1201 | /* After the PCI bus scan is complete, we can register |
| 1202 | * the error interrupt handlers. |
| 1203 | */ |
| 1204 | psycho_register_error_handlers(p); |
| 1205 | } |
| 1206 | |
| 1207 | static void __init psycho_iommu_init(struct pci_controller_info *p) |
| 1208 | { |
| 1209 | struct pci_iommu *iommu = p->pbm_A.iommu; |
| 1210 | unsigned long tsbbase, i; |
| 1211 | u64 control; |
| 1212 | |
| 1213 | /* Setup initial software IOMMU state. */ |
| 1214 | spin_lock_init(&iommu->lock); |
David S. Miller | 7c963ad | 2005-05-31 16:57:59 -0700 | [diff] [blame] | 1215 | iommu->ctx_lowest_free = 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1216 | |
| 1217 | /* Register addresses. */ |
| 1218 | iommu->iommu_control = p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL; |
| 1219 | iommu->iommu_tsbbase = p->pbm_A.controller_regs + PSYCHO_IOMMU_TSBBASE; |
| 1220 | iommu->iommu_flush = p->pbm_A.controller_regs + PSYCHO_IOMMU_FLUSH; |
| 1221 | /* PSYCHO's IOMMU lacks ctx flushing. */ |
| 1222 | iommu->iommu_ctxflush = 0; |
| 1223 | |
| 1224 | /* We use the main control register of PSYCHO as the write |
| 1225 | * completion register. |
| 1226 | */ |
| 1227 | iommu->write_complete_reg = p->pbm_A.controller_regs + PSYCHO_CONTROL; |
| 1228 | |
| 1229 | /* |
| 1230 | * Invalidate TLB Entries. |
| 1231 | */ |
| 1232 | control = psycho_read(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL); |
| 1233 | control |= PSYCHO_IOMMU_CTRL_DENAB; |
| 1234 | psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL, control); |
| 1235 | for(i = 0; i < 16; i++) { |
| 1236 | psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_TAG + (i * 8UL), 0); |
| 1237 | psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_DATA + (i * 8UL), 0); |
| 1238 | } |
| 1239 | |
| 1240 | /* Leave diag mode enabled for full-flushing done |
| 1241 | * in pci_iommu.c |
| 1242 | */ |
| 1243 | |
| 1244 | iommu->dummy_page = __get_free_pages(GFP_KERNEL, 0); |
| 1245 | if (!iommu->dummy_page) { |
| 1246 | prom_printf("PSYCHO_IOMMU: Error, gfp(dummy_page) failed.\n"); |
| 1247 | prom_halt(); |
| 1248 | } |
| 1249 | memset((void *)iommu->dummy_page, 0, PAGE_SIZE); |
| 1250 | iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page); |
| 1251 | |
| 1252 | /* Using assumed page size 8K with 128K entries we need 1MB iommu page |
| 1253 | * table (128K ioptes * 8 bytes per iopte). This is |
| 1254 | * page order 7 on UltraSparc. |
| 1255 | */ |
| 1256 | tsbbase = __get_free_pages(GFP_KERNEL, get_order(IO_TSB_SIZE)); |
| 1257 | if (!tsbbase) { |
| 1258 | prom_printf("PSYCHO_IOMMU: Error, gfp(tsb) failed.\n"); |
| 1259 | prom_halt(); |
| 1260 | } |
| 1261 | iommu->page_table = (iopte_t *)tsbbase; |
| 1262 | iommu->page_table_sz_bits = 17; |
| 1263 | iommu->page_table_map_base = 0xc0000000; |
| 1264 | iommu->dma_addr_mask = 0xffffffff; |
| 1265 | pci_iommu_table_init(iommu, IO_TSB_SIZE); |
| 1266 | |
| 1267 | /* We start with no consistent mappings. */ |
| 1268 | iommu->lowest_consistent_map = |
| 1269 | 1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS); |
| 1270 | |
| 1271 | for (i = 0; i < PBM_NCLUSTERS; i++) { |
| 1272 | iommu->alloc_info[i].flush = 0; |
| 1273 | iommu->alloc_info[i].next = 0; |
| 1274 | } |
| 1275 | |
| 1276 | psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_TSBBASE, __pa(tsbbase)); |
| 1277 | |
| 1278 | control = psycho_read(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL); |
| 1279 | control &= ~(PSYCHO_IOMMU_CTRL_TSBSZ | PSYCHO_IOMMU_CTRL_TBWSZ); |
| 1280 | control |= (PSYCHO_IOMMU_TSBSZ_128K | PSYCHO_IOMMU_CTRL_ENAB); |
| 1281 | psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL, control); |
| 1282 | |
| 1283 | /* If necessary, hook us up for starfire IRQ translations. */ |
| 1284 | if(this_is_starfire) |
| 1285 | p->starfire_cookie = starfire_hookup(p->pbm_A.portid); |
| 1286 | else |
| 1287 | p->starfire_cookie = NULL; |
| 1288 | } |
| 1289 | |
| 1290 | #define PSYCHO_IRQ_RETRY 0x1a00UL |
| 1291 | #define PSYCHO_PCIA_DIAG 0x2020UL |
| 1292 | #define PSYCHO_PCIB_DIAG 0x4020UL |
| 1293 | #define PSYCHO_PCIDIAG_RESV 0xffffffffffffff80UL /* Reserved */ |
| 1294 | #define PSYCHO_PCIDIAG_DRETRY 0x0000000000000040UL /* Disable retry limit */ |
| 1295 | #define PSYCHO_PCIDIAG_DISYNC 0x0000000000000020UL /* Disable DMA wr / irq sync */ |
| 1296 | #define PSYCHO_PCIDIAG_DDWSYNC 0x0000000000000010UL /* Disable DMA wr / PIO rd sync */ |
| 1297 | #define PSYCHO_PCIDIAG_IDDPAR 0x0000000000000008UL /* Invert DMA data parity */ |
| 1298 | #define PSYCHO_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO data parity */ |
| 1299 | #define PSYCHO_PCIDIAG_IPAPAR 0x0000000000000002UL /* Invert PIO address parity */ |
| 1300 | #define PSYCHO_PCIDIAG_LPBACK 0x0000000000000001UL /* Enable loopback mode */ |
| 1301 | |
| 1302 | static void psycho_controller_hwinit(struct pci_controller_info *p) |
| 1303 | { |
| 1304 | u64 tmp; |
| 1305 | |
| 1306 | /* PROM sets the IRQ retry value too low, increase it. */ |
| 1307 | psycho_write(p->pbm_A.controller_regs + PSYCHO_IRQ_RETRY, 0xff); |
| 1308 | |
| 1309 | /* Enable arbiter for all PCI slots. */ |
| 1310 | tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIA_CTRL); |
| 1311 | tmp |= PSYCHO_PCICTRL_AEN; |
| 1312 | psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIA_CTRL, tmp); |
| 1313 | |
| 1314 | tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIB_CTRL); |
| 1315 | tmp |= PSYCHO_PCICTRL_AEN; |
| 1316 | psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIB_CTRL, tmp); |
| 1317 | |
| 1318 | /* Disable DMA write / PIO read synchronization on |
| 1319 | * both PCI bus segments. |
| 1320 | * [ U2P Erratum 1243770, STP2223BGA data sheet ] |
| 1321 | */ |
| 1322 | tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIA_DIAG); |
| 1323 | tmp |= PSYCHO_PCIDIAG_DDWSYNC; |
| 1324 | psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIA_DIAG, tmp); |
| 1325 | |
| 1326 | tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIB_DIAG); |
| 1327 | tmp |= PSYCHO_PCIDIAG_DDWSYNC; |
| 1328 | psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIB_DIAG, tmp); |
| 1329 | } |
| 1330 | |
| 1331 | static void __init pbm_register_toplevel_resources(struct pci_controller_info *p, |
| 1332 | struct pci_pbm_info *pbm) |
| 1333 | { |
| 1334 | char *name = pbm->name; |
| 1335 | |
| 1336 | sprintf(name, "PSYCHO%d PBM%c", |
| 1337 | p->index, |
| 1338 | (pbm == &p->pbm_A ? 'A' : 'B')); |
| 1339 | pbm->io_space.name = pbm->mem_space.name = name; |
| 1340 | |
| 1341 | request_resource(&ioport_resource, &pbm->io_space); |
| 1342 | request_resource(&iomem_resource, &pbm->mem_space); |
| 1343 | pci_register_legacy_regions(&pbm->io_space, |
| 1344 | &pbm->mem_space); |
| 1345 | } |
| 1346 | |
| 1347 | static void psycho_pbm_strbuf_init(struct pci_controller_info *p, |
| 1348 | struct pci_pbm_info *pbm, |
| 1349 | int is_pbm_a) |
| 1350 | { |
| 1351 | unsigned long base = pbm->controller_regs; |
| 1352 | u64 control; |
| 1353 | |
| 1354 | if (is_pbm_a) { |
| 1355 | pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_A; |
| 1356 | pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_A; |
| 1357 | pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_A; |
| 1358 | } else { |
| 1359 | pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_B; |
| 1360 | pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_B; |
| 1361 | pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_B; |
| 1362 | } |
| 1363 | /* PSYCHO's streaming buffer lacks ctx flushing. */ |
| 1364 | pbm->stc.strbuf_ctxflush = 0; |
| 1365 | pbm->stc.strbuf_ctxmatch_base = 0; |
| 1366 | |
| 1367 | pbm->stc.strbuf_flushflag = (volatile unsigned long *) |
| 1368 | ((((unsigned long)&pbm->stc.__flushflag_buf[0]) |
| 1369 | + 63UL) |
| 1370 | & ~63UL); |
| 1371 | pbm->stc.strbuf_flushflag_pa = (unsigned long) |
| 1372 | __pa(pbm->stc.strbuf_flushflag); |
| 1373 | |
| 1374 | /* Enable the streaming buffer. We have to be careful |
| 1375 | * just in case OBP left it with LRU locking enabled. |
| 1376 | * |
| 1377 | * It is possible to control if PBM will be rerun on |
| 1378 | * line misses. Currently I just retain whatever setting |
| 1379 | * OBP left us with. All checks so far show it having |
| 1380 | * a value of zero. |
| 1381 | */ |
| 1382 | #undef PSYCHO_STRBUF_RERUN_ENABLE |
| 1383 | #undef PSYCHO_STRBUF_RERUN_DISABLE |
| 1384 | control = psycho_read(pbm->stc.strbuf_control); |
| 1385 | control |= PSYCHO_STRBUF_CTRL_ENAB; |
| 1386 | control &= ~(PSYCHO_STRBUF_CTRL_LENAB | PSYCHO_STRBUF_CTRL_LPTR); |
| 1387 | #ifdef PSYCHO_STRBUF_RERUN_ENABLE |
| 1388 | control &= ~(PSYCHO_STRBUF_CTRL_RRDIS); |
| 1389 | #else |
| 1390 | #ifdef PSYCHO_STRBUF_RERUN_DISABLE |
| 1391 | control |= PSYCHO_STRBUF_CTRL_RRDIS; |
| 1392 | #endif |
| 1393 | #endif |
| 1394 | psycho_write(pbm->stc.strbuf_control, control); |
| 1395 | |
| 1396 | pbm->stc.strbuf_enabled = 1; |
| 1397 | } |
| 1398 | |
| 1399 | #define PSYCHO_IOSPACE_A 0x002000000UL |
| 1400 | #define PSYCHO_IOSPACE_B 0x002010000UL |
| 1401 | #define PSYCHO_IOSPACE_SIZE 0x00000ffffUL |
| 1402 | #define PSYCHO_MEMSPACE_A 0x100000000UL |
| 1403 | #define PSYCHO_MEMSPACE_B 0x180000000UL |
| 1404 | #define PSYCHO_MEMSPACE_SIZE 0x07fffffffUL |
| 1405 | |
| 1406 | static void psycho_pbm_init(struct pci_controller_info *p, |
| 1407 | int prom_node, int is_pbm_a) |
| 1408 | { |
| 1409 | unsigned int busrange[2]; |
| 1410 | struct pci_pbm_info *pbm; |
| 1411 | int err; |
| 1412 | |
| 1413 | if (is_pbm_a) { |
| 1414 | pbm = &p->pbm_A; |
| 1415 | pbm->pci_first_slot = 1; |
| 1416 | pbm->io_space.start = pbm->controller_regs + PSYCHO_IOSPACE_A; |
| 1417 | pbm->mem_space.start = pbm->controller_regs + PSYCHO_MEMSPACE_A; |
| 1418 | } else { |
| 1419 | pbm = &p->pbm_B; |
| 1420 | pbm->pci_first_slot = 2; |
| 1421 | pbm->io_space.start = pbm->controller_regs + PSYCHO_IOSPACE_B; |
| 1422 | pbm->mem_space.start = pbm->controller_regs + PSYCHO_MEMSPACE_B; |
| 1423 | } |
| 1424 | |
| 1425 | pbm->chip_type = PBM_CHIP_TYPE_PSYCHO; |
| 1426 | pbm->chip_version = |
| 1427 | prom_getintdefault(prom_node, "version#", 0); |
| 1428 | pbm->chip_revision = |
| 1429 | prom_getintdefault(prom_node, "module-revision#", 0); |
| 1430 | |
| 1431 | pbm->io_space.end = pbm->io_space.start + PSYCHO_IOSPACE_SIZE; |
| 1432 | pbm->io_space.flags = IORESOURCE_IO; |
| 1433 | pbm->mem_space.end = pbm->mem_space.start + PSYCHO_MEMSPACE_SIZE; |
| 1434 | pbm->mem_space.flags = IORESOURCE_MEM; |
| 1435 | pbm_register_toplevel_resources(p, pbm); |
| 1436 | |
| 1437 | pbm->parent = p; |
| 1438 | pbm->prom_node = prom_node; |
| 1439 | prom_getstring(prom_node, "name", |
| 1440 | pbm->prom_name, |
| 1441 | sizeof(pbm->prom_name)); |
| 1442 | |
| 1443 | err = prom_getproperty(prom_node, "ranges", |
| 1444 | (char *)pbm->pbm_ranges, |
| 1445 | sizeof(pbm->pbm_ranges)); |
| 1446 | if (err != -1) |
| 1447 | pbm->num_pbm_ranges = |
| 1448 | (err / sizeof(struct linux_prom_pci_ranges)); |
| 1449 | else |
| 1450 | pbm->num_pbm_ranges = 0; |
| 1451 | |
| 1452 | err = prom_getproperty(prom_node, "interrupt-map", |
| 1453 | (char *)pbm->pbm_intmap, |
| 1454 | sizeof(pbm->pbm_intmap)); |
| 1455 | if (err != -1) { |
| 1456 | pbm->num_pbm_intmap = (err / sizeof(struct linux_prom_pci_intmap)); |
| 1457 | err = prom_getproperty(prom_node, "interrupt-map-mask", |
| 1458 | (char *)&pbm->pbm_intmask, |
| 1459 | sizeof(pbm->pbm_intmask)); |
| 1460 | if (err == -1) { |
| 1461 | prom_printf("PSYCHO-PBM: Fatal error, no " |
| 1462 | "interrupt-map-mask.\n"); |
| 1463 | prom_halt(); |
| 1464 | } |
| 1465 | } else { |
| 1466 | pbm->num_pbm_intmap = 0; |
| 1467 | memset(&pbm->pbm_intmask, 0, sizeof(pbm->pbm_intmask)); |
| 1468 | } |
| 1469 | |
| 1470 | err = prom_getproperty(prom_node, "bus-range", |
| 1471 | (char *)&busrange[0], |
| 1472 | sizeof(busrange)); |
| 1473 | if (err == 0 || err == -1) { |
| 1474 | prom_printf("PSYCHO-PBM: Fatal error, no bus-range.\n"); |
| 1475 | prom_halt(); |
| 1476 | } |
| 1477 | pbm->pci_first_busno = busrange[0]; |
| 1478 | pbm->pci_last_busno = busrange[1]; |
| 1479 | |
| 1480 | psycho_pbm_strbuf_init(p, pbm, is_pbm_a); |
| 1481 | } |
| 1482 | |
| 1483 | #define PSYCHO_CONFIGSPACE 0x001000000UL |
| 1484 | |
| 1485 | void __init psycho_init(int node, char *model_name) |
| 1486 | { |
| 1487 | struct linux_prom64_registers pr_regs[3]; |
| 1488 | struct pci_controller_info *p; |
| 1489 | struct pci_iommu *iommu; |
| 1490 | u32 upa_portid; |
| 1491 | int is_pbm_a, err; |
| 1492 | |
| 1493 | upa_portid = prom_getintdefault(node, "upa-portid", 0xff); |
| 1494 | |
| 1495 | for(p = pci_controller_root; p; p = p->next) { |
| 1496 | if (p->pbm_A.portid == upa_portid) { |
| 1497 | is_pbm_a = (p->pbm_A.prom_node == 0); |
| 1498 | psycho_pbm_init(p, node, is_pbm_a); |
| 1499 | return; |
| 1500 | } |
| 1501 | } |
| 1502 | |
| 1503 | p = kmalloc(sizeof(struct pci_controller_info), GFP_ATOMIC); |
| 1504 | if (!p) { |
| 1505 | prom_printf("PSYCHO: Fatal memory allocation error.\n"); |
| 1506 | prom_halt(); |
| 1507 | } |
| 1508 | memset(p, 0, sizeof(*p)); |
| 1509 | iommu = kmalloc(sizeof(struct pci_iommu), GFP_ATOMIC); |
| 1510 | if (!iommu) { |
| 1511 | prom_printf("PSYCHO: Fatal memory allocation error.\n"); |
| 1512 | prom_halt(); |
| 1513 | } |
| 1514 | memset(iommu, 0, sizeof(*iommu)); |
| 1515 | p->pbm_A.iommu = p->pbm_B.iommu = iommu; |
| 1516 | |
| 1517 | p->next = pci_controller_root; |
| 1518 | pci_controller_root = p; |
| 1519 | |
| 1520 | p->pbm_A.portid = upa_portid; |
| 1521 | p->pbm_B.portid = upa_portid; |
| 1522 | p->index = pci_num_controllers++; |
| 1523 | p->pbms_same_domain = 0; |
| 1524 | p->scan_bus = psycho_scan_bus; |
| 1525 | p->irq_build = psycho_irq_build; |
| 1526 | p->base_address_update = psycho_base_address_update; |
| 1527 | p->resource_adjust = psycho_resource_adjust; |
| 1528 | p->pci_ops = &psycho_ops; |
| 1529 | |
| 1530 | err = prom_getproperty(node, "reg", |
| 1531 | (char *)&pr_regs[0], |
| 1532 | sizeof(pr_regs)); |
| 1533 | if (err == 0 || err == -1) { |
| 1534 | prom_printf("PSYCHO: Fatal error, no reg property.\n"); |
| 1535 | prom_halt(); |
| 1536 | } |
| 1537 | |
| 1538 | p->pbm_A.controller_regs = pr_regs[2].phys_addr; |
| 1539 | p->pbm_B.controller_regs = pr_regs[2].phys_addr; |
| 1540 | printk("PCI: Found PSYCHO, control regs at %016lx\n", |
| 1541 | p->pbm_A.controller_regs); |
| 1542 | |
| 1543 | p->pbm_A.config_space = p->pbm_B.config_space = |
| 1544 | (pr_regs[2].phys_addr + PSYCHO_CONFIGSPACE); |
| 1545 | printk("PSYCHO: Shared PCI config space at %016lx\n", |
| 1546 | p->pbm_A.config_space); |
| 1547 | |
| 1548 | /* |
| 1549 | * Psycho's PCI MEM space is mapped to a 2GB aligned area, so |
| 1550 | * we need to adjust our MEM space mask. |
| 1551 | */ |
| 1552 | pci_memspace_mask = 0x7fffffffUL; |
| 1553 | |
| 1554 | psycho_controller_hwinit(p); |
| 1555 | |
| 1556 | psycho_iommu_init(p); |
| 1557 | |
| 1558 | is_pbm_a = ((pr_regs[0].phys_addr & 0x6000) == 0x2000); |
| 1559 | psycho_pbm_init(p, node, is_pbm_a); |
| 1560 | } |