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Paul Walmsley543d9372008-03-18 10:22:06 +02001/*
2 * linux/arch/arm/mach-omap2/clock.c
3 *
Tony Lindgrena16e9702008-03-18 11:56:39 +02004 * Copyright (C) 2005-2008 Texas Instruments, Inc.
Paul Walmsley8c349742010-02-22 22:09:24 -07005 * Copyright (C) 2004-2010 Nokia Corporation
Tony Lindgrena16e9702008-03-18 11:56:39 +02006 *
7 * Contacts:
Paul Walmsley543d9372008-03-18 10:22:06 +02008 * Richard Woodruff <r-woodruff2@ti.com>
Paul Walmsley543d9372008-03-18 10:22:06 +02009 * Paul Walmsley
10 *
Paul Walmsley543d9372008-03-18 10:22:06 +020011 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15#undef DEBUG
16
Paul Walmsley543d9372008-03-18 10:22:06 +020017#include <linux/kernel.h>
Paul Walmsley1fe9be82012-09-27 10:33:33 -060018#include <linux/export.h>
Paul Walmsley543d9372008-03-18 10:22:06 +020019#include <linux/list.h>
20#include <linux/errno.h>
Paul Walmsley4d30e822010-02-22 22:09:36 -070021#include <linux/err.h>
22#include <linux/delay.h>
Stephen Boydf5b00f62015-06-22 17:05:21 -070023#include <linux/clk.h>
Mike Turquette32cc0022012-11-10 16:58:41 -070024#include <linux/clk-provider.h>
Russell Kingfced80c2008-09-06 12:10:45 +010025#include <linux/io.h>
Russell Kingfbd3bdb2008-09-06 12:13:59 +010026#include <linux/bitops.h>
Tero Kristo9f029b12014-10-22 15:15:36 +030027#include <linux/of_address.h>
Jean Pihet5e7c58d2011-03-03 11:25:43 +010028#include <asm/cpu.h>
Tony Lindgrendbc04162012-08-31 10:59:07 -070029
Tony Lindgrendbc04162012-08-31 10:59:07 -070030#include <trace/events/power.h>
31
32#include "soc.h"
33#include "clockdomain.h"
Paul Walmsley543d9372008-03-18 10:22:06 +020034#include "clock.h"
Paul Walmsleyc4ceedc2012-10-29 20:56:29 -060035#include "cm.h"
Paul Walmsleyff4ae5d2012-10-21 01:01:11 -060036#include "cm2xxx.h"
37#include "cm3xxx.h"
Paul Walmsley543d9372008-03-18 10:22:06 +020038#include "cm-regbits-24xx.h"
39#include "cm-regbits-34xx.h"
Paul Walmsleyc4ceedc2012-10-29 20:56:29 -060040#include "common.h"
41
Afzal Mohammed99541192011-12-13 10:46:43 -080042u16 cpu_mask;
Paul Walmsley543d9372008-03-18 10:22:06 +020043
Tero Kristoa24886e2014-07-02 11:47:40 +030044/* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */
45#define OMAP3430_DPLL_FINT_BAND1_MIN 750000
46#define OMAP3430_DPLL_FINT_BAND1_MAX 2100000
47#define OMAP3430_DPLL_FINT_BAND2_MIN 7500000
48#define OMAP3430_DPLL_FINT_BAND2_MAX 21000000
49
50/*
51 * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx.
52 * From device data manual section 4.3 "DPLL and DLL Specifications".
53 */
54#define OMAP3PLUS_DPLL_FINT_MIN 32000
55#define OMAP3PLUS_DPLL_FINT_MAX 52000000
56
Tero Kristo6c0afb52017-02-09 11:24:37 +020057struct ti_clk_ll_ops omap_clk_ll_ops = {
Tero Kristo9a356d62015-03-03 11:14:31 +020058 .clkdm_clk_enable = clkdm_clk_enable,
59 .clkdm_clk_disable = clkdm_clk_disable,
Tero Kristob6f27b22016-09-30 14:10:11 +030060 .clkdm_lookup = clkdm_lookup,
Tero Kristo192383d2015-03-03 13:47:08 +020061 .cm_wait_module_ready = omap_cm_wait_module_ready,
62 .cm_split_idlest_reg = cm_split_idlest_reg,
Tero Kristo9f029b12014-10-22 15:15:36 +030063};
Tero Kristo3ada6b102013-10-22 11:47:08 +030064
Tero Kristo9f029b12014-10-22 15:15:36 +030065/**
Tero Kristoe9e63082015-04-27 21:55:42 +030066 * omap2_clk_setup_ll_ops - setup clock driver low-level ops
67 *
68 * Sets up clock driver low-level platform ops. These are needed
69 * for register accesses and various other misc platform operations.
70 * Returns 0 on success, -EBUSY if low level ops have been registered
71 * already.
72 */
73int __init omap2_clk_setup_ll_ops(void)
74{
75 return ti_clk_setup_ll_ops(&omap_clk_ll_ops);
76}
77
Mike Turquette32cc0022012-11-10 16:58:41 -070078/*
Paul Walmsley30962d92010-02-22 22:09:38 -070079 * OMAP2+ specific clock functions
80 */
Paul Walmsley543d9372008-03-18 10:22:06 +020081
Tero Kristo8111e012014-07-02 11:47:39 +030082/**
83 * ti_clk_init_features - init clock features struct for the SoC
84 *
85 * Initializes the clock features struct based on the SoC type.
86 */
87void __init ti_clk_init_features(void)
88{
Tero Kristof3b19aa2015-02-27 17:54:14 +020089 struct ti_clk_features features = { 0 };
Tero Kristoa24886e2014-07-02 11:47:40 +030090 /* Fint setup for DPLLs */
91 if (cpu_is_omap3430()) {
Tero Kristof3b19aa2015-02-27 17:54:14 +020092 features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN;
93 features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX;
94 features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX;
95 features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN;
Tero Kristoa24886e2014-07-02 11:47:40 +030096 } else {
Tero Kristof3b19aa2015-02-27 17:54:14 +020097 features.fint_min = OMAP3PLUS_DPLL_FINT_MIN;
98 features.fint_max = OMAP3PLUS_DPLL_FINT_MAX;
Tero Kristoa24886e2014-07-02 11:47:40 +030099 }
Tero Kristo512d91c2014-07-02 11:47:42 +0300100
101 /* Bypass value setup for DPLLs */
102 if (cpu_is_omap24xx()) {
Tero Kristof3b19aa2015-02-27 17:54:14 +0200103 features.dpll_bypass_vals |=
Tero Kristo512d91c2014-07-02 11:47:42 +0300104 (1 << OMAP2XXX_EN_DPLL_LPBYPASS) |
105 (1 << OMAP2XXX_EN_DPLL_FRBYPASS);
106 } else if (cpu_is_omap34xx()) {
Tero Kristof3b19aa2015-02-27 17:54:14 +0200107 features.dpll_bypass_vals |=
Tero Kristo512d91c2014-07-02 11:47:42 +0300108 (1 << OMAP3XXX_EN_DPLL_LPBYPASS) |
109 (1 << OMAP3XXX_EN_DPLL_FRBYPASS);
110 } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() ||
111 soc_is_omap54xx() || soc_is_dra7xx()) {
Tero Kristof3b19aa2015-02-27 17:54:14 +0200112 features.dpll_bypass_vals |=
Tero Kristo512d91c2014-07-02 11:47:42 +0300113 (1 << OMAP4XXX_EN_DPLL_LPBYPASS) |
114 (1 << OMAP4XXX_EN_DPLL_FRBYPASS) |
115 (1 << OMAP4XXX_EN_DPLL_MNBYPASS);
116 }
Tero Kristo2337c5b2014-07-02 11:47:43 +0300117
118 /* Jitter correction only available on OMAP343X */
119 if (cpu_is_omap343x())
Tero Kristof3b19aa2015-02-27 17:54:14 +0200120 features.flags |= TI_CLK_DPLL_HAS_FREQSEL;
Tero Kristo066edb22014-07-02 11:47:44 +0300121
122 /* Idlest value for interface clocks.
123 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
124 * 34xx reverses this, just to keep us on our toes
125 * AM35xx uses both, depending on the module.
126 */
127 if (cpu_is_omap24xx())
Tero Kristof3b19aa2015-02-27 17:54:14 +0200128 features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL;
Tero Kristo066edb22014-07-02 11:47:44 +0300129 else if (cpu_is_omap34xx())
Tero Kristof3b19aa2015-02-27 17:54:14 +0200130 features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL;
Tero Kristof0d2f682014-10-03 16:57:10 +0300131
132 /* On OMAP3430 ES1.0, DPLL4 can't be re-programmed */
133 if (omap_rev() == OMAP3430_REV_ES1_0)
Tero Kristof3b19aa2015-02-27 17:54:14 +0200134 features.flags |= TI_CLK_DPLL4_DENY_REPROGRAM;
135
Tero Kristo07ff73a2015-11-30 16:43:25 +0200136 /* Errata I810 for omap5 / dra7 */
137 if (soc_is_omap54xx() || soc_is_dra7xx())
138 features.flags |= TI_CLK_ERRATA_I810;
139
Tero Kristof3b19aa2015-02-27 17:54:14 +0200140 ti_clk_setup_features(&features);
Tero Kristo8111e012014-07-02 11:47:39 +0300141}