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Magnus Dammeccf0602013-03-26 10:34:24 +09001/*
2 * r8a73a4 processor support
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Magnus Dammeccf0602013-03-26 10:34:24 +090015 */
16#include <linux/irq.h>
Magnus Dammeccf0602013-03-26 10:34:24 +090017#include <linux/kernel.h>
18#include <linux/of_platform.h>
Magnus Damm984ca292013-03-26 10:34:42 +090019#include <linux/platform_data/irq-renesas-irqc.h>
Magnus Damme481a522013-03-26 10:34:33 +090020#include <linux/serial_sci.h>
Guennadi Liakhovetski9f754b42013-08-02 16:50:40 +020021#include <linux/sh_dma.h>
Magnus Damma7b99f22013-06-28 20:27:23 +090022#include <linux/sh_timer.h>
Geert Uytterhoevenfac49562014-06-20 18:53:02 +020023
Magnus Dammeccf0602013-03-26 10:34:24 +090024#include <asm/mach/arch.h>
25
Magnus Dammfd44aa52014-06-17 16:47:37 +090026#include "common.h"
Magnus Damm74ac0de2014-06-17 16:47:13 +090027#include "dma-register.h"
Magnus Dammb6bab122014-06-17 16:47:29 +090028#include "irqs.h"
Geert Uytterhoevenfac49562014-06-20 18:53:02 +020029#include "r8a73a4.h"
Magnus Dammeccf0602013-03-26 10:34:24 +090030
Magnus Dammd313d062013-03-26 10:34:52 +090031static const struct resource pfc_resources[] = {
32 DEFINE_RES_MEM(0xe6050000, 0x9000),
33};
34
35void __init r8a73a4_pinmux_init(void)
36{
37 platform_device_register_simple("pfc-r8a73a4", -1, pfc_resources,
38 ARRAY_SIZE(pfc_resources));
39}
40
Laurent Pinchart4d32e832013-12-06 10:59:26 +010041#define R8A73A4_SCIF(scif_type, _scscr, index, baseaddr, irq) \
42static struct plat_sci_port scif##index##_platform_data = { \
Magnus Damme481a522013-03-26 10:34:33 +090043 .type = scif_type, \
Magnus Damme481a522013-03-26 10:34:33 +090044 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, \
Laurent Pinchart4d32e832013-12-06 10:59:26 +010045 .scscr = _scscr, \
Laurent Pinchart88264782013-12-06 10:59:33 +010046}; \
47 \
48static struct resource scif##index##_resources[] = { \
49 DEFINE_RES_MEM(baseaddr, 0x100), \
50 DEFINE_RES_IRQ(irq), \
Magnus Damme481a522013-03-26 10:34:33 +090051}
52
Laurent Pinchart4d32e832013-12-06 10:59:26 +010053#define R8A73A4_SCIFA(index, baseaddr, irq) \
54 R8A73A4_SCIF(PORT_SCIFA, SCSCR_RE | SCSCR_TE | SCSCR_CKE0, \
55 index, baseaddr, irq)
Magnus Damme481a522013-03-26 10:34:33 +090056
Laurent Pinchart4d32e832013-12-06 10:59:26 +010057#define R8A73A4_SCIFB(index, baseaddr, irq) \
58 R8A73A4_SCIF(PORT_SCIFB, SCSCR_RE | SCSCR_TE, \
59 index, baseaddr, irq)
Magnus Damme481a522013-03-26 10:34:33 +090060
Laurent Pinchart4d32e832013-12-06 10:59:26 +010061R8A73A4_SCIFA(0, 0xe6c40000, gic_spi(144)); /* SCIFA0 */
62R8A73A4_SCIFA(1, 0xe6c50000, gic_spi(145)); /* SCIFA1 */
63R8A73A4_SCIFB(2, 0xe6c20000, gic_spi(148)); /* SCIFB0 */
64R8A73A4_SCIFB(3, 0xe6c30000, gic_spi(149)); /* SCIFB1 */
65R8A73A4_SCIFB(4, 0xe6ce0000, gic_spi(150)); /* SCIFB2 */
66R8A73A4_SCIFB(5, 0xe6cf0000, gic_spi(151)); /* SCIFB3 */
Magnus Damme481a522013-03-26 10:34:33 +090067
Laurent Pinchart4d32e832013-12-06 10:59:26 +010068#define r8a73a4_register_scif(index) \
Pawel Molld2168142014-07-23 18:07:18 +010069 platform_device_register_resndata(NULL, "sh-sci", index, \
Laurent Pinchart88264782013-12-06 10:59:33 +010070 scif##index##_resources, \
71 ARRAY_SIZE(scif##index##_resources), \
72 &scif##index##_platform_data, \
73 sizeof(scif##index##_platform_data))
Magnus Damme481a522013-03-26 10:34:33 +090074
Magnus Damm984ca292013-03-26 10:34:42 +090075static const struct renesas_irqc_config irqc0_data = {
76 .irq_base = irq_pin(0), /* IRQ0 -> IRQ31 */
77};
78
79static const struct resource irqc0_resources[] = {
80 DEFINE_RES_MEM(0xe61c0000, 0x200), /* IRQC Event Detector Block_0 */
81 DEFINE_RES_IRQ(gic_spi(0)), /* IRQ0 */
82 DEFINE_RES_IRQ(gic_spi(1)), /* IRQ1 */
83 DEFINE_RES_IRQ(gic_spi(2)), /* IRQ2 */
84 DEFINE_RES_IRQ(gic_spi(3)), /* IRQ3 */
85 DEFINE_RES_IRQ(gic_spi(4)), /* IRQ4 */
86 DEFINE_RES_IRQ(gic_spi(5)), /* IRQ5 */
87 DEFINE_RES_IRQ(gic_spi(6)), /* IRQ6 */
88 DEFINE_RES_IRQ(gic_spi(7)), /* IRQ7 */
89 DEFINE_RES_IRQ(gic_spi(8)), /* IRQ8 */
90 DEFINE_RES_IRQ(gic_spi(9)), /* IRQ9 */
91 DEFINE_RES_IRQ(gic_spi(10)), /* IRQ10 */
92 DEFINE_RES_IRQ(gic_spi(11)), /* IRQ11 */
93 DEFINE_RES_IRQ(gic_spi(12)), /* IRQ12 */
94 DEFINE_RES_IRQ(gic_spi(13)), /* IRQ13 */
95 DEFINE_RES_IRQ(gic_spi(14)), /* IRQ14 */
96 DEFINE_RES_IRQ(gic_spi(15)), /* IRQ15 */
97 DEFINE_RES_IRQ(gic_spi(16)), /* IRQ16 */
98 DEFINE_RES_IRQ(gic_spi(17)), /* IRQ17 */
99 DEFINE_RES_IRQ(gic_spi(18)), /* IRQ18 */
100 DEFINE_RES_IRQ(gic_spi(19)), /* IRQ19 */
101 DEFINE_RES_IRQ(gic_spi(20)), /* IRQ20 */
102 DEFINE_RES_IRQ(gic_spi(21)), /* IRQ21 */
103 DEFINE_RES_IRQ(gic_spi(22)), /* IRQ22 */
104 DEFINE_RES_IRQ(gic_spi(23)), /* IRQ23 */
105 DEFINE_RES_IRQ(gic_spi(24)), /* IRQ24 */
106 DEFINE_RES_IRQ(gic_spi(25)), /* IRQ25 */
107 DEFINE_RES_IRQ(gic_spi(26)), /* IRQ26 */
108 DEFINE_RES_IRQ(gic_spi(27)), /* IRQ27 */
109 DEFINE_RES_IRQ(gic_spi(28)), /* IRQ28 */
110 DEFINE_RES_IRQ(gic_spi(29)), /* IRQ29 */
111 DEFINE_RES_IRQ(gic_spi(30)), /* IRQ30 */
112 DEFINE_RES_IRQ(gic_spi(31)), /* IRQ31 */
113};
114
115static const struct renesas_irqc_config irqc1_data = {
116 .irq_base = irq_pin(32), /* IRQ32 -> IRQ57 */
117};
118
119static const struct resource irqc1_resources[] = {
120 DEFINE_RES_MEM(0xe61c0200, 0x200), /* IRQC Event Detector Block_1 */
121 DEFINE_RES_IRQ(gic_spi(32)), /* IRQ32 */
122 DEFINE_RES_IRQ(gic_spi(33)), /* IRQ33 */
123 DEFINE_RES_IRQ(gic_spi(34)), /* IRQ34 */
124 DEFINE_RES_IRQ(gic_spi(35)), /* IRQ35 */
125 DEFINE_RES_IRQ(gic_spi(36)), /* IRQ36 */
126 DEFINE_RES_IRQ(gic_spi(37)), /* IRQ37 */
127 DEFINE_RES_IRQ(gic_spi(38)), /* IRQ38 */
128 DEFINE_RES_IRQ(gic_spi(39)), /* IRQ39 */
129 DEFINE_RES_IRQ(gic_spi(40)), /* IRQ40 */
130 DEFINE_RES_IRQ(gic_spi(41)), /* IRQ41 */
131 DEFINE_RES_IRQ(gic_spi(42)), /* IRQ42 */
132 DEFINE_RES_IRQ(gic_spi(43)), /* IRQ43 */
133 DEFINE_RES_IRQ(gic_spi(44)), /* IRQ44 */
134 DEFINE_RES_IRQ(gic_spi(45)), /* IRQ45 */
135 DEFINE_RES_IRQ(gic_spi(46)), /* IRQ46 */
136 DEFINE_RES_IRQ(gic_spi(47)), /* IRQ47 */
137 DEFINE_RES_IRQ(gic_spi(48)), /* IRQ48 */
138 DEFINE_RES_IRQ(gic_spi(49)), /* IRQ49 */
139 DEFINE_RES_IRQ(gic_spi(50)), /* IRQ50 */
140 DEFINE_RES_IRQ(gic_spi(51)), /* IRQ51 */
141 DEFINE_RES_IRQ(gic_spi(52)), /* IRQ52 */
142 DEFINE_RES_IRQ(gic_spi(53)), /* IRQ53 */
143 DEFINE_RES_IRQ(gic_spi(54)), /* IRQ54 */
144 DEFINE_RES_IRQ(gic_spi(55)), /* IRQ55 */
145 DEFINE_RES_IRQ(gic_spi(56)), /* IRQ56 */
146 DEFINE_RES_IRQ(gic_spi(57)), /* IRQ57 */
147};
148
149#define r8a73a4_register_irqc(idx) \
Pawel Molld2168142014-07-23 18:07:18 +0100150 platform_device_register_resndata(NULL, "renesas_irqc", \
Magnus Damm984ca292013-03-26 10:34:42 +0900151 idx, irqc##idx##_resources, \
152 ARRAY_SIZE(irqc##idx##_resources), \
153 &irqc##idx##_data, \
154 sizeof(struct renesas_irqc_config))
155
Kuninori Morimotoc91cf2f2013-03-25 23:18:15 -0700156/* Thermal0 -> Thermal2 */
157static const struct resource thermal0_resources[] = {
158 DEFINE_RES_MEM(0xe61f0000, 0x14),
159 DEFINE_RES_MEM(0xe61f0100, 0x38),
160 DEFINE_RES_MEM(0xe61f0200, 0x38),
161 DEFINE_RES_MEM(0xe61f0300, 0x38),
162 DEFINE_RES_IRQ(gic_spi(69)),
163};
164
165#define r8a73a4_register_thermal() \
166 platform_device_register_simple("rcar_thermal", -1, \
167 thermal0_resources, \
168 ARRAY_SIZE(thermal0_resources))
169
Laurent Pinchart52065ef2014-04-23 13:15:11 +0200170static struct sh_timer_config cmt1_platform_data = {
171 .channels_mask = 0xff,
Magnus Damma7b99f22013-06-28 20:27:23 +0900172};
173
Laurent Pinchart52065ef2014-04-23 13:15:11 +0200174static struct resource cmt1_resources[] = {
175 DEFINE_RES_MEM(0xe6130000, 0x1004),
176 DEFINE_RES_IRQ(gic_spi(120)),
Magnus Damma7b99f22013-06-28 20:27:23 +0900177};
178
Simon Horman95e39682014-07-07 09:54:37 +0200179#define r8a73a4_register_cmt(idx) \
Pawel Molld2168142014-07-23 18:07:18 +0100180 platform_device_register_resndata(NULL, "sh-cmt-48-gen2", \
Magnus Damma7b99f22013-06-28 20:27:23 +0900181 idx, cmt##idx##_resources, \
182 ARRAY_SIZE(cmt##idx##_resources), \
183 &cmt##idx##_platform_data, \
184 sizeof(struct sh_timer_config))
185
Guennadi Liakhovetski9f754b42013-08-02 16:50:40 +0200186/* DMA */
187static const struct sh_dmae_slave_config dma_slaves[] = {
188 {
189 .slave_id = SHDMA_SLAVE_MMCIF0_TX,
190 .addr = 0xee200034,
191 .chcr = CHCR_TX(XMIT_SZ_32BIT),
192 .mid_rid = 0xd1,
193 }, {
194 .slave_id = SHDMA_SLAVE_MMCIF0_RX,
195 .addr = 0xee200034,
196 .chcr = CHCR_RX(XMIT_SZ_32BIT),
197 .mid_rid = 0xd2,
198 }, {
199 .slave_id = SHDMA_SLAVE_MMCIF1_TX,
200 .addr = 0xee220034,
201 .chcr = CHCR_TX(XMIT_SZ_32BIT),
202 .mid_rid = 0xe1,
203 }, {
204 .slave_id = SHDMA_SLAVE_MMCIF1_RX,
205 .addr = 0xee220034,
206 .chcr = CHCR_RX(XMIT_SZ_32BIT),
207 .mid_rid = 0xe2,
208 },
209};
210
211#define DMAE_CHANNEL(a, b) \
212 { \
213 .offset = (a) - 0x20, \
214 .dmars = (a) - 0x20 + 0x40, \
215 .chclr_bit = (b), \
216 .chclr_offset = 0x80 - 0x20, \
217 }
218
219static const struct sh_dmae_channel dma_channels[] = {
220 DMAE_CHANNEL(0x8000, 0),
221 DMAE_CHANNEL(0x8080, 1),
222 DMAE_CHANNEL(0x8100, 2),
223 DMAE_CHANNEL(0x8180, 3),
224 DMAE_CHANNEL(0x8200, 4),
225 DMAE_CHANNEL(0x8280, 5),
226 DMAE_CHANNEL(0x8300, 6),
227 DMAE_CHANNEL(0x8380, 7),
228 DMAE_CHANNEL(0x8400, 8),
229 DMAE_CHANNEL(0x8480, 9),
230 DMAE_CHANNEL(0x8500, 10),
231 DMAE_CHANNEL(0x8580, 11),
232 DMAE_CHANNEL(0x8600, 12),
233 DMAE_CHANNEL(0x8680, 13),
234 DMAE_CHANNEL(0x8700, 14),
235 DMAE_CHANNEL(0x8780, 15),
236 DMAE_CHANNEL(0x8800, 16),
237 DMAE_CHANNEL(0x8880, 17),
238 DMAE_CHANNEL(0x8900, 18),
239 DMAE_CHANNEL(0x8980, 19),
240};
241
242static const struct sh_dmae_pdata dma_pdata = {
243 .slave = dma_slaves,
244 .slave_num = ARRAY_SIZE(dma_slaves),
245 .channel = dma_channels,
246 .channel_num = ARRAY_SIZE(dma_channels),
247 .ts_low_shift = TS_LOW_SHIFT,
248 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
249 .ts_high_shift = TS_HI_SHIFT,
250 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
251 .ts_shift = dma_ts_shift,
252 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
253 .dmaor_init = DMAOR_DME,
254 .chclr_present = 1,
255 .chclr_bitwise = 1,
256};
257
258static struct resource dma_resources[] = {
259 DEFINE_RES_MEM(0xe6700020, 0x89e0),
Kuninori Morimoto1a936a32013-10-07 22:59:23 -0700260 DEFINE_RES_IRQ(gic_spi(220)),
Guennadi Liakhovetski9f754b42013-08-02 16:50:40 +0200261 {
262 /* IRQ for channels 0-19 */
263 .start = gic_spi(200),
264 .end = gic_spi(219),
265 .flags = IORESOURCE_IRQ,
266 },
267};
268
269#define r8a73a4_register_dmac() \
Pawel Molld2168142014-07-23 18:07:18 +0100270 platform_device_register_resndata(NULL, "sh-dma-engine", 0, \
Guennadi Liakhovetski9f754b42013-08-02 16:50:40 +0200271 dma_resources, ARRAY_SIZE(dma_resources), \
272 &dma_pdata, sizeof(dma_pdata))
273
Guennadi Liakhovetski69f36662013-07-08 18:04:57 +0200274void __init r8a73a4_add_standard_devices(void)
275{
Simon Hormandfb846c2014-07-07 09:54:38 +0200276 r8a73a4_register_cmt(1);
Simon Horman27bc8232014-07-07 09:54:34 +0200277 r8a73a4_register_scif(0);
278 r8a73a4_register_scif(1);
279 r8a73a4_register_scif(2);
280 r8a73a4_register_scif(3);
281 r8a73a4_register_scif(4);
282 r8a73a4_register_scif(5);
Magnus Damm984ca292013-03-26 10:34:42 +0900283 r8a73a4_register_irqc(0);
284 r8a73a4_register_irqc(1);
Kuninori Morimotoc91cf2f2013-03-25 23:18:15 -0700285 r8a73a4_register_thermal();
Guennadi Liakhovetski9f754b42013-08-02 16:50:40 +0200286 r8a73a4_register_dmac();
Magnus Dammeccf0602013-03-26 10:34:24 +0900287}
288
289#ifdef CONFIG_USE_OF
Magnus Dammeccf0602013-03-26 10:34:24 +0900290
291static const char *r8a73a4_boards_compat_dt[] __initdata = {
292 "renesas,r8a73a4",
293 NULL,
294};
295
296DT_MACHINE_START(R8A73A4_DT, "Generic R8A73A4 (Flattened Device Tree)")
Magnus Dammf5720082014-08-20 22:03:03 +0900297 .init_early = shmobile_init_delay,
Magnus Damm0592d1b2014-07-31 08:33:08 +0900298 .init_late = shmobile_init_late,
Magnus Dammeccf0602013-03-26 10:34:24 +0900299 .dt_compat = r8a73a4_boards_compat_dt,
300MACHINE_END
301#endif /* CONFIG_USE_OF */