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kunit / linux / 22baebd489c78cf7d02030bf50b0c99e4fcb6748 / . / arch / sparc / kernel / rtrap_64.S
blob: 709a82ebd294c07bd4b87698c695325e5093a7e4 [file] [log] [blame]
Adrian Bunkb00dc832008-05-19 16:52:27 -0700[diff] [blame]1/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]2 * rtrap.S: Preparing for return from trap on Sparc V9.
3 *
4 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
5 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
6 */
7
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]8
9#include <asm/asi.h>
10#include <asm/pstate.h>
11#include <asm/ptrace.h>
12#include <asm/spitfire.h>
13#include <asm/head.h>
14#include <asm/visasm.h>
15#include <asm/processor.h>
16
Kirill Tkhai812cb832013-09-14 16:02:11 +0400[diff] [blame]17#ifdef CONFIG_CONTEXT_TRACKING
18# define SCHEDULE_USER schedule_user
19#else
20# define SCHEDULE_USER schedule
21#endif
22
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]23 .text
24 .align 32
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]25__handle_preemption:
Kirill Tkhai812cb832013-09-14 16:02:11 +0400[diff] [blame]26 call SCHEDULE_USER
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]27 wrpr %g0, RTRAP_PSTATE, %pstate
28 ba,pt %xcc, __handle_preemption_continue
29 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
30
31__handle_user_windows:
32 call fault_in_user_windows
33 wrpr %g0, RTRAP_PSTATE, %pstate
Al Virocaebf912010-09-23 21:52:52 -0700[diff] [blame]34 ba,pt %xcc, __handle_preemption_continue
35 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]36
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]37__handle_userfpu:
38 rd %fprs, %l5
39 andcc %l5, FPRS_FEF, %g0
40 sethi %hi(TSTATE_PEF), %o0
41 be,a,pn %icc, __handle_userfpu_continue
42 andn %l1, %o0, %l1
43 ba,a,pt %xcc, __handle_userfpu_continue
44
45__handle_signal:
David S. Miller2d7d5f02006-01-19 02:42:49 -0800[diff] [blame]46 mov %l5, %o1
David S. Miller2d7d5f02006-01-19 02:42:49 -0800[diff] [blame]47 add %sp, PTREGS_OFF, %o0
David S. Miller7697daa2008-04-24 03:15:22 -0700[diff] [blame]48 mov %l0, %o2
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]49 call do_notify_resume
50 wrpr %g0, RTRAP_PSTATE, %pstate
51 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]52
53 /* Signal delivery can modify pt_regs tstate, so we must
54 * reload it.
55 */
56 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
57 sethi %hi(0xf << 20), %l4
58 and %l1, %l4, %l4
Al Virocaebf912010-09-23 21:52:52 -0700[diff] [blame]59 ba,pt %xcc, __handle_preemption_continue
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]60 andn %l1, %l4, %l1
61
David S. Miller55657362008-11-25 22:24:59 -0800[diff] [blame]62 /* When returning from a NMI (%pil==15) interrupt we want to
63 * avoid running softirqs, doing IRQ tracing, preempting, etc.
64 */
65 .globl rtrap_nmi
66rtrap_nmi: ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
67 sethi %hi(0xf << 20), %l4
68 and %l1, %l4, %l4
69 andn %l1, %l4, %l1
70 srl %l4, 20, %l4
71 ba,pt %xcc, rtrap_no_irq_enable
Rob Gardner1ca04a42015-12-21 21:48:03 -0700[diff] [blame]72 nop
73 /* Do not actually set the %pil here. We will do that
74 * below after we clear PSTATE_IE in the %pstate register.
75 * If we re-enable interrupts here, we can recurse down
76 * the hardirq stack potentially endlessly, causing a
77 * stack overflow.
78 */
David S. Miller55657362008-11-25 22:24:59 -0800[diff] [blame]79
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]80 .align 64
David S. Miller7697daa2008-04-24 03:15:22 -0700[diff] [blame]81 .globl rtrap_irq, rtrap, irqsz_patchme, rtrap_xcall
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]82rtrap_irq:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]83rtrap:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]84 /* mm/ultra.S:xcall_report_regs KNOWS about this load. */
David S. Miller78b7e3d2012-04-13 13:56:46 -0700[diff] [blame]85 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]86rtrap_xcall:
87 sethi %hi(0xf << 20), %l4
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]88 and %l1, %l4, %l4
David S. Miller10e26722006-11-16 13:38:57 -0800[diff] [blame]89 andn %l1, %l4, %l1
90 srl %l4, 20, %l4
91#ifdef CONFIG_TRACE_IRQFLAGS
92 brnz,pn %l4, rtrap_no_irq_enable
93 nop
94 call trace_hardirqs_on
95 nop
David S. Miller28a1f532010-04-20 00:48:37 -0700[diff] [blame]96 /* Do not actually set the %pil here. We will do that
97 * below after we clear PSTATE_IE in the %pstate register.
98 * If we re-enable interrupts here, we can recurse down
99 * the hardirq stack potentially endlessly, causing a
100 * stack overflow.
101 *
102 * It is tempting to put this test and trace_hardirqs_on
103 * call at the 'rt_continue' label, but that will not work
104 * as that path hits unconditionally and we do not want to
105 * execute this in NMI return paths, for example.
106 */
David S. Miller10e26722006-11-16 13:38:57 -0800[diff] [blame]107#endif
David S. Miller55657362008-11-25 22:24:59 -0800[diff] [blame]108rtrap_no_irq_enable:
David S. Miller10e26722006-11-16 13:38:57 -0800[diff] [blame]109 andcc %l1, TSTATE_PRIV, %l3
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]110 bne,pn %icc, to_kernel
David S. Miller10e26722006-11-16 13:38:57 -0800[diff] [blame]111 nop
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]112
113 /* We must hold IRQs off and atomically test schedule+signal
114 * state, then hold them off all the way back to userspace.
David S. Miller10e26722006-11-16 13:38:57 -0800[diff] [blame]115 * If we are returning to kernel, none of this matters. Note
116 * that we are disabling interrupts via PSTATE_IE, not using
117 * %pil.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]118 *
119 * If we do not do this, there is a window where we would do
120 * the tests, later the signal/resched event arrives but we do
121 * not process it since we are still in kernel mode. It would
122 * take until the next local IRQ before the signal/resched
123 * event would be handled.
124 *
David S. Millerc7d5a002010-03-03 08:08:49 -0800[diff] [blame]125 * This also means that if we have to deal with user
126 * windows, we have to redo all of these sched+signal checks
127 * with IRQs disabled.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]128 */
129to_user: wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
130 wrpr 0, %pil
131__handle_preemption_continue:
132 ldx [%g6 + TI_FLAGS], %l0
133 sethi %hi(_TIF_USER_WORK_MASK), %o0
134 or %o0, %lo(_TIF_USER_WORK_MASK), %o0
135 andcc %l0, %o0, %g0
136 sethi %hi(TSTATE_PEF), %o0
137 be,pt %xcc, user_nowork
138 andcc %l1, %o0, %g0
139 andcc %l0, _TIF_NEED_RESCHED, %g0
140 bne,pn %xcc, __handle_preemption
Roland McGrathe35a8922008-04-20 15:06:49 -0700[diff] [blame]141 andcc %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]142 bne,pn %xcc, __handle_signal
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]143 ldub [%g6 + TI_WSAVED], %o2
144 brnz,pn %o2, __handle_user_windows
145 nop
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]146 sethi %hi(TSTATE_PEF), %o0
David S. Millerc7d5a002010-03-03 08:08:49 -0800[diff] [blame]147 andcc %l1, %o0, %g0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]148
149 /* This fpdepth clear is necessary for non-syscall rtraps only */
150user_nowork:
151 bne,pn %xcc, __handle_userfpu
152 stb %g0, [%g6 + TI_FPDEPTH]
153__handle_userfpu_continue:
154
155rt_continue: ldx [%sp + PTREGS_OFF + PT_V9_G1], %g1
156 ldx [%sp + PTREGS_OFF + PT_V9_G2], %g2
157
158 ldx [%sp + PTREGS_OFF + PT_V9_G3], %g3
159 ldx [%sp + PTREGS_OFF + PT_V9_G4], %g4
160 ldx [%sp + PTREGS_OFF + PT_V9_G5], %g5
David S. Miller56fb4df2006-02-26 23:24:22 -0800[diff] [blame]161 brz,pt %l3, 1f
David S. Miller314981a2006-02-05 21:59:03 -0800[diff] [blame]162 mov %g6, %l2
163
David S. Miller56fb4df2006-02-26 23:24:22 -0800[diff] [blame]164 /* Must do this before thread reg is clobbered below. */
David S. Millerffe483d2006-02-02 21:55:10 -0800[diff] [blame]165 LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
David S. Miller74bf4312006-01-31 18:29:18 -0800[diff] [blame]1661:
167 ldx [%sp + PTREGS_OFF + PT_V9_G6], %g6
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]168 ldx [%sp + PTREGS_OFF + PT_V9_G7], %g7
David S. Miller936f4822006-02-05 21:29:28 -0800[diff] [blame]169
170 /* Normal globals are restored, go to trap globals. */
171661: wrpr %g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
David S. Milleraf02bec2006-02-16 16:23:45 -0800[diff] [blame]172 nop
173 .section .sun4v_2insn_patch, "ax"
David S. Miller936f4822006-02-05 21:29:28 -0800[diff] [blame]174 .word 661b
David S. Milleraf02bec2006-02-16 16:23:45 -0800[diff] [blame]175 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
David S. Miller936f4822006-02-05 21:29:28 -0800[diff] [blame]176 SET_GL(1)
177 .previous
178
David S. Miller314981a2006-02-05 21:59:03 -0800[diff] [blame]179 mov %l2, %g6
180
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]181 ldx [%sp + PTREGS_OFF + PT_V9_I0], %i0
182 ldx [%sp + PTREGS_OFF + PT_V9_I1], %i1
183
184 ldx [%sp + PTREGS_OFF + PT_V9_I2], %i2
185 ldx [%sp + PTREGS_OFF + PT_V9_I3], %i3
186 ldx [%sp + PTREGS_OFF + PT_V9_I4], %i4
187 ldx [%sp + PTREGS_OFF + PT_V9_I5], %i5
188 ldx [%sp + PTREGS_OFF + PT_V9_I6], %i6
189 ldx [%sp + PTREGS_OFF + PT_V9_I7], %i7
190 ldx [%sp + PTREGS_OFF + PT_V9_TPC], %l2
191 ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %o2
192
193 ld [%sp + PTREGS_OFF + PT_V9_Y], %o3
194 wr %o3, %g0, %y
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]195 wrpr %l4, 0x0, %pil
196 wrpr %g0, 0x1, %tl
David S. Miller28e61032008-05-11 02:07:19 -0700[diff] [blame]197 andn %l1, TSTATE_SYSCALL, %l1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]198 wrpr %l1, %g0, %tstate
199 wrpr %l2, %g0, %tpc
200 wrpr %o2, %g0, %tnpc
201
202 brnz,pn %l3, kern_rtt
203 mov PRIMARY_CONTEXT, %l7
David S. Miller8b11bd12006-02-07 22:13:05 -0800[diff] [blame]204
205661: ldxa [%l7 + %l7] ASI_DMMU, %l0
206 .section .sun4v_1insn_patch, "ax"
207 .word 661b
208 ldxa [%l7 + %l7] ASI_MMU, %l0
209 .previous
210
David S. Miller0835ae02005-10-04 15:23:20 -0700[diff] [blame]211 sethi %hi(sparc64_kern_pri_nuc_bits), %l1
212 ldx [%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]213 or %l0, %l1, %l0
David S. Miller8b11bd12006-02-07 22:13:05 -0800[diff] [blame]214
215661: stxa %l0, [%l7] ASI_DMMU
216 .section .sun4v_1insn_patch, "ax"
217 .word 661b
218 stxa %l0, [%l7] ASI_MMU
219 .previous
220
David S. Miller4da808c2006-01-31 18:33:00 -0800[diff] [blame]221 sethi %hi(KERNBASE), %l7
222 flush %l7
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]223 rdpr %wstate, %l1
224 rdpr %otherwin, %l2
225 srl %l1, 3, %l1
226
227 wrpr %l2, %g0, %canrestore
228 wrpr %l1, %g0, %wstate
David S. Miller314ef682006-02-04 00:10:01 -0800[diff] [blame]229 brnz,pt %l2, user_rtt_restore
230 wrpr %g0, %g0, %otherwin
231
232 ldx [%g6 + TI_FLAGS], %g3
233 wr %g0, ASI_AIUP, %asi
234 rdpr %cwp, %g1
235 andcc %g3, _TIF_32BIT, %g0
236 sub %g1, 1, %g1
237 bne,pt %xcc, user_rtt_fill_32bit
238 wrpr %g1, %cwp
239 ba,a,pt %xcc, user_rtt_fill_64bit
Babu Moger0ae2d262017-03-17 14:52:21 -0600[diff] [blame]240 nop
David S. Miller314ef682006-02-04 00:10:01 -0800[diff] [blame]241
David S. Miller7cafc0b2016-05-28 20:41:12 -0700[diff] [blame]242user_rtt_fill_fixup_dax:
243 ba,pt %xcc, user_rtt_fill_fixup_common
244 mov 1, %g3
245
246user_rtt_fill_fixup_mna:
247 ba,pt %xcc, user_rtt_fill_fixup_common
248 mov 2, %g3
249
David S. Miller314ef682006-02-04 00:10:01 -0800[diff] [blame]250user_rtt_fill_fixup:
David S. Miller7cafc0b2016-05-28 20:41:12 -0700[diff] [blame]251 ba,pt %xcc, user_rtt_fill_fixup_common
252 clr %g3
David S. Miller314ef682006-02-04 00:10:01 -0800[diff] [blame]253
254user_rtt_pre_restore:
255 add %g1, 1, %g1
256 wrpr %g1, 0x0, %cwp
257
258user_rtt_restore:
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]259 restore
260 rdpr %canrestore, %g1
261 wrpr %g1, 0x0, %cleanwin
262 retry
263 nop
264
David S. Miller314ef682006-02-04 00:10:01 -0800[diff] [blame]265kern_rtt: rdpr %canrestore, %g1
266 brz,pn %g1, kern_rtt_fill
267 nop
268kern_rtt_restore:
David S. Millerada44a02008-05-21 21:50:01 -0700[diff] [blame]269 stw %g0, [%sp + PTREGS_OFF + PT_V9_MAGIC]
David S. Miller314ef682006-02-04 00:10:01 -0800[diff] [blame]270 restore
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]271 retry
David S. Miller314ef682006-02-04 00:10:01 -0800[diff] [blame]272
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]273to_kernel:
274#ifdef CONFIG_PREEMPT
275 ldsw [%g6 + TI_PRE_COUNT], %l5
276 brnz %l5, kern_fpucheck
277 ldx [%g6 + TI_FLAGS], %l5
278 andcc %l5, _TIF_NEED_RESCHED, %g0
279 be,pt %xcc, kern_fpucheck
David S. Miller10e26722006-11-16 13:38:57 -0800[diff] [blame]280 nop
281 cmp %l4, 0
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]282 bne,pn %xcc, kern_fpucheck
Thomas Gleixner9385d942013-09-17 18:53:08 +0000[diff] [blame]283 nop
284 call preempt_schedule_irq
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]285 nop
286 ba,pt %xcc, rtrap
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]287#endif
288kern_fpucheck: ldub [%g6 + TI_FPDEPTH], %l5
289 brz,pt %l5, rt_continue
290 srl %l5, 1, %o0
291 add %g6, TI_FPSAVED, %l6
292 ldub [%l6 + %o0], %l2
293 sub %l5, 2, %l5
294
295 add %g6, TI_GSR, %o1
296 andcc %l2, (FPRS_FEF|FPRS_DU), %g0
297 be,pt %icc, 2f
298 and %l2, FPRS_DL, %l6
299 andcc %l2, FPRS_FEF, %g0
300 be,pn %icc, 5f
301 sll %o0, 3, %o5
302 rd %fprs, %g1
303
304 wr %g1, FPRS_FEF, %fprs
305 ldx [%o1 + %o5], %g1
306 add %g6, TI_XFSR, %o1
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]307 sll %o0, 8, %o2
308 add %g6, TI_FPREGS, %o3
309 brz,pn %l6, 1f
310 add %g6, TI_FPREGS+0x40, %o4
311
David S. Millerba6399332005-10-07 13:30:49 -0700[diff] [blame]312 membar #Sync
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]313 ldda [%o3 + %o2] ASI_BLK_P, %f0
314 ldda [%o4 + %o2] ASI_BLK_P, %f16
David S. Millerba6399332005-10-07 13:30:49 -0700[diff] [blame]315 membar #Sync
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]3161: andcc %l2, FPRS_DU, %g0
317 be,pn %icc, 1f
318 wr %g1, 0, %gsr
319 add %o2, 0x80, %o2
David S. Millerba6399332005-10-07 13:30:49 -0700[diff] [blame]320 membar #Sync
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]321 ldda [%o3 + %o2] ASI_BLK_P, %f32
322 ldda [%o4 + %o2] ASI_BLK_P, %f48
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]3231: membar #Sync
324 ldx [%o1 + %o5], %fsr
3252: stb %l5, [%g6 + TI_FPDEPTH]
326 ba,pt %xcc, rt_continue
327 nop
3285: wr %g0, FPRS_FEF, %fprs
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]329 sll %o0, 8, %o2
330
331 add %g6, TI_FPREGS+0x80, %o3
332 add %g6, TI_FPREGS+0xc0, %o4
David S. Millerba6399332005-10-07 13:30:49 -0700[diff] [blame]333 membar #Sync
Linus Torvalds1da177e2005-04-16 15:20:36 -0700[diff] [blame]334 ldda [%o3 + %o2] ASI_BLK_P, %f32
335 ldda [%o4 + %o2] ASI_BLK_P, %f48
336 membar #Sync
337 wr %g0, FPRS_DU, %fprs
338 ba,pt %xcc, rt_continue
339 stb %l5, [%g6 + TI_FPDEPTH]