Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 1 | /* |
| 2 | * arch/arm/mach-at91/include/mach/at91sam9_smc.h |
| 3 | * |
Andrew Victor | 3d73e89 | 2008-09-18 21:44:20 +0100 | [diff] [blame] | 4 | * Copyright (C) 2007 Andrew Victor |
| 5 | * Copyright (C) 2007 Atmel Corporation. |
| 6 | * |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 7 | * Static Memory Controllers (SMC) - System peripherals registers. |
| 8 | * Based on AT91SAM9261 datasheet revision D. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; either version 2 of the License, or |
| 13 | * (at your option) any later version. |
| 14 | */ |
| 15 | |
| 16 | #ifndef AT91SAM9_SMC_H |
| 17 | #define AT91SAM9_SMC_H |
| 18 | |
Jean-Christophe PLAGNIOL-VILLARD | faee0cc | 2011-10-14 01:37:09 +0800 | [diff] [blame] | 19 | #include <mach/cpu.h> |
| 20 | |
Jean-Christophe PLAGNIOL-VILLARD | 59594e13 | 2011-11-27 19:29:57 +0800 | [diff] [blame] | 21 | #ifndef __ASSEMBLY__ |
| 22 | struct sam9_smc_config { |
| 23 | /* Setup register */ |
| 24 | u8 ncs_read_setup; |
| 25 | u8 nrd_setup; |
| 26 | u8 ncs_write_setup; |
| 27 | u8 nwe_setup; |
| 28 | |
| 29 | /* Pulse register */ |
| 30 | u8 ncs_read_pulse; |
| 31 | u8 nrd_pulse; |
| 32 | u8 ncs_write_pulse; |
| 33 | u8 nwe_pulse; |
| 34 | |
| 35 | /* Cycle register */ |
| 36 | u16 read_cycle; |
| 37 | u16 write_cycle; |
| 38 | |
| 39 | /* Mode register */ |
| 40 | u32 mode; |
| 41 | u8 tdf_cycles:4; |
| 42 | }; |
| 43 | |
| 44 | extern void sam9_smc_configure(int id, int cs, struct sam9_smc_config *config); |
| 45 | extern void sam9_smc_read(int id, int cs, struct sam9_smc_config *config); |
| 46 | extern void sam9_smc_read_mode(int id, int cs, struct sam9_smc_config *config); |
| 47 | extern void sam9_smc_write_mode(int id, int cs, struct sam9_smc_config *config); |
| 48 | #endif |
| 49 | |
Jean-Christophe PLAGNIOL-VILLARD | faee0cc | 2011-10-14 01:37:09 +0800 | [diff] [blame] | 50 | #define AT91_SMC_SETUP 0x00 /* Setup Register for CS n */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 51 | #define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */ |
| 52 | #define AT91_SMC_NWESETUP_(x) ((x) << 0) |
| 53 | #define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */ |
| 54 | #define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8) |
| 55 | #define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */ |
| 56 | #define AT91_SMC_NRDSETUP_(x) ((x) << 16) |
| 57 | #define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */ |
| 58 | #define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24) |
| 59 | |
Jean-Christophe PLAGNIOL-VILLARD | faee0cc | 2011-10-14 01:37:09 +0800 | [diff] [blame] | 60 | #define AT91_SMC_PULSE 0x04 /* Pulse Register for CS n */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 61 | #define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */ |
| 62 | #define AT91_SMC_NWEPULSE_(x) ((x) << 0) |
| 63 | #define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */ |
| 64 | #define AT91_SMC_NCS_WRPULSE_(x)((x) << 8) |
| 65 | #define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */ |
| 66 | #define AT91_SMC_NRDPULSE_(x) ((x) << 16) |
| 67 | #define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */ |
| 68 | #define AT91_SMC_NCS_RDPULSE_(x)((x) << 24) |
| 69 | |
Jean-Christophe PLAGNIOL-VILLARD | faee0cc | 2011-10-14 01:37:09 +0800 | [diff] [blame] | 70 | #define AT91_SMC_CYCLE 0x08 /* Cycle Register for CS n */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 71 | #define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */ |
| 72 | #define AT91_SMC_NWECYCLE_(x) ((x) << 0) |
| 73 | #define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */ |
| 74 | #define AT91_SMC_NRDCYCLE_(x) ((x) << 16) |
| 75 | |
Jean-Christophe PLAGNIOL-VILLARD | faee0cc | 2011-10-14 01:37:09 +0800 | [diff] [blame] | 76 | #define AT91_SMC_MODE 0x0c /* Mode Register for CS n */ |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 77 | #define AT91_SMC_READMODE (1 << 0) /* Read Mode */ |
| 78 | #define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */ |
| 79 | #define AT91_SMC_EXNWMODE (3 << 4) /* NWAIT Mode */ |
| 80 | #define AT91_SMC_EXNWMODE_DISABLE (0 << 4) |
| 81 | #define AT91_SMC_EXNWMODE_FROZEN (2 << 4) |
| 82 | #define AT91_SMC_EXNWMODE_READY (3 << 4) |
| 83 | #define AT91_SMC_BAT (1 << 8) /* Byte Access Type */ |
| 84 | #define AT91_SMC_BAT_SELECT (0 << 8) |
| 85 | #define AT91_SMC_BAT_WRITE (1 << 8) |
| 86 | #define AT91_SMC_DBW (3 << 12) /* Data Bus Width */ |
| 87 | #define AT91_SMC_DBW_8 (0 << 12) |
| 88 | #define AT91_SMC_DBW_16 (1 << 12) |
| 89 | #define AT91_SMC_DBW_32 (2 << 12) |
| 90 | #define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */ |
| 91 | #define AT91_SMC_TDF_(x) ((x) << 16) |
| 92 | #define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */ |
| 93 | #define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */ |
| 94 | #define AT91_SMC_PS (3 << 28) /* Page Size */ |
| 95 | #define AT91_SMC_PS_4 (0 << 28) |
| 96 | #define AT91_SMC_PS_8 (1 << 28) |
| 97 | #define AT91_SMC_PS_16 (2 << 28) |
| 98 | #define AT91_SMC_PS_32 (3 << 28) |
| 99 | |
Russell King | a09e64f | 2008-08-05 16:14:15 +0100 | [diff] [blame] | 100 | #endif |