blob: 64765474676f6ddd37f893cac1be69d1c07bed91 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
David Brownell75862692005-09-23 17:14:37 -070010 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
12 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070013 * The bridge optimization stuff has been removed. If you really
14 * have a silly BIOS which is unable to set your host bridge right,
15 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
16 */
17
Linus Torvalds1da177e2005-04-16 15:20:36 -070018#include <linux/types.h>
19#include <linux/kernel.h>
Paul Gortmaker363c75d2011-05-27 09:37:25 -040020#include <linux/export.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070021#include <linux/pci.h>
22#include <linux/init.h>
23#include <linux/delay.h>
Len Brown25be5e62005-05-27 04:21:50 -040024#include <linux/acpi.h>
bjorn.helgaas@hp.com9f23ed32007-12-17 14:09:38 -070025#include <linux/kallsyms.h>
Andreas Petlund75e07fc2008-11-20 20:42:25 -080026#include <linux/dmi.h>
Alexander Duyck649426e2009-03-05 13:57:28 -050027#include <linux/pci-aspm.h>
Yuji Shimada32a9a6822009-03-16 17:13:39 +090028#include <linux/ioport.h>
Rafael J. Wysocki93177a72010-01-02 22:57:24 +010029#include <asm/dma.h> /* isa_dma_bridge_buggy */
Greg KHbc56b9e2005-04-08 14:53:31 +090030#include "pci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070031
Yuji Shimada32a9a6822009-03-16 17:13:39 +090032/*
Yuji Shimada0cdbe302009-04-06 10:24:21 +090033 * This quirk function disables memory decoding and releases memory resources
34 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
Yuji Shimada32a9a6822009-03-16 17:13:39 +090035 * It also rounds up size to specified alignment.
36 * Later on, the kernel will assign page-aligned memory resource back
Yuji Shimada0cdbe302009-04-06 10:24:21 +090037 * to the device.
Yuji Shimada32a9a6822009-03-16 17:13:39 +090038 */
39static void __devinit quirk_resource_alignment(struct pci_dev *dev)
40{
41 int i;
42 struct resource *r;
43 resource_size_t align, size;
Yuji Shimada0cdbe302009-04-06 10:24:21 +090044 u16 command;
Yuji Shimada32a9a6822009-03-16 17:13:39 +090045
46 if (!pci_is_reassigndev(dev))
47 return;
48
49 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
50 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
51 dev_warn(&dev->dev,
52 "Can't reassign resources to host bridge.\n");
53 return;
54 }
55
Yuji Shimada0cdbe302009-04-06 10:24:21 +090056 dev_info(&dev->dev,
57 "Disabling memory decoding and releasing memory resources.\n");
58 pci_read_config_word(dev, PCI_COMMAND, &command);
59 command &= ~PCI_COMMAND_MEMORY;
60 pci_write_config_word(dev, PCI_COMMAND, command);
Yuji Shimada32a9a6822009-03-16 17:13:39 +090061
62 align = pci_specified_resource_alignment(dev);
63 for (i=0; i < PCI_BRIDGE_RESOURCES; i++) {
64 r = &dev->resource[i];
65 if (!(r->flags & IORESOURCE_MEM))
66 continue;
67 size = resource_size(r);
68 if (size < align) {
69 size = align;
70 dev_info(&dev->dev,
71 "Rounding up size of resource #%d to %#llx.\n",
72 i, (unsigned long long)size);
73 }
74 r->end = size - 1;
75 r->start = 0;
76 }
77 /* Need to disable bridge's resource window,
78 * to enable the kernel to reassign new resource
79 * window later on.
80 */
81 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
82 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
83 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
84 r = &dev->resource[i];
85 if (!(r->flags & IORESOURCE_MEM))
86 continue;
87 r->end = resource_size(r) - 1;
88 r->start = 0;
89 }
90 pci_disable_bridge_window(dev);
91 }
92}
93DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_resource_alignment);
94
Jacob Pan253d2e52010-07-16 10:19:22 -070095/*
96 * Decoding should be disabled for a PCI device during BAR sizing to avoid
97 * conflict. But doing so may cause problems on host bridge and perhaps other
98 * key system devices. For devices that need to have mmio decoding always-on,
99 * we need to set the dev->mmio_always_on bit.
100 */
101static void __devinit quirk_mmio_always_on(struct pci_dev *dev)
102{
103 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
104 dev->mmio_always_on = 1;
105}
106DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_mmio_always_on);
107
Doug Thompsonbd8481e2006-05-08 17:06:09 -0700108/* The Mellanox Tavor device gives false positive parity errors
109 * Mark this device with a broken_parity_status, to allow
110 * PCI scanning code to "skip" this now blacklisted device.
111 */
112static void __devinit quirk_mellanox_tavor(struct pci_dev *dev)
113{
114 dev->broken_parity_status = 1; /* This device gives false positives */
115}
116DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR,quirk_mellanox_tavor);
117DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX,PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE,quirk_mellanox_tavor);
118
Linus Torvalds1da177e2005-04-16 15:20:36 -0700119/* Deal with broken BIOS'es that neglect to enable passive release,
120 which can cause problems in combination with the 82441FX/PPro MTRRs */
Alan Cox1597cac2006-12-04 15:14:45 -0800121static void quirk_passive_release(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700122{
123 struct pci_dev *d = NULL;
124 unsigned char dlc;
125
126 /* We have to make sure a particular bit is set in the PIIX3
127 ISA bridge, so we have to go out and find it. */
128 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
129 pci_read_config_byte(d, 0x82, &dlc);
130 if (!(dlc & 1<<1)) {
Adam Jackson999da9f2008-12-01 14:30:29 -0800131 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700132 dlc |= 1<<1;
133 pci_write_config_byte(d, 0x82, dlc);
134 }
135 }
136}
Andrew Morton652c5382007-11-21 15:07:13 -0800137DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
138DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700139
140/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
141 but VIA don't answer queries. If you happen to have good contacts at VIA
142 ask them for me please -- Alan
143
144 This appears to be BIOS not version dependent. So presumably there is a
145 chipset level fix */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700146
147static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
148{
149 if (!isa_dma_bridge_buggy) {
150 isa_dma_bridge_buggy=1;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700151 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700152 }
153}
154 /*
155 * Its not totally clear which chipsets are the problematic ones
156 * We know 82C586 and 82C596 variants are affected.
157 */
Andrew Morton652c5382007-11-21 15:07:13 -0800158DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
159DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
161DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
162DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
163DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
164DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700165
Linus Torvalds1da177e2005-04-16 15:20:36 -0700166/*
Len Brown4731fdc2010-09-24 21:02:27 -0400167 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
168 * for some HT machines to use C4 w/o hanging.
169 */
170static void __devinit quirk_tigerpoint_bm_sts(struct pci_dev *dev)
171{
172 u32 pmbase;
173 u16 pm1a;
174
175 pci_read_config_dword(dev, 0x40, &pmbase);
176 pmbase = pmbase & 0xff80;
177 pm1a = inw(pmbase);
178
179 if (pm1a & 0x10) {
180 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
181 outw(0x10, pmbase);
182 }
183}
184DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
185
186/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700187 * Chipsets where PCI->PCI transfers vanish or hang
188 */
189static void __devinit quirk_nopcipci(struct pci_dev *dev)
190{
191 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700192 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700193 pci_pci_problems |= PCIPCI_FAIL;
194 }
195}
Andrew Morton652c5382007-11-21 15:07:13 -0800196DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
197DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
Alan Cox236561e2006-09-30 23:27:03 -0700198
199static void __devinit quirk_nopciamd(struct pci_dev *dev)
200{
201 u8 rev;
202 pci_read_config_byte(dev, 0x08, &rev);
203 if (rev == 0x13) {
204 /* Erratum 24 */
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700205 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
Alan Cox236561e2006-09-30 23:27:03 -0700206 pci_pci_problems |= PCIAGP_FAIL;
207 }
208}
Andrew Morton652c5382007-11-21 15:07:13 -0800209DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700210
211/*
212 * Triton requires workarounds to be used by the drivers
213 */
214static void __devinit quirk_triton(struct pci_dev *dev)
215{
216 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700217 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700218 pci_pci_problems |= PCIPCI_TRITON;
219 }
220}
Andrew Morton652c5382007-11-21 15:07:13 -0800221DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
222DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
223DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
224DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700225
226/*
227 * VIA Apollo KT133 needs PCI latency patch
228 * Made according to a windows driver based patch by George E. Breese
229 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
Justin P. Mattock631dd1a2010-10-18 11:03:14 +0200230 * and http://www.georgebreese.com/net/software/#PCI
Linus Torvalds1da177e2005-04-16 15:20:36 -0700231 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
232 * the info on which Mr Breese based his work.
233 *
234 * Updated based on further information from the site and also on
235 * information provided by VIA
236 */
Alan Cox1597cac2006-12-04 15:14:45 -0800237static void quirk_vialatency(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700238{
239 struct pci_dev *p;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700240 u8 busarb;
241 /* Ok we have a potential problem chipset here. Now see if we have
242 a buggy southbridge */
243
244 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
245 if (p!=NULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700246 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
247 /* Check for buggy part revisions */
Auke Kok2b1afa82007-10-29 14:55:02 -0700248 if (p->revision < 0x40 || p->revision > 0x42)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700249 goto exit;
250 } else {
251 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
252 if (p==NULL) /* No problem parts */
253 goto exit;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700254 /* Check for buggy part revisions */
Auke Kok2b1afa82007-10-29 14:55:02 -0700255 if (p->revision < 0x10 || p->revision > 0x12)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700256 goto exit;
257 }
258
259 /*
260 * Ok we have the problem. Now set the PCI master grant to
261 * occur every master grant. The apparent bug is that under high
262 * PCI load (quite common in Linux of course) you can get data
263 * loss when the CPU is held off the bus for 3 bus master requests
264 * This happens to include the IDE controllers....
265 *
266 * VIA only apply this fix when an SB Live! is present but under
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300267 * both Linux and Windows this isn't enough, and we have seen
Linus Torvalds1da177e2005-04-16 15:20:36 -0700268 * corruption without SB Live! but with things like 3 UDMA IDE
269 * controllers. So we ignore that bit of the VIA recommendation..
270 */
271
272 pci_read_config_byte(dev, 0x76, &busarb);
273 /* Set bit 4 and bi 5 of byte 76 to 0x01
274 "Master priority rotation on every PCI master grant */
275 busarb &= ~(1<<5);
276 busarb |= (1<<4);
277 pci_write_config_byte(dev, 0x76, busarb);
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700278 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700279exit:
280 pci_dev_put(p);
281}
Andrew Morton652c5382007-11-21 15:07:13 -0800282DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
283DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
284DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
Alan Cox1597cac2006-12-04 15:14:45 -0800285/* Must restore this on a resume from RAM */
Andrew Morton652c5382007-11-21 15:07:13 -0800286DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
287DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
288DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700289
290/*
291 * VIA Apollo VP3 needs ETBF on BT848/878
292 */
293static void __devinit quirk_viaetbf(struct pci_dev *dev)
294{
295 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700296 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700297 pci_pci_problems |= PCIPCI_VIAETBF;
298 }
299}
Andrew Morton652c5382007-11-21 15:07:13 -0800300DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700301
302static void __devinit quirk_vsfx(struct pci_dev *dev)
303{
304 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700305 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700306 pci_pci_problems |= PCIPCI_VSFX;
307 }
308}
Andrew Morton652c5382007-11-21 15:07:13 -0800309DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700310
311/*
312 * Ali Magik requires workarounds to be used by the drivers
313 * that DMA to AGP space. Latency must be set to 0xA and triton
314 * workaround applied too
315 * [Info kindly provided by ALi]
316 */
317static void __init quirk_alimagik(struct pci_dev *dev)
318{
319 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700320 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700321 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
322 }
323}
Andrew Morton652c5382007-11-21 15:07:13 -0800324DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
325DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700326
327/*
328 * Natoma has some interesting boundary conditions with Zoran stuff
329 * at least
330 */
331static void __devinit quirk_natoma(struct pci_dev *dev)
332{
333 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700334 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700335 pci_pci_problems |= PCIPCI_NATOMA;
336 }
337}
Andrew Morton652c5382007-11-21 15:07:13 -0800338DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
339DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
340DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
341DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
342DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
343DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700344
345/*
346 * This chip can cause PCI parity errors if config register 0xA0 is read
347 * while DMAs are occurring.
348 */
349static void __devinit quirk_citrine(struct pci_dev *dev)
350{
351 dev->cfg_size = 0xA0;
352}
Andrew Morton652c5382007-11-21 15:07:13 -0800353DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700354
355/*
356 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
357 * If it's needed, re-allocate the region.
358 */
359static void __devinit quirk_s3_64M(struct pci_dev *dev)
360{
361 struct resource *r = &dev->resource[0];
362
363 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
364 r->start = 0;
365 r->end = 0x3ffffff;
366 }
367}
Andrew Morton652c5382007-11-21 15:07:13 -0800368DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
369DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700370
Andres Salomon73d2eaa2010-02-05 01:42:43 -0500371/*
372 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
373 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
374 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
375 * (which conflicts w/ BAR1's memory range).
376 */
377static void __devinit quirk_cs5536_vsa(struct pci_dev *dev)
378{
379 if (pci_resource_len(dev, 0) != 8) {
380 struct resource *res = &dev->resource[0];
381 res->end = res->start + 8 - 1;
382 dev_info(&dev->dev, "CS5536 ISA bridge bug detected "
383 "(incorrect header); workaround applied.\n");
384 }
385}
386DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
387
Linus Torvalds6693e742005-10-25 20:40:09 -0700388static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region,
389 unsigned size, int nr, const char *name)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700390{
391 region &= ~(size-1);
392 if (region) {
David S. Miller085ae412005-08-08 13:19:08 -0700393 struct pci_bus_region bus_region;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700394 struct resource *res = dev->resource + nr;
395
396 res->name = pci_name(dev);
397 res->start = region;
398 res->end = region + size - 1;
399 res->flags = IORESOURCE_IO;
David S. Miller085ae412005-08-08 13:19:08 -0700400
401 /* Convert from PCI bus to resource space. */
402 bus_region.start = res->start;
403 bus_region.end = res->end;
404 pcibios_bus_to_resource(dev, res, &bus_region);
405
Bjorn Helgaasf967a442010-03-22 16:34:05 -0600406 if (pci_claim_resource(dev, nr) == 0)
407 dev_info(&dev->dev, "quirk: %pR claimed by %s\n",
408 res, name);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700409 }
410}
411
412/*
413 * ATI Northbridge setups MCE the processor if you even
414 * read somewhere between 0x3b0->0x3bb or read 0x3d3
415 */
416static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
417{
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700418 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700419 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
420 request_region(0x3b0, 0x0C, "RadeonIGP");
421 request_region(0x3d3, 0x01, "RadeonIGP");
422}
Andrew Morton652c5382007-11-21 15:07:13 -0800423DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700424
425/*
426 * Let's make the southbridge information explicit instead
427 * of having to worry about people probing the ACPI areas,
428 * for example.. (Yes, it happens, and if you read the wrong
429 * ACPI register it will put the machine to sleep with no
430 * way of waking it up again. Bummer).
431 *
432 * ALI M7101: Two IO regions pointed to by words at
433 * 0xE0 (64 bytes of ACPI registers)
434 * 0xE2 (32 bytes of SMB registers)
435 */
436static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
437{
438 u16 region;
439
440 pci_read_config_word(dev, 0xE0, &region);
Linus Torvalds6693e742005-10-25 20:40:09 -0700441 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700442 pci_read_config_word(dev, 0xE2, &region);
Linus Torvalds6693e742005-10-25 20:40:09 -0700443 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700444}
Andrew Morton652c5382007-11-21 15:07:13 -0800445DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700446
Linus Torvalds6693e742005-10-25 20:40:09 -0700447static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
448{
449 u32 devres;
450 u32 mask, size, base;
451
452 pci_read_config_dword(dev, port, &devres);
453 if ((devres & enable) != enable)
454 return;
455 mask = (devres >> 16) & 15;
456 base = devres & 0xffff;
457 size = 16;
458 for (;;) {
459 unsigned bit = size >> 1;
460 if ((bit & mask) == bit)
461 break;
462 size = bit;
463 }
464 /*
465 * For now we only print it out. Eventually we'll want to
466 * reserve it (at least if it's in the 0x1000+ range), but
467 * let's get enough confirmation reports first.
468 */
469 base &= -size;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700470 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
Linus Torvalds6693e742005-10-25 20:40:09 -0700471}
472
473static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
474{
475 u32 devres;
476 u32 mask, size, base;
477
478 pci_read_config_dword(dev, port, &devres);
479 if ((devres & enable) != enable)
480 return;
481 base = devres & 0xffff0000;
482 mask = (devres & 0x3f) << 16;
483 size = 128 << 16;
484 for (;;) {
485 unsigned bit = size >> 1;
486 if ((bit & mask) == bit)
487 break;
488 size = bit;
489 }
490 /*
491 * For now we only print it out. Eventually we'll want to
492 * reserve it, but let's get enough confirmation reports first.
493 */
494 base &= -size;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700495 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
Linus Torvalds6693e742005-10-25 20:40:09 -0700496}
497
Linus Torvalds1da177e2005-04-16 15:20:36 -0700498/*
499 * PIIX4 ACPI: Two IO regions pointed to by longwords at
500 * 0x40 (64 bytes of ACPI registers)
Linus Torvalds08db2a72005-10-30 14:40:07 -0800501 * 0x90 (16 bytes of SMB registers)
Linus Torvalds6693e742005-10-25 20:40:09 -0700502 * and a few strange programmable PIIX4 device resources.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700503 */
504static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
505{
Linus Torvalds6693e742005-10-25 20:40:09 -0700506 u32 region, res_a;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700507
508 pci_read_config_dword(dev, 0x40, &region);
Linus Torvalds6693e742005-10-25 20:40:09 -0700509 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700510 pci_read_config_dword(dev, 0x90, &region);
Linus Torvalds08db2a72005-10-30 14:40:07 -0800511 quirk_io_region(dev, region, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
Linus Torvalds6693e742005-10-25 20:40:09 -0700512
513 /* Device resource A has enables for some of the other ones */
514 pci_read_config_dword(dev, 0x5c, &res_a);
515
516 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
517 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
518
519 /* Device resource D is just bitfields for static resources */
520
521 /* Device 12 enabled? */
522 if (res_a & (1 << 29)) {
523 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
524 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
525 }
526 /* Device 13 enabled? */
527 if (res_a & (1 << 30)) {
528 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
529 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
530 }
531 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
532 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700533}
Andrew Morton652c5382007-11-21 15:07:13 -0800534DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
535DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700536
Jiri Slabycdb97552011-02-28 10:45:09 +0100537#define ICH_PMBASE 0x40
538#define ICH_ACPI_CNTL 0x44
539#define ICH4_ACPI_EN 0x10
540#define ICH6_ACPI_EN 0x80
541#define ICH4_GPIOBASE 0x58
542#define ICH4_GPIO_CNTL 0x5c
543#define ICH4_GPIO_EN 0x10
544#define ICH6_GPIOBASE 0x48
545#define ICH6_GPIO_CNTL 0x4c
546#define ICH6_GPIO_EN 0x10
547
Linus Torvalds1da177e2005-04-16 15:20:36 -0700548/*
549 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
550 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
551 * 0x58 (64 bytes of GPIO I/O space)
552 */
553static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
554{
555 u32 region;
Jiri Slabycdb97552011-02-28 10:45:09 +0100556 u8 enable;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700557
Jiri Slaby87e3dc32011-02-28 10:45:10 +0100558 /*
559 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
560 * with low legacy (and fixed) ports. We don't know the decoding
561 * priority and can't tell whether the legacy device or the one created
562 * here is really at that address. This happens on boards with broken
563 * BIOSes.
564 */
565
Jiri Slabycdb97552011-02-28 10:45:09 +0100566 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
567 if (enable & ICH4_ACPI_EN) {
568 pci_read_config_dword(dev, ICH_PMBASE, &region);
Jiri Slaby87e3dc32011-02-28 10:45:10 +0100569 region &= PCI_BASE_ADDRESS_IO_MASK;
570 if (region >= PCIBIOS_MIN_IO)
571 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES,
572 "ICH4 ACPI/GPIO/TCO");
Jiri Slabycdb97552011-02-28 10:45:09 +0100573 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700574
Jiri Slabycdb97552011-02-28 10:45:09 +0100575 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
576 if (enable & ICH4_GPIO_EN) {
577 pci_read_config_dword(dev, ICH4_GPIOBASE, &region);
Jiri Slaby87e3dc32011-02-28 10:45:10 +0100578 region &= PCI_BASE_ADDRESS_IO_MASK;
579 if (region >= PCIBIOS_MIN_IO)
580 quirk_io_region(dev, region, 64,
581 PCI_BRIDGE_RESOURCES + 1, "ICH4 GPIO");
Jiri Slabycdb97552011-02-28 10:45:09 +0100582 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700583}
Andrew Morton652c5382007-11-21 15:07:13 -0800584DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
585DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
586DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
587DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
588DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
589DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
590DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
591DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
592DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
593DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700594
Linus Torvalds894886e2008-12-06 10:10:10 -0800595static void __devinit ich6_lpc_acpi_gpio(struct pci_dev *dev)
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000596{
597 u32 region;
Jiri Slabycdb97552011-02-28 10:45:09 +0100598 u8 enable;
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000599
Jiri Slabycdb97552011-02-28 10:45:09 +0100600 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
601 if (enable & ICH6_ACPI_EN) {
602 pci_read_config_dword(dev, ICH_PMBASE, &region);
Jiri Slaby87e3dc32011-02-28 10:45:10 +0100603 region &= PCI_BASE_ADDRESS_IO_MASK;
604 if (region >= PCIBIOS_MIN_IO)
605 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES,
606 "ICH6 ACPI/GPIO/TCO");
Jiri Slabycdb97552011-02-28 10:45:09 +0100607 }
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000608
Jiri Slabycdb97552011-02-28 10:45:09 +0100609 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
Jean Delvareb6d95bb2011-04-15 10:24:07 +0200610 if (enable & ICH6_GPIO_EN) {
Jiri Slabycdb97552011-02-28 10:45:09 +0100611 pci_read_config_dword(dev, ICH6_GPIOBASE, &region);
Jiri Slaby87e3dc32011-02-28 10:45:10 +0100612 region &= PCI_BASE_ADDRESS_IO_MASK;
613 if (region >= PCIBIOS_MIN_IO)
614 quirk_io_region(dev, region, 64,
615 PCI_BRIDGE_RESOURCES + 1, "ICH6 GPIO");
Jiri Slabycdb97552011-02-28 10:45:09 +0100616 }
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000617}
Linus Torvalds894886e2008-12-06 10:10:10 -0800618
619static void __devinit ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
620{
621 u32 val;
622 u32 size, base;
623
624 pci_read_config_dword(dev, reg, &val);
625
626 /* Enabled? */
627 if (!(val & 1))
628 return;
629 base = val & 0xfffc;
630 if (dynsize) {
631 /*
632 * This is not correct. It is 16, 32 or 64 bytes depending on
633 * register D31:F0:ADh bits 5:4.
634 *
635 * But this gets us at least _part_ of it.
636 */
637 size = 16;
638 } else {
639 size = 128;
640 }
641 base &= ~(size-1);
642
643 /* Just print it out for now. We should reserve it after more debugging */
644 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
645}
646
647static void __devinit quirk_ich6_lpc(struct pci_dev *dev)
648{
649 /* Shared ACPI/GPIO decode with all ICH6+ */
650 ich6_lpc_acpi_gpio(dev);
651
652 /* ICH6-specific generic IO decode */
653 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
654 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
655}
656DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
657DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
658
659static void __devinit ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
660{
661 u32 val;
662 u32 mask, base;
663
664 pci_read_config_dword(dev, reg, &val);
665
666 /* Enabled? */
667 if (!(val & 1))
668 return;
669
670 /*
671 * IO base in bits 15:2, mask in bits 23:18, both
672 * are dword-based
673 */
674 base = val & 0xfffc;
675 mask = (val >> 16) & 0xfc;
676 mask |= 3;
677
678 /* Just print it out for now. We should reserve it after more debugging */
679 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
680}
681
682/* ICH7-10 has the same common LPC generic IO decode registers */
683static void __devinit quirk_ich7_lpc(struct pci_dev *dev)
684{
Jean Delvare5d9c0a72011-04-15 10:03:53 +0200685 /* We share the common ACPI/GPIO decode with ICH6 */
Linus Torvalds894886e2008-12-06 10:10:10 -0800686 ich6_lpc_acpi_gpio(dev);
687
688 /* And have 4 ICH7+ generic decodes */
689 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
690 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
691 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
692 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
693}
694DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
695DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
696DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
697DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
698DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
699DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
700DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
701DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
702DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
703DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
704DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
705DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
706DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000707
Linus Torvalds1da177e2005-04-16 15:20:36 -0700708/*
709 * VIA ACPI: One IO region pointed to by longword at
710 * 0x48 or 0x20 (256 bytes of ACPI registers)
711 */
712static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
713{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700714 u32 region;
715
Auke Kok651472f2007-08-27 16:18:10 -0700716 if (dev->revision & 0x10) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700717 pci_read_config_dword(dev, 0x48, &region);
718 region &= PCI_BASE_ADDRESS_IO_MASK;
Linus Torvalds6693e742005-10-25 20:40:09 -0700719 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES, "vt82c586 ACPI");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700720 }
721}
Andrew Morton652c5382007-11-21 15:07:13 -0800722DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700723
724/*
725 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
726 * 0x48 (256 bytes of ACPI registers)
727 * 0x70 (128 bytes of hardware monitoring register)
728 * 0x90 (16 bytes of SMB registers)
729 */
730static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
731{
732 u16 hm;
733 u32 smb;
734
735 quirk_vt82c586_acpi(dev);
736
737 pci_read_config_word(dev, 0x70, &hm);
738 hm &= PCI_BASE_ADDRESS_IO_MASK;
Meelis Roos02f313b2005-10-29 13:31:49 +0300739 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1, "vt82c686 HW-mon");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700740
741 pci_read_config_dword(dev, 0x90, &smb);
742 smb &= PCI_BASE_ADDRESS_IO_MASK;
Meelis Roos02f313b2005-10-29 13:31:49 +0300743 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2, "vt82c686 SMB");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700744}
Andrew Morton652c5382007-11-21 15:07:13 -0800745DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700746
Ivan Kokshaysky6d85f292005-08-08 12:55:54 +0400747/*
748 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
749 * 0x88 (128 bytes of power management registers)
750 * 0xd0 (16 bytes of SMB registers)
751 */
752static void __devinit quirk_vt8235_acpi(struct pci_dev *dev)
753{
754 u16 pm, smb;
755
756 pci_read_config_word(dev, 0x88, &pm);
757 pm &= PCI_BASE_ADDRESS_IO_MASK;
Linus Torvalds6693e742005-10-25 20:40:09 -0700758 quirk_io_region(dev, pm, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
Ivan Kokshaysky6d85f292005-08-08 12:55:54 +0400759
760 pci_read_config_word(dev, 0xd0, &smb);
761 smb &= PCI_BASE_ADDRESS_IO_MASK;
Linus Torvalds6693e742005-10-25 20:40:09 -0700762 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 1, "vt8235 SMB");
Ivan Kokshaysky6d85f292005-08-08 12:55:54 +0400763}
764DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
765
Gabe Black1f56f4a2009-10-06 09:19:45 -0500766/*
767 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
768 * Disable fast back-to-back on the secondary bus segment
769 */
770static void __devinit quirk_xio2000a(struct pci_dev *dev)
771{
772 struct pci_dev *pdev;
773 u16 command;
774
775 dev_warn(&dev->dev, "TI XIO2000a quirk detected; "
776 "secondary bus fast back-to-back transfers disabled\n");
777 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
778 pci_read_config_word(pdev, PCI_COMMAND, &command);
779 if (command & PCI_COMMAND_FAST_BACK)
780 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
781 }
782}
783DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
784 quirk_xio2000a);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700785
786#ifdef CONFIG_X86_IO_APIC
787
788#include <asm/io_apic.h>
789
790/*
791 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
792 * devices to the external APIC.
793 *
794 * TODO: When we have device-specific interrupt routers,
795 * this code will go away from quirks.
796 */
Alan Cox1597cac2006-12-04 15:14:45 -0800797static void quirk_via_ioapic(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700798{
799 u8 tmp;
800
801 if (nr_ioapics < 1)
802 tmp = 0; /* nothing routed to external APIC */
803 else
804 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
805
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700806 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700807 tmp == 0 ? "Disa" : "Ena");
808
809 /* Offset 0x58: External APIC IRQ output control */
810 pci_write_config_byte (dev, 0x58, tmp);
811}
Andrew Morton652c5382007-11-21 15:07:13 -0800812DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +0200813DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700814
815/*
Karsten Wiesea1740912005-09-03 15:56:33 -0700816 * VIA 8237: Some BIOSs don't set the 'Bypass APIC De-Assert Message' Bit.
817 * This leads to doubled level interrupt rates.
818 * Set this bit to get rid of cycle wastage.
819 * Otherwise uncritical.
820 */
Alan Cox1597cac2006-12-04 15:14:45 -0800821static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
Karsten Wiesea1740912005-09-03 15:56:33 -0700822{
823 u8 misc_control2;
824#define BYPASS_APIC_DEASSERT 8
825
826 pci_read_config_byte(dev, 0x5B, &misc_control2);
827 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700828 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
Karsten Wiesea1740912005-09-03 15:56:33 -0700829 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
830 }
831}
832DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +0200833DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
Karsten Wiesea1740912005-09-03 15:56:33 -0700834
835/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700836 * The AMD io apic can hang the box when an apic irq is masked.
837 * We check all revs >= B0 (yet not in the pre production!) as the bug
838 * is currently marked NoFix
839 *
840 * We have multiple reports of hangs with this chipset that went away with
Alan Cox236561e2006-09-30 23:27:03 -0700841 * noapic specified. For the moment we assume it's the erratum. We may be wrong
Linus Torvalds1da177e2005-04-16 15:20:36 -0700842 * of course. However the advice is demonstrably good even if so..
843 */
844static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
845{
Auke Kok44c10132007-06-08 15:46:36 -0700846 if (dev->revision >= 0x02) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700847 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
848 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700849 }
850}
Andrew Morton652c5382007-11-21 15:07:13 -0800851DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700852
853static void __init quirk_ioapic_rmw(struct pci_dev *dev)
854{
855 if (dev->devfn == 0 && dev->bus->number == 0)
856 sis_apic_bug = 1;
857}
Andrew Morton652c5382007-11-21 15:07:13 -0800858DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700859#endif /* CONFIG_X86_IO_APIC */
860
Peter Orubad556ad42007-05-15 13:59:13 +0200861/*
862 * Some settings of MMRBC can lead to data corruption so block changes.
863 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
864 */
865static void __init quirk_amd_8131_mmrbc(struct pci_dev *dev)
866{
Auke Kokaa288d42007-08-27 16:17:47 -0700867 if (dev->subordinate && dev->revision <= 0x12) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700868 dev_info(&dev->dev, "AMD8131 rev %x detected; "
869 "disabling PCI-X MMRBC\n", dev->revision);
Peter Orubad556ad42007-05-15 13:59:13 +0200870 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
871 }
872}
873DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700874
875/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700876 * FIXME: it is questionable that quirk_via_acpi
877 * is needed. It shows up as an ISA bridge, and does not
878 * support the PCI_INTERRUPT_LINE register at all. Therefore
879 * it seems like setting the pci_dev's 'irq' to the
880 * value of the ACPI SCI interrupt is only done for convenience.
881 * -jgarzik
882 */
883static void __devinit quirk_via_acpi(struct pci_dev *d)
884{
885 /*
886 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
887 */
888 u8 irq;
889 pci_read_config_byte(d, 0x42, &irq);
890 irq &= 0xf;
891 if (irq && (irq != 2))
892 d->irq = irq;
893}
Andrew Morton652c5382007-11-21 15:07:13 -0800894DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
895DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700896
Daniel Drake09d60292006-09-25 16:52:19 -0700897
898/*
Alan Cox1597cac2006-12-04 15:14:45 -0800899 * VIA bridges which have VLink
Daniel Drake09d60292006-09-25 16:52:19 -0700900 */
Alan Cox1597cac2006-12-04 15:14:45 -0800901
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800902static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
903
904static void quirk_via_bridge(struct pci_dev *dev)
905{
906 /* See what bridge we have and find the device ranges */
907 switch (dev->device) {
908 case PCI_DEVICE_ID_VIA_82C686:
Jean Delvarecb7468e2007-01-31 23:48:12 -0800909 /* The VT82C686 is special, it attaches to PCI and can have
910 any device number. All its subdevices are functions of
911 that single device. */
912 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
913 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800914 break;
915 case PCI_DEVICE_ID_VIA_8237:
916 case PCI_DEVICE_ID_VIA_8237A:
917 via_vlink_dev_lo = 15;
918 break;
919 case PCI_DEVICE_ID_VIA_8235:
920 via_vlink_dev_lo = 16;
921 break;
922 case PCI_DEVICE_ID_VIA_8231:
923 case PCI_DEVICE_ID_VIA_8233_0:
924 case PCI_DEVICE_ID_VIA_8233A:
925 case PCI_DEVICE_ID_VIA_8233C_0:
926 via_vlink_dev_lo = 17;
927 break;
928 }
929}
930DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
931DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
932DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
933DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
934DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
935DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
936DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
937DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
Daniel Drake09d60292006-09-25 16:52:19 -0700938
Alan Cox1597cac2006-12-04 15:14:45 -0800939/**
940 * quirk_via_vlink - VIA VLink IRQ number update
941 * @dev: PCI device
942 *
943 * If the device we are dealing with is on a PIC IRQ we need to
944 * ensure that the IRQ line register which usually is not relevant
945 * for PCI cards, is actually written so that interrupts get sent
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800946 * to the right place.
947 * We only do this on systems where a VIA south bridge was detected,
948 * and only for VIA devices on the motherboard (see quirk_via_bridge
949 * above).
Alan Cox1597cac2006-12-04 15:14:45 -0800950 */
951
952static void quirk_via_vlink(struct pci_dev *dev)
Len Brown25be5e62005-05-27 04:21:50 -0400953{
954 u8 irq, new_irq;
955
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800956 /* Check if we have VLink at all */
957 if (via_vlink_dev_lo == -1)
Daniel Drake09d60292006-09-25 16:52:19 -0700958 return;
959
960 new_irq = dev->irq;
961
962 /* Don't quirk interrupts outside the legacy IRQ range */
963 if (!new_irq || new_irq > 15)
964 return;
965
Alan Cox1597cac2006-12-04 15:14:45 -0800966 /* Internal device ? */
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800967 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
968 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
Alan Cox1597cac2006-12-04 15:14:45 -0800969 return;
970
971 /* This is an internal VLink device on a PIC interrupt. The BIOS
972 ought to have set this but may not have, so we redo it */
973
Len Brown25be5e62005-05-27 04:21:50 -0400974 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
975 if (new_irq != irq) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700976 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
977 irq, new_irq);
Len Brown25be5e62005-05-27 04:21:50 -0400978 udelay(15); /* unknown if delay really needed */
979 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
980 }
981}
Alan Cox1597cac2006-12-04 15:14:45 -0800982DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
Len Brown25be5e62005-05-27 04:21:50 -0400983
Linus Torvalds1da177e2005-04-16 15:20:36 -0700984/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700985 * VIA VT82C598 has its device ID settable and many BIOSes
986 * set it to the ID of VT82C597 for backward compatibility.
987 * We need to switch it off to be able to recognize the real
988 * type of the chip.
989 */
990static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
991{
992 pci_write_config_byte(dev, 0xfc, 0);
993 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
994}
Andrew Morton652c5382007-11-21 15:07:13 -0800995DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700996
997/*
998 * CardBus controllers have a legacy base address that enables them
999 * to respond as i82365 pcmcia controllers. We don't want them to
1000 * do this even if the Linux CardBus driver is not loaded, because
1001 * the Linux i82365 driver does not (and should not) handle CardBus.
1002 */
Alan Cox1597cac2006-12-04 15:14:45 -08001003static void quirk_cardbus_legacy(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001004{
1005 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
1006 return;
1007 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
1008}
1009DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001010DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001011
1012/*
1013 * Following the PCI ordering rules is optional on the AMD762. I'm not
1014 * sure what the designers were smoking but let's not inhale...
1015 *
1016 * To be fair to AMD, it follows the spec by default, its BIOS people
1017 * who turn it off!
1018 */
Alan Cox1597cac2006-12-04 15:14:45 -08001019static void quirk_amd_ordering(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001020{
1021 u32 pcic;
1022 pci_read_config_dword(dev, 0x4C, &pcic);
1023 if ((pcic&6)!=6) {
1024 pcic |= 6;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001025 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001026 pci_write_config_dword(dev, 0x4C, pcic);
1027 pci_read_config_dword(dev, 0x84, &pcic);
1028 pcic |= (1<<23); /* Required in this mode */
1029 pci_write_config_dword(dev, 0x84, pcic);
1030 }
1031}
Andrew Morton652c5382007-11-21 15:07:13 -08001032DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001033DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001034
1035/*
1036 * DreamWorks provided workaround for Dunord I-3000 problem
1037 *
1038 * This card decodes and responds to addresses not apparently
1039 * assigned to it. We force a larger allocation to ensure that
1040 * nothing gets put too close to it.
1041 */
1042static void __devinit quirk_dunord ( struct pci_dev * dev )
1043{
1044 struct resource *r = &dev->resource [1];
1045 r->start = 0;
1046 r->end = 0xffffff;
1047}
Andrew Morton652c5382007-11-21 15:07:13 -08001048DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001049
1050/*
1051 * i82380FB mobile docking controller: its PCI-to-PCI bridge
1052 * is subtractive decoding (transparent), and does indicate this
1053 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
1054 * instead of 0x01.
1055 */
1056static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
1057{
1058 dev->transparent = 1;
1059}
Andrew Morton652c5382007-11-21 15:07:13 -08001060DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1061DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001062
1063/*
1064 * Common misconfiguration of the MediaGX/Geode PCI master that will
1065 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
Justin P. Mattock631dd1a2010-10-18 11:03:14 +02001066 * datasheets found at http://www.national.com/analog for info on what
Linus Torvalds1da177e2005-04-16 15:20:36 -07001067 * these bits do. <christer@weinigel.se>
1068 */
Alan Cox1597cac2006-12-04 15:14:45 -08001069static void quirk_mediagx_master(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001070{
1071 u8 reg;
1072 pci_read_config_byte(dev, 0x41, &reg);
1073 if (reg & 2) {
1074 reg &= ~2;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001075 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001076 pci_write_config_byte(dev, 0x41, reg);
1077 }
1078}
Andrew Morton652c5382007-11-21 15:07:13 -08001079DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1080DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001081
1082/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001083 * Ensure C0 rev restreaming is off. This is normally done by
1084 * the BIOS but in the odd case it is not the results are corruption
1085 * hence the presence of a Linux check
1086 */
Alan Cox1597cac2006-12-04 15:14:45 -08001087static void quirk_disable_pxb(struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001088{
1089 u16 config;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001090
Auke Kok44c10132007-06-08 15:46:36 -07001091 if (pdev->revision != 0x04) /* Only C0 requires this */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001092 return;
1093 pci_read_config_word(pdev, 0x40, &config);
1094 if (config & (1<<6)) {
1095 config &= ~(1<<6);
1096 pci_write_config_word(pdev, 0x40, config);
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001097 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001098 }
1099}
Andrew Morton652c5382007-11-21 15:07:13 -08001100DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001101DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001102
Crane Cai05a7d222008-02-02 13:56:56 +08001103static void __devinit quirk_amd_ide_mode(struct pci_dev *pdev)
Conke Huab174432006-12-19 13:11:37 -08001104{
Shane Huang5deab532009-10-13 11:14:00 +08001105 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
Crane Cai05a7d222008-02-02 13:56:56 +08001106 u8 tmp;
Conke Huab174432006-12-19 13:11:37 -08001107
Crane Cai05a7d222008-02-02 13:56:56 +08001108 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1109 if (tmp == 0x01) {
Conke Huab174432006-12-19 13:11:37 -08001110 pci_read_config_byte(pdev, 0x40, &tmp);
1111 pci_write_config_byte(pdev, 0x40, tmp|1);
1112 pci_write_config_byte(pdev, 0x9, 1);
1113 pci_write_config_byte(pdev, 0xa, 6);
1114 pci_write_config_byte(pdev, 0x40, tmp);
1115
Conke Huc9f89472007-01-09 05:32:51 -05001116 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
Crane Cai05a7d222008-02-02 13:56:56 +08001117 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
Conke Huab174432006-12-19 13:11:37 -08001118 }
1119}
Crane Cai05a7d222008-02-02 13:56:56 +08001120DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001121DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
Crane Cai05a7d222008-02-02 13:56:56 +08001122DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001123DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
Shane Huang5deab532009-10-13 11:14:00 +08001124DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1125DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
Conke Huab174432006-12-19 13:11:37 -08001126
Linus Torvalds1da177e2005-04-16 15:20:36 -07001127/*
1128 * Serverworks CSB5 IDE does not fully support native mode
1129 */
1130static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
1131{
1132 u8 prog;
1133 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1134 if (prog & 5) {
1135 prog &= ~5;
1136 pdev->class &= ~5;
1137 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
Alan Cox368c73d2006-10-04 00:41:26 +01001138 /* PCI layer will sort out resources */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001139 }
1140}
Andrew Morton652c5382007-11-21 15:07:13 -08001141DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001142
1143/*
1144 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1145 */
1146static void __init quirk_ide_samemode(struct pci_dev *pdev)
1147{
1148 u8 prog;
1149
1150 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1151
1152 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001153 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001154 prog &= ~5;
1155 pdev->class &= ~5;
1156 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001157 }
1158}
Alan Cox368c73d2006-10-04 00:41:26 +01001159DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001160
Alan Cox979b1792008-07-24 17:18:38 +01001161/*
1162 * Some ATA devices break if put into D3
1163 */
1164
1165static void __devinit quirk_no_ata_d3(struct pci_dev *pdev)
1166{
1167 /* Quirk the legacy ATA devices only. The AHCI ones are ok */
1168 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE)
1169 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1170}
1171DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, quirk_no_ata_d3);
1172DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, quirk_no_ata_d3);
Alan Cox7a661c62009-06-24 16:02:27 +01001173/* ALi loses some register settings that we cannot then restore */
1174DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, quirk_no_ata_d3);
1175/* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1176 occur when mode detecting */
1177DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_no_ata_d3);
Alan Cox979b1792008-07-24 17:18:38 +01001178
Linus Torvalds1da177e2005-04-16 15:20:36 -07001179/* This was originally an Alpha specific thing, but it really fits here.
1180 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1181 */
1182static void __init quirk_eisa_bridge(struct pci_dev *dev)
1183{
1184 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1185}
Andrew Morton652c5382007-11-21 15:07:13 -08001186DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001187
Johannes Goecke7daa0c42006-04-20 02:43:17 -07001188
1189/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001190 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1191 * is not activated. The myth is that Asus said that they do not want the
1192 * users to be irritated by just another PCI Device in the Win98 device
1193 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
1194 * package 2.7.0 for details)
1195 *
1196 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1197 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
gw.kernel@tnode.comd7698ed2007-08-23 21:22:04 +02001198 * becomes necessary to do this tweak in two steps -- the chosen trigger
1199 * is either the Host bridge (preferred) or on-board VGA controller.
Jean Delvare9208ee82007-03-24 16:56:44 +01001200 *
1201 * Note that we used to unhide the SMBus that way on Toshiba laptops
1202 * (Satellite A40 and Tecra M2) but then found that the thermal management
1203 * was done by SMM code, which could cause unsynchronized concurrent
1204 * accesses to the SMBus registers, with potentially bad effects. Thus you
1205 * should be very careful when adding new entries: if SMM is accessing the
1206 * Intel SMBus, this is a very good reason to leave it hidden.
Jean Delvarea99acc82008-03-28 14:16:04 -07001207 *
1208 * Likewise, many recent laptops use ACPI for thermal management. If the
1209 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1210 * natively, and keeping the SMBus hidden is the right thing to do. If you
1211 * are about to add an entry in the table below, please first disassemble
1212 * the DSDT and double-check that there is no code accessing the SMBus.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001213 */
Vivek Goyal9d24a812007-01-11 01:52:44 +01001214static int asus_hides_smbus;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001215
1216static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
1217{
1218 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1219 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1220 switch(dev->subsystem_device) {
Jean Delvarea00db372005-06-29 17:04:06 +02001221 case 0x8025: /* P4B-LX */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001222 case 0x8070: /* P4B */
1223 case 0x8088: /* P4B533 */
1224 case 0x1626: /* L3C notebook */
1225 asus_hides_smbus = 1;
1226 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001227 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001228 switch(dev->subsystem_device) {
1229 case 0x80b1: /* P4GE-V */
1230 case 0x80b2: /* P4PE */
1231 case 0x8093: /* P4B533-V */
1232 asus_hides_smbus = 1;
1233 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001234 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001235 switch(dev->subsystem_device) {
1236 case 0x8030: /* P4T533 */
1237 asus_hides_smbus = 1;
1238 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001239 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001240 switch (dev->subsystem_device) {
1241 case 0x8070: /* P4G8X Deluxe */
1242 asus_hides_smbus = 1;
1243 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001244 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
Jean Delvare321311a2006-07-31 08:53:15 +02001245 switch (dev->subsystem_device) {
1246 case 0x80c9: /* PU-DLS */
1247 asus_hides_smbus = 1;
1248 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001249 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001250 switch (dev->subsystem_device) {
1251 case 0x1751: /* M2N notebook */
1252 case 0x1821: /* M5N notebook */
Mats Erik Andersson4096ed02009-05-12 12:05:23 +02001253 case 0x1897: /* A6L notebook */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001254 asus_hides_smbus = 1;
1255 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001256 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001257 switch (dev->subsystem_device) {
1258 case 0x184b: /* W1N notebook */
1259 case 0x186a: /* M6Ne notebook */
1260 asus_hides_smbus = 1;
1261 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001262 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
Jean Delvare2e457852007-01-05 09:17:56 +01001263 switch (dev->subsystem_device) {
1264 case 0x80f2: /* P4P800-X */
1265 asus_hides_smbus = 1;
1266 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001267 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001268 switch (dev->subsystem_device) {
1269 case 0x1882: /* M6V notebook */
Jean Delvare2d1e1c72006-04-01 16:46:35 +02001270 case 0x1977: /* A6VA notebook */
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001271 asus_hides_smbus = 1;
1272 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001273 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1274 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1275 switch(dev->subsystem_device) {
1276 case 0x088C: /* HP Compaq nc8000 */
1277 case 0x0890: /* HP Compaq nc6000 */
1278 asus_hides_smbus = 1;
1279 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001280 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001281 switch (dev->subsystem_device) {
1282 case 0x12bc: /* HP D330L */
Jean Delvaree3b1bd52005-09-21 22:26:31 +02001283 case 0x12bd: /* HP D530 */
Michal Miroslaw74c57422009-05-12 13:49:25 -07001284 case 0x006a: /* HP Compaq nx9500 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001285 asus_hides_smbus = 1;
1286 }
Jean Delvare677cc642007-11-21 18:29:06 +01001287 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1288 switch (dev->subsystem_device) {
1289 case 0x12bf: /* HP xw4100 */
1290 asus_hides_smbus = 1;
1291 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001292 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1293 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1294 switch(dev->subsystem_device) {
1295 case 0xC00C: /* Samsung P35 notebook */
1296 asus_hides_smbus = 1;
1297 }
Rumen Ivanov Zarevc87f8832005-09-06 13:39:32 -07001298 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1299 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1300 switch(dev->subsystem_device) {
1301 case 0x0058: /* Compaq Evo N620c */
1302 asus_hides_smbus = 1;
1303 }
gw.kernel@tnode.comd7698ed2007-08-23 21:22:04 +02001304 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1305 switch(dev->subsystem_device) {
1306 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1307 /* Motherboard doesn't have Host bridge
1308 * subvendor/subdevice IDs, therefore checking
1309 * its on-board VGA controller */
1310 asus_hides_smbus = 1;
1311 }
David O'Shea8293b0f2009-03-02 09:51:13 +01001312 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
Jean Delvare10260d92008-06-04 13:53:31 +02001313 switch(dev->subsystem_device) {
1314 case 0x00b8: /* Compaq Evo D510 CMT */
1315 case 0x00b9: /* Compaq Evo D510 SFF */
Jean Delvare6b5096e2009-07-28 11:49:19 +02001316 case 0x00ba: /* Compaq Evo D510 USDT */
David O'Shea8293b0f2009-03-02 09:51:13 +01001317 /* Motherboard doesn't have Host bridge
1318 * subvendor/subdevice IDs and on-board VGA
1319 * controller is disabled if an AGP card is
1320 * inserted, therefore checking USB UHCI
1321 * Controller #1 */
Jean Delvare10260d92008-06-04 13:53:31 +02001322 asus_hides_smbus = 1;
1323 }
Krzysztof Helt27e46852008-06-08 13:47:02 +02001324 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1325 switch (dev->subsystem_device) {
1326 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1327 /* Motherboard doesn't have host bridge
1328 * subvendor/subdevice IDs, therefore checking
1329 * its on-board VGA controller */
1330 asus_hides_smbus = 1;
1331 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001332 }
1333}
Andrew Morton652c5382007-11-21 15:07:13 -08001334DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1335DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1336DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1337DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
Jean Delvare677cc642007-11-21 18:29:06 +01001338DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
Andrew Morton652c5382007-11-21 15:07:13 -08001339DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1340DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1341DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1342DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1343DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001344
Andrew Morton652c5382007-11-21 15:07:13 -08001345DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
David O'Shea8293b0f2009-03-02 09:51:13 +01001346DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
Krzysztof Helt27e46852008-06-08 13:47:02 +02001347DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
gw.kernel@tnode.comd7698ed2007-08-23 21:22:04 +02001348
Alan Cox1597cac2006-12-04 15:14:45 -08001349static void asus_hides_smbus_lpc(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001350{
1351 u16 val;
1352
1353 if (likely(!asus_hides_smbus))
1354 return;
1355
1356 pci_read_config_word(dev, 0xF2, &val);
1357 if (val & 0x8) {
1358 pci_write_config_word(dev, 0xF2, val & (~0x8));
1359 pci_read_config_word(dev, 0xF2, &val);
1360 if (val & 0x8)
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001361 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001362 else
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001363 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001364 }
1365}
Andrew Morton652c5382007-11-21 15:07:13 -08001366DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1367DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1368DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1369DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1370DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1371DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1372DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001373DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1374DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1375DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1376DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1377DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1378DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1379DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001380
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001381/* It appears we just have one such device. If not, we have a warning */
1382static void __iomem *asus_rcba_base;
1383static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001384{
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001385 u32 rcba;
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001386
1387 if (likely(!asus_hides_smbus))
1388 return;
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001389 WARN_ON(asus_rcba_base);
1390
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001391 pci_read_config_dword(dev, 0xF0, &rcba);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001392 /* use bits 31:14, 16 kB aligned */
1393 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1394 if (asus_rcba_base == NULL)
1395 return;
1396}
1397
1398static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1399{
1400 u32 val;
1401
1402 if (likely(!asus_hides_smbus || !asus_rcba_base))
1403 return;
1404 /* read the Function Disable register, dword mode only */
1405 val = readl(asus_rcba_base + 0x3418);
1406 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1407}
1408
1409static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1410{
1411 if (likely(!asus_hides_smbus || !asus_rcba_base))
1412 return;
1413 iounmap(asus_rcba_base);
1414 asus_rcba_base = NULL;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001415 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001416}
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001417
1418static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1419{
1420 asus_hides_smbus_lpc_ich6_suspend(dev);
1421 asus_hides_smbus_lpc_ich6_resume_early(dev);
1422 asus_hides_smbus_lpc_ich6_resume(dev);
1423}
Andrew Morton652c5382007-11-21 15:07:13 -08001424DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001425DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1426DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1427DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
Carl-Daniel Hailfingerce007ea2006-05-15 09:44:33 -07001428
Linus Torvalds1da177e2005-04-16 15:20:36 -07001429/*
1430 * SiS 96x south bridge: BIOS typically hides SMBus device...
1431 */
Alan Cox1597cac2006-12-04 15:14:45 -08001432static void quirk_sis_96x_smbus(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001433{
1434 u8 val = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001435 pci_read_config_byte(dev, 0x77, &val);
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001436 if (val & 0x10) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001437 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001438 pci_write_config_byte(dev, 0x77, val & ~0x10);
1439 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001440}
Andrew Morton652c5382007-11-21 15:07:13 -08001441DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1442DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1443DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1444DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001445DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1446DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1447DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1448DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001449
Linus Torvalds1da177e2005-04-16 15:20:36 -07001450/*
1451 * ... This is further complicated by the fact that some SiS96x south
1452 * bridges pretend to be 85C503/5513 instead. In that case see if we
1453 * spotted a compatible north bridge to make sure.
1454 * (pci_find_device doesn't work yet)
1455 *
1456 * We can also enable the sis96x bit in the discovery register..
1457 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001458#define SIS_DETECT_REGISTER 0x40
1459
Alan Cox1597cac2006-12-04 15:14:45 -08001460static void quirk_sis_503(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001461{
1462 u8 reg;
1463 u16 devid;
1464
1465 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1466 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1467 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1468 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1469 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1470 return;
1471 }
1472
Linus Torvalds1da177e2005-04-16 15:20:36 -07001473 /*
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001474 * Ok, it now shows up as a 96x.. run the 96x quirk by
1475 * hand in case it has already been processed.
1476 * (depends on link order, which is apparently not guaranteed)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001477 */
1478 dev->device = devid;
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001479 quirk_sis_96x_smbus(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001480}
Andrew Morton652c5382007-11-21 15:07:13 -08001481DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001482DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001483
Linus Torvalds1da177e2005-04-16 15:20:36 -07001484
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001485/*
1486 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1487 * and MC97 modem controller are disabled when a second PCI soundcard is
1488 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1489 * -- bjd
1490 */
Alan Cox1597cac2006-12-04 15:14:45 -08001491static void asus_hides_ac97_lpc(struct pci_dev *dev)
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001492{
1493 u8 val;
1494 int asus_hides_ac97 = 0;
1495
1496 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1497 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1498 asus_hides_ac97 = 1;
1499 }
1500
1501 if (!asus_hides_ac97)
1502 return;
1503
1504 pci_read_config_byte(dev, 0x50, &val);
1505 if (val & 0xc0) {
1506 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1507 pci_read_config_byte(dev, 0x50, &val);
1508 if (val & 0xc0)
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001509 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", val);
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001510 else
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001511 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001512 }
1513}
Andrew Morton652c5382007-11-21 15:07:13 -08001514DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001515DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
Alan Cox1597cac2006-12-04 15:14:45 -08001516
Tejun Heo77967052006-08-19 03:54:39 +09001517#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
Alan Cox15e0c692006-07-12 15:05:41 +01001518
1519/*
1520 * If we are using libata we can drive this chip properly but must
1521 * do this early on to make the additional device appear during
1522 * the PCI scanning.
1523 */
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001524static void quirk_jmicron_ata(struct pci_dev *pdev)
Alan Cox15e0c692006-07-12 15:05:41 +01001525{
Tejun Heoe34bb372007-02-26 20:24:03 +09001526 u32 conf1, conf5, class;
Alan Cox15e0c692006-07-12 15:05:41 +01001527 u8 hdr;
1528
1529 /* Only poke fn 0 */
1530 if (PCI_FUNC(pdev->devfn))
1531 return;
1532
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001533 pci_read_config_dword(pdev, 0x40, &conf1);
1534 pci_read_config_dword(pdev, 0x80, &conf5);
Alan Cox15e0c692006-07-12 15:05:41 +01001535
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001536 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1537 conf5 &= ~(1 << 24); /* Clear bit 24 */
Alan Cox15e0c692006-07-12 15:05:41 +01001538
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001539 switch (pdev->device) {
Tejun Heo4daedcf2010-06-03 11:57:04 +02001540 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1541 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001542 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001543 /* The controller should be in single function ahci mode */
1544 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1545 break;
Alan Cox15e0c692006-07-12 15:05:41 +01001546
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001547 case PCI_DEVICE_ID_JMICRON_JMB365:
1548 case PCI_DEVICE_ID_JMICRON_JMB366:
1549 /* Redirect IDE second PATA port to the right spot */
1550 conf5 |= (1 << 24);
1551 /* Fall through */
1552 case PCI_DEVICE_ID_JMICRON_JMB361:
1553 case PCI_DEVICE_ID_JMICRON_JMB363:
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001554 case PCI_DEVICE_ID_JMICRON_JMB369:
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001555 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1556 /* Set the class codes correctly and then direct IDE 0 */
Tejun Heo3a9e3a52007-10-23 15:27:31 +09001557 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001558 break;
1559
1560 case PCI_DEVICE_ID_JMICRON_JMB368:
1561 /* The controller should be in single function IDE mode */
1562 conf1 |= 0x00C00000; /* Set 22, 23 */
1563 break;
Alan Cox15e0c692006-07-12 15:05:41 +01001564 }
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001565
1566 pci_write_config_dword(pdev, 0x40, conf1);
1567 pci_write_config_dword(pdev, 0x80, conf5);
1568
1569 /* Update pdev accordingly */
1570 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1571 pdev->hdr_type = hdr & 0x7f;
1572 pdev->multifunction = !!(hdr & 0x80);
Tejun Heoe34bb372007-02-26 20:24:03 +09001573
1574 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1575 pdev->class = class >> 8;
Alan Cox15e0c692006-07-12 15:05:41 +01001576}
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001577DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1578DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
Tejun Heo4daedcf2010-06-03 11:57:04 +02001579DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001580DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001581DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001582DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1583DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1584DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001585DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001586DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1587DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
Tejun Heo4daedcf2010-06-03 11:57:04 +02001588DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001589DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001590DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001591DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1592DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1593DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001594DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
Alan Cox15e0c692006-07-12 15:05:41 +01001595
1596#endif
1597
Linus Torvalds1da177e2005-04-16 15:20:36 -07001598#ifdef CONFIG_X86_IO_APIC
1599static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1600{
1601 int i;
1602
1603 if ((pdev->class >> 8) != 0xff00)
1604 return;
1605
1606 /* the first BAR is the location of the IO APIC...we must
1607 * not touch this (and it's already covered by the fixmap), so
1608 * forcibly insert it into the resource tree */
1609 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1610 insert_resource(&iomem_resource, &pdev->resource[0]);
1611
1612 /* The next five BARs all seem to be rubbish, so just clean
1613 * them out */
1614 for (i=1; i < 6; i++) {
1615 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1616 }
1617
1618}
Andrew Morton652c5382007-11-21 15:07:13 -08001619DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001620#endif
1621
Linus Torvalds1da177e2005-04-16 15:20:36 -07001622static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1623{
Eric W. Biederman0ba379e2009-09-06 21:48:35 -07001624 pci_msi_off(pdev);
1625 pdev->no_msi = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001626}
Andrew Morton652c5382007-11-21 15:07:13 -08001627DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1628DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1629DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001630
Kristen Accardi4602b882005-08-16 15:15:58 -07001631
1632/*
1633 * It's possible for the MSI to get corrupted if shpc and acpi
1634 * are used together on certain PXH-based systems.
1635 */
1636static void __devinit quirk_pcie_pxh(struct pci_dev *dev)
1637{
Eric W. Biedermanf5f2b132007-03-05 00:30:07 -08001638 pci_msi_off(dev);
Kristen Accardi4602b882005-08-16 15:15:58 -07001639 dev->no_msi = 1;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001640 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
Kristen Accardi4602b882005-08-16 15:15:58 -07001641}
1642DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1643DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1644DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1645DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1646DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1647
Kristen Carlson Accardiffadcc22006-07-12 08:59:00 -07001648/*
1649 * Some Intel PCI Express chipsets have trouble with downstream
1650 * device power management.
1651 */
1652static void quirk_intel_pcie_pm(struct pci_dev * dev)
1653{
1654 pci_pm_d3_delay = 120;
1655 dev->no_d1d2 = 1;
1656}
1657
1658DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1659DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1660DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1661DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1662DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1663DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1664DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1665DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1666DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1667DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1668DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1669DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1670DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1671DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1672DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1673DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1674DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1675DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1676DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1677DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1678DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
Kristen Accardi4602b882005-08-16 15:15:58 -07001679
Stefan Assmann426b3b82008-06-11 16:35:16 +02001680#ifdef CONFIG_X86_IO_APIC
1681/*
Stefan Assmanne1d3a902008-06-11 16:35:17 +02001682 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1683 * remap the original interrupt in the linux kernel to the boot interrupt, so
1684 * that a PCI device's interrupt handler is installed on the boot interrupt
1685 * line instead.
1686 */
1687static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1688{
Stefan Assmann41b9eb22008-07-15 13:48:55 +02001689 if (noioapicquirk || noioapicreroute)
Stefan Assmanne1d3a902008-06-11 16:35:17 +02001690 return;
1691
1692 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001693 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1694 dev->vendor, dev->device);
Stefan Assmanne1d3a902008-06-11 16:35:17 +02001695}
Olaf Dabrunz88d1dce2008-07-08 15:59:48 +02001696DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1697DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1698DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1699DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1700DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1701DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1702DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1703DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1704DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1705DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1706DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1707DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1708DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1709DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1710DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1711DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
Stefan Assmanne1d3a902008-06-11 16:35:17 +02001712
1713/*
Stefan Assmann426b3b82008-06-11 16:35:16 +02001714 * On some chipsets we can disable the generation of legacy INTx boot
1715 * interrupts.
1716 */
1717
1718/*
1719 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1720 * 300641-004US, section 5.7.3.
1721 */
1722#define INTEL_6300_IOAPIC_ABAR 0x40
1723#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1724
1725static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1726{
1727 u16 pci_config_word;
1728
1729 if (noioapicquirk)
1730 return;
1731
1732 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1733 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1734 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1735
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001736 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1737 dev->vendor, dev->device);
Stefan Assmann426b3b82008-06-11 16:35:16 +02001738}
Olaf Dabrunz88d1dce2008-07-08 15:59:48 +02001739DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1740DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
Olaf Dabrunz77251182008-07-08 15:59:47 +02001741
1742/*
1743 * disable boot interrupts on HT-1000
1744 */
1745#define BC_HT1000_FEATURE_REG 0x64
1746#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1747#define BC_HT1000_MAP_IDX 0xC00
1748#define BC_HT1000_MAP_DATA 0xC01
1749
1750static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1751{
1752 u32 pci_config_dword;
1753 u8 irq;
1754
1755 if (noioapicquirk)
1756 return;
1757
1758 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1759 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1760 BC_HT1000_PIC_REGS_ENABLE);
1761
1762 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1763 outb(irq, BC_HT1000_MAP_IDX);
1764 outb(0x00, BC_HT1000_MAP_DATA);
1765 }
1766
1767 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1768
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001769 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1770 dev->vendor, dev->device);
Olaf Dabrunz77251182008-07-08 15:59:47 +02001771}
Olaf Dabrunz88d1dce2008-07-08 15:59:48 +02001772DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1773DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001774
1775/*
1776 * disable boot interrupts on AMD and ATI chipsets
1777 */
1778/*
1779 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1780 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1781 * (due to an erratum).
1782 */
1783#define AMD_813X_MISC 0x40
1784#define AMD_813X_NOIOAMODE (1<<0)
Stefan Assmann4fd8bdc2009-10-27 08:57:42 +01001785#define AMD_813X_REV_B1 0x12
Stefan Assmannbbe19442009-02-26 10:46:48 -08001786#define AMD_813X_REV_B2 0x13
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001787
1788static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1789{
1790 u32 pci_config_dword;
1791
1792 if (noioapicquirk)
1793 return;
Stefan Assmann4fd8bdc2009-10-27 08:57:42 +01001794 if ((dev->revision == AMD_813X_REV_B1) ||
1795 (dev->revision == AMD_813X_REV_B2))
Stefan Assmannbbe19442009-02-26 10:46:48 -08001796 return;
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001797
1798 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1799 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1800 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1801
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001802 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1803 dev->vendor, dev->device);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001804}
Stefan Assmann4fd8bdc2009-10-27 08:57:42 +01001805DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1806DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1807DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1808DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001809
1810#define AMD_8111_PCI_IRQ_ROUTING 0x56
1811
1812static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1813{
1814 u16 pci_config_word;
1815
1816 if (noioapicquirk)
1817 return;
1818
1819 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1820 if (!pci_config_word) {
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001821 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] "
1822 "already disabled\n", dev->vendor, dev->device);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001823 return;
1824 }
1825 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001826 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1827 dev->vendor, dev->device);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001828}
Olaf Dabrunz88d1dce2008-07-08 15:59:48 +02001829DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1830DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
Stefan Assmann426b3b82008-06-11 16:35:16 +02001831#endif /* CONFIG_X86_IO_APIC */
1832
Sergei Shtylyov33dced22007-02-07 18:18:45 +01001833/*
1834 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1835 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1836 * Re-allocate the region if needed...
1837 */
1838static void __init quirk_tc86c001_ide(struct pci_dev *dev)
1839{
1840 struct resource *r = &dev->resource[0];
1841
1842 if (r->start & 0x8) {
1843 r->start = 0;
1844 r->end = 0xf;
1845 }
1846}
1847DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1848 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1849 quirk_tc86c001_ide);
1850
Linus Torvalds1da177e2005-04-16 15:20:36 -07001851static void __devinit quirk_netmos(struct pci_dev *dev)
1852{
1853 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1854 unsigned int num_serial = dev->subsystem_device & 0xf;
1855
1856 /*
1857 * These Netmos parts are multiport serial devices with optional
1858 * parallel ports. Even when parallel ports are present, they
1859 * are identified as class SERIAL, which means the serial driver
1860 * will claim them. To prevent this, mark them as class OTHER.
1861 * These combo devices should be claimed by parport_serial.
1862 *
1863 * The subdevice ID is of the form 0x00PS, where <P> is the number
1864 * of parallel ports and <S> is the number of serial ports.
1865 */
1866 switch (dev->device) {
Jiri Slaby4c9c1682008-12-08 16:19:14 +01001867 case PCI_DEVICE_ID_NETMOS_9835:
1868 /* Well, this rule doesn't hold for the following 9835 device */
1869 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1870 dev->subsystem_device == 0x0299)
1871 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001872 case PCI_DEVICE_ID_NETMOS_9735:
1873 case PCI_DEVICE_ID_NETMOS_9745:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001874 case PCI_DEVICE_ID_NETMOS_9845:
1875 case PCI_DEVICE_ID_NETMOS_9855:
1876 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1877 num_parallel) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001878 dev_info(&dev->dev, "Netmos %04x (%u parallel, "
Linus Torvalds1da177e2005-04-16 15:20:36 -07001879 "%u serial); changing class SERIAL to OTHER "
1880 "(use parport_serial)\n",
1881 dev->device, num_parallel, num_serial);
1882 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1883 (dev->class & 0xff);
1884 }
1885 }
1886}
1887DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1888
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001889static void __devinit quirk_e100_interrupt(struct pci_dev *dev)
1890{
Ivan Kokshayskye64aecc2007-12-18 00:39:27 +03001891 u16 command, pmcsr;
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001892 u8 __iomem *csr;
1893 u8 cmd_hi;
Ivan Kokshayskye64aecc2007-12-18 00:39:27 +03001894 int pm;
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001895
1896 switch (dev->device) {
1897 /* PCI IDs taken from drivers/net/e100.c */
1898 case 0x1029:
1899 case 0x1030 ... 0x1034:
1900 case 0x1038 ... 0x103E:
1901 case 0x1050 ... 0x1057:
1902 case 0x1059:
1903 case 0x1064 ... 0x106B:
1904 case 0x1091 ... 0x1095:
1905 case 0x1209:
1906 case 0x1229:
1907 case 0x2449:
1908 case 0x2459:
1909 case 0x245D:
1910 case 0x27DC:
1911 break;
1912 default:
1913 return;
1914 }
1915
1916 /*
1917 * Some firmware hands off the e100 with interrupts enabled,
1918 * which can cause a flood of interrupts if packets are
1919 * received before the driver attaches to the device. So
1920 * disable all e100 interrupts here. The driver will
1921 * re-enable them when it's ready.
1922 */
1923 pci_read_config_word(dev, PCI_COMMAND, &command);
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001924
Benjamin Herrenschmidt1bef7dc2007-09-29 09:06:21 +10001925 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001926 return;
1927
Ivan Kokshayskye64aecc2007-12-18 00:39:27 +03001928 /*
1929 * Check that the device is in the D0 power state. If it's not,
1930 * there is no point to look any further.
1931 */
1932 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
1933 if (pm) {
1934 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
1935 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
1936 return;
1937 }
1938
Benjamin Herrenschmidt1bef7dc2007-09-29 09:06:21 +10001939 /* Convert from PCI bus to resource space. */
1940 csr = ioremap(pci_resource_start(dev, 0), 8);
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001941 if (!csr) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001942 dev_warn(&dev->dev, "Can't map e100 registers\n");
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001943 return;
1944 }
1945
1946 cmd_hi = readb(csr + 3);
1947 if (cmd_hi == 0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001948 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; "
1949 "disabling\n");
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001950 writeb(1, csr + 3);
1951 }
1952
1953 iounmap(csr);
1954}
Marian Balakowicz4e68fc92007-07-03 11:03:18 +02001955DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_e100_interrupt);
Ivan Kokshayskya5312e22005-11-01 01:43:56 +03001956
Alexander Duyck649426e2009-03-05 13:57:28 -05001957/*
1958 * The 82575 and 82598 may experience data corruption issues when transitioning
1959 * out of L0S. To prevent this we need to disable L0S on the pci-e link
1960 */
1961static void __devinit quirk_disable_aspm_l0s(struct pci_dev *dev)
1962{
1963 dev_info(&dev->dev, "Disabling L0s\n");
1964 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
1965}
1966DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
1967DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
1968DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
1969DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
1970DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
1971DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
1972DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
1973DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
1974DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
1975DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
1976DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
1977DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
1978DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
1979DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
1980
Ivan Kokshayskya5312e22005-11-01 01:43:56 +03001981static void __devinit fixup_rev1_53c810(struct pci_dev* dev)
1982{
1983 /* rev 1 ncr53c810 chips don't set the class at all which means
1984 * they don't get their resources remapped. Fix that here.
1985 */
1986
1987 if (dev->class == PCI_CLASS_NOT_DEFINED) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001988 dev_info(&dev->dev, "NCR 53c810 rev 1 detected; setting PCI class\n");
Ivan Kokshayskya5312e22005-11-01 01:43:56 +03001989 dev->class = PCI_CLASS_STORAGE_SCSI;
1990 }
1991}
1992DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
1993
Daniel Yeisley9d265122005-12-05 07:06:43 -05001994/* Enable 1k I/O space granularity on the Intel P64H2 */
1995static void __devinit quirk_p64h2_1k_io(struct pci_dev *dev)
1996{
1997 u16 en1k;
1998 u8 io_base_lo, io_limit_lo;
1999 unsigned long base, limit;
2000 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
2001
2002 pci_read_config_word(dev, 0x40, &en1k);
2003
2004 if (en1k & 0x200) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002005 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
Daniel Yeisley9d265122005-12-05 07:06:43 -05002006
2007 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
2008 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
2009 base = (io_base_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
2010 limit = (io_limit_lo & (PCI_IO_RANGE_MASK | 0x0c)) << 8;
2011
2012 if (base <= limit) {
2013 res->start = base;
2014 res->end = limit + 0x3ff;
2015 }
2016 }
2017}
2018DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2019
Daniel Yeisley15a260d2006-12-21 14:34:57 -05002020/* Fix the IOBL_ADR for 1k I/O space granularity on the Intel P64H2
2021 * The IOBL_ADR gets re-written to 4k boundaries in pci_setup_bridge()
2022 * in drivers/pci/setup-bus.c
2023 */
2024static void __devinit quirk_p64h2_1k_io_fix_iobl(struct pci_dev *dev)
2025{
2026 u16 en1k, iobl_adr, iobl_adr_1k;
2027 struct resource *res = dev->resource + PCI_BRIDGE_RESOURCES;
2028
2029 pci_read_config_word(dev, 0x40, &en1k);
2030
2031 if (en1k & 0x200) {
2032 pci_read_config_word(dev, PCI_IO_BASE, &iobl_adr);
2033
2034 iobl_adr_1k = iobl_adr | (res->start >> 8) | (res->end & 0xfc00);
2035
2036 if (iobl_adr != iobl_adr_1k) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002037 dev_info(&dev->dev, "Fixing P64H2 IOBL_ADR from 0x%x to 0x%x for 1KB granularity\n",
Daniel Yeisley15a260d2006-12-21 14:34:57 -05002038 iobl_adr,iobl_adr_1k);
2039 pci_write_config_word(dev, PCI_IO_BASE, iobl_adr_1k);
2040 }
2041 }
2042}
2043DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io_fix_iobl);
2044
Brice Goglincf34a8e2006-06-13 14:35:42 -04002045/* Under some circumstances, AER is not linked with extended capabilities.
2046 * Force it to be linked by setting the corresponding control bit in the
2047 * config space.
2048 */
Alan Cox1597cac2006-12-04 15:14:45 -08002049static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
Brice Goglincf34a8e2006-06-13 14:35:42 -04002050{
2051 uint8_t b;
2052 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2053 if (!(b & 0x20)) {
2054 pci_write_config_byte(dev, 0xf41, b | 0x20);
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002055 dev_info(&dev->dev,
2056 "Linking AER extended capability\n");
Brice Goglincf34a8e2006-06-13 14:35:42 -04002057 }
2058 }
2059}
2060DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2061 quirk_nvidia_ck804_pcie_aer_ext_cap);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02002062DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
Alan Cox1597cac2006-12-04 15:14:45 -08002063 quirk_nvidia_ck804_pcie_aer_ext_cap);
Brice Goglincf34a8e2006-06-13 14:35:42 -04002064
Tim Yamin53a9bf42007-11-01 23:14:54 +00002065static void __devinit quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2066{
2067 /*
2068 * Disable PCI Bus Parking and PCI Master read caching on CX700
2069 * which causes unspecified timing errors with a VT6212L on the PCI
Tim Yaminca846392010-03-19 14:22:58 -07002070 * bus leading to USB2.0 packet loss.
2071 *
2072 * This quirk is only enabled if a second (on the external PCI bus)
2073 * VT6212L is found -- the CX700 core itself also contains a USB
2074 * host controller with the same PCI ID as the VT6212L.
Tim Yamin53a9bf42007-11-01 23:14:54 +00002075 */
2076
Tim Yaminca846392010-03-19 14:22:58 -07002077 /* Count VT6212L instances */
2078 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2079 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
Tim Yamin53a9bf42007-11-01 23:14:54 +00002080 uint8_t b;
Tim Yaminca846392010-03-19 14:22:58 -07002081
2082 /* p should contain the first (internal) VT6212L -- see if we have
2083 an external one by searching again */
2084 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2085 if (!p)
2086 return;
2087 pci_dev_put(p);
2088
Tim Yamin53a9bf42007-11-01 23:14:54 +00002089 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2090 if (b & 0x40) {
2091 /* Turn off PCI Bus Parking */
2092 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2093
Tim Yaminbc043272008-03-30 20:58:59 +01002094 dev_info(&dev->dev,
2095 "Disabling VIA CX700 PCI parking\n");
2096 }
2097 }
2098
2099 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2100 if (b != 0) {
Tim Yamin53a9bf42007-11-01 23:14:54 +00002101 /* Turn off PCI Master read caching */
2102 pci_write_config_byte(dev, 0x72, 0x0);
Tim Yaminbc043272008-03-30 20:58:59 +01002103
2104 /* Set PCI Master Bus time-out to "1x16 PCLK" */
Tim Yamin53a9bf42007-11-01 23:14:54 +00002105 pci_write_config_byte(dev, 0x75, 0x1);
Tim Yaminbc043272008-03-30 20:58:59 +01002106
2107 /* Disable "Read FIFO Timer" */
Tim Yamin53a9bf42007-11-01 23:14:54 +00002108 pci_write_config_byte(dev, 0x77, 0x0);
2109
Bjorn Helgaasd6505a52008-02-29 16:12:18 -07002110 dev_info(&dev->dev,
Tim Yaminbc043272008-03-30 20:58:59 +01002111 "Disabling VIA CX700 PCI caching\n");
Tim Yamin53a9bf42007-11-01 23:14:54 +00002112 }
2113 }
2114}
Tim Yaminca846392010-03-19 14:22:58 -07002115DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
Tim Yamin53a9bf42007-11-01 23:14:54 +00002116
Benjamin Li99cb233d2008-07-02 10:59:04 -07002117/*
2118 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2119 * VPD end tag will hang the device. This problem was initially
2120 * observed when a vpd entry was created in sysfs
2121 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2122 * will dump 32k of data. Reading a full 32k will cause an access
2123 * beyond the VPD end tag causing the device to hang. Once the device
2124 * is hung, the bnx2 driver will not be able to reset the device.
2125 * We believe that it is legal to read beyond the end tag and
2126 * therefore the solution is to limit the read/write length.
2127 */
2128static void __devinit quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
2129{
Eric Dumazet9d82d8e2008-07-31 20:27:31 +02002130 /*
Dean Hildebrand35405f22008-08-07 17:31:45 -07002131 * Only disable the VPD capability for 5706, 5706S, 5708,
2132 * 5708S and 5709 rev. A
Eric Dumazet9d82d8e2008-07-31 20:27:31 +02002133 */
Benjamin Li99cb233d2008-07-02 10:59:04 -07002134 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
Dean Hildebrand35405f22008-08-07 17:31:45 -07002135 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
Benjamin Li99cb233d2008-07-02 10:59:04 -07002136 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
Eric Dumazet9d82d8e2008-07-31 20:27:31 +02002137 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
Benjamin Li99cb233d2008-07-02 10:59:04 -07002138 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2139 (dev->revision & 0xf0) == 0x0)) {
2140 if (dev->vpd)
2141 dev->vpd->len = 0x80;
2142 }
2143}
2144
Yu Zhaobffadff2008-10-28 14:44:11 +08002145DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2146 PCI_DEVICE_ID_NX2_5706,
2147 quirk_brcm_570x_limit_vpd);
2148DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2149 PCI_DEVICE_ID_NX2_5706S,
2150 quirk_brcm_570x_limit_vpd);
2151DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2152 PCI_DEVICE_ID_NX2_5708,
2153 quirk_brcm_570x_limit_vpd);
2154DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2155 PCI_DEVICE_ID_NX2_5708S,
2156 quirk_brcm_570x_limit_vpd);
2157DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2158 PCI_DEVICE_ID_NX2_5709,
2159 quirk_brcm_570x_limit_vpd);
2160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2161 PCI_DEVICE_ID_NX2_5709S,
2162 quirk_brcm_570x_limit_vpd);
Benjamin Li99cb233d2008-07-02 10:59:04 -07002163
Michal Miroslaw26c56dc2009-05-12 13:49:26 -07002164/* Originally in EDAC sources for i82875P:
2165 * Intel tells BIOS developers to hide device 6 which
2166 * configures the overflow device access containing
2167 * the DRBs - this is where we expose device 6.
2168 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2169 */
2170static void __devinit quirk_unhide_mch_dev6(struct pci_dev *dev)
2171{
2172 u8 reg;
2173
2174 if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
2175 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2176 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2177 }
2178}
2179
2180DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2181 quirk_unhide_mch_dev6);
2182DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2183 quirk_unhide_mch_dev6);
2184
Chris Metcalff02cbbe2010-11-02 12:05:10 -04002185#ifdef CONFIG_TILE
2186/*
2187 * The Tilera TILEmpower platform needs to set the link speed
2188 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2189 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2190 * capability register of the PEX8624 PCIe switch. The switch
2191 * supports link speed auto negotiation, but falsely sets
2192 * the link speed to 5GT/s.
2193 */
2194static void __devinit quirk_tile_plx_gen1(struct pci_dev *dev)
2195{
2196 if (tile_plx_gen1) {
2197 pci_write_config_dword(dev, 0x98, 0x1);
2198 mdelay(50);
2199 }
2200}
2201DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2202#endif /* CONFIG_TILE */
Michal Miroslaw26c56dc2009-05-12 13:49:26 -07002203
Brice Goglin3f79e102006-08-31 01:54:56 -04002204#ifdef CONFIG_PCI_MSI
Tejun Heoebdf7d32007-05-31 00:40:48 -07002205/* Some chipsets do not support MSI. We cannot easily rely on setting
2206 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
2207 * some other busses controlled by the chipset even if Linux is not
2208 * aware of it. Instead of setting the flag on all busses in the
2209 * machine, simply disable MSI globally.
Brice Goglin3f79e102006-08-31 01:54:56 -04002210 */
Tejun Heoebdf7d32007-05-31 00:40:48 -07002211static void __init quirk_disable_all_msi(struct pci_dev *dev)
Brice Goglin3f79e102006-08-31 01:54:56 -04002212{
Michael Ellerman88187df2007-01-25 19:34:07 +11002213 pci_no_msi();
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002214 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
Brice Goglin3f79e102006-08-31 01:54:56 -04002215}
Tejun Heoebdf7d32007-05-31 00:40:48 -07002216DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2217DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2218DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
Tejun Heo66d715c2008-07-04 09:59:32 -07002219DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
Jay Cliburn184b8122007-05-26 17:01:04 -05002220DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
Thomas Renninger162dedd2009-04-03 06:34:00 -07002221DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
Tejun Heo549e1562010-05-23 10:22:55 +02002222DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
Brice Goglin3f79e102006-08-31 01:54:56 -04002223
2224/* Disable MSI on chipsets that are known to not support it */
2225static void __devinit quirk_disable_msi(struct pci_dev *dev)
2226{
2227 if (dev->subordinate) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002228 dev_warn(&dev->dev, "MSI quirk detected; "
2229 "subordinate MSI disabled\n");
Brice Goglin3f79e102006-08-31 01:54:56 -04002230 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2231 }
2232}
2233DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
Matthew Wilcox134b3452010-03-24 07:11:01 -06002234DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
Alex Deucher9313ff42010-05-18 10:42:53 -04002235DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
Brice Goglin6397c752006-08-31 01:55:32 -04002236
Clemens Ladischaff61362010-05-26 12:21:10 +02002237/*
2238 * The APC bridge device in AMD 780 family northbridges has some random
2239 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2240 * we use the possible vendor/device IDs of the host bridge for the
2241 * declared quirk, and search for the APC bridge by slot number.
2242 */
2243static void __devinit quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2244{
2245 struct pci_dev *apc_bridge;
2246
2247 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2248 if (apc_bridge) {
2249 if (apc_bridge->device == 0x9602)
2250 quirk_disable_msi(apc_bridge);
2251 pci_dev_put(apc_bridge);
2252 }
2253}
2254DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2255DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2256
Brice Goglin6397c752006-08-31 01:55:32 -04002257/* Go through the list of Hypertransport capabilities and
2258 * return 1 if a HT MSI capability is found and enabled */
2259static int __devinit msi_ht_cap_enabled(struct pci_dev *dev)
2260{
Michael Ellerman7a380502006-11-22 18:26:21 +11002261 int pos, ttl = 48;
2262
2263 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2264 while (pos && ttl--) {
2265 u8 flags;
2266
2267 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2268 &flags) == 0)
2269 {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002270 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
Michael Ellerman7a380502006-11-22 18:26:21 +11002271 flags & HT_MSI_FLAGS_ENABLE ?
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002272 "enabled" : "disabled");
Michael Ellerman7a380502006-11-22 18:26:21 +11002273 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
Brice Goglin6397c752006-08-31 01:55:32 -04002274 }
Michael Ellerman7a380502006-11-22 18:26:21 +11002275
2276 pos = pci_find_next_ht_capability(dev, pos,
2277 HT_CAPTYPE_MSI_MAPPING);
Brice Goglin6397c752006-08-31 01:55:32 -04002278 }
2279 return 0;
2280}
2281
2282/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
2283static void __devinit quirk_msi_ht_cap(struct pci_dev *dev)
2284{
2285 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002286 dev_warn(&dev->dev, "MSI quirk detected; "
2287 "subordinate MSI disabled\n");
Brice Goglin6397c752006-08-31 01:55:32 -04002288 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2289 }
2290}
2291DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2292 quirk_msi_ht_cap);
Sebastien Dugue6bae1d92007-12-13 16:09:25 -08002293
Brice Goglin6397c752006-08-31 01:55:32 -04002294/* The nVidia CK804 chipset may have 2 HT MSI mappings.
2295 * MSI are supported if the MSI capability set in any of these mappings.
2296 */
2297static void __devinit quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2298{
2299 struct pci_dev *pdev;
2300
2301 if (!dev->subordinate)
2302 return;
2303
2304 /* check HT MSI cap on this chipset and the root one.
2305 * a single one having MSI is enough to be sure that MSI are supported.
2306 */
Alan Cox11f242f2006-10-10 14:39:00 -07002307 pdev = pci_get_slot(dev->bus, 0);
Jesper Juhl9ac0ce82006-12-04 15:14:48 -08002308 if (!pdev)
2309 return;
David Rientjes0c875c282006-12-03 11:55:34 -08002310 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002311 dev_warn(&dev->dev, "MSI quirk detected; "
2312 "subordinate MSI disabled\n");
Brice Goglin6397c752006-08-31 01:55:32 -04002313 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2314 }
Alan Cox11f242f2006-10-10 14:39:00 -07002315 pci_dev_put(pdev);
Brice Goglin6397c752006-08-31 01:55:32 -04002316}
2317DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2318 quirk_nvidia_ck804_msi_ht_cap);
David Millerba698ad2007-10-25 01:16:30 -07002319
Bjorn Helgaas415b6d02008-02-29 16:04:39 -07002320/* Force enable MSI mapping capability on HT bridges */
2321static void __devinit ht_enable_msi_mapping(struct pci_dev *dev)
Peer Chen9dc625e2008-02-04 23:50:13 -08002322{
2323 int pos, ttl = 48;
2324
2325 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2326 while (pos && ttl--) {
2327 u8 flags;
2328
2329 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2330 &flags) == 0) {
2331 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2332
2333 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2334 flags | HT_MSI_FLAGS_ENABLE);
2335 }
2336 pos = pci_find_next_ht_capability(dev, pos,
2337 HT_CAPTYPE_MSI_MAPPING);
2338 }
2339}
Bjorn Helgaas415b6d02008-02-29 16:04:39 -07002340DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2341 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2342 ht_enable_msi_mapping);
Peer Chen9dc625e2008-02-04 23:50:13 -08002343
Yinghai Lue0ae4f52009-02-17 20:40:09 -08002344DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2345 ht_enable_msi_mapping);
2346
Ben Hutchingse4146bb2010-05-16 02:28:49 +01002347/* The P5N32-SLI motherboards from Asus have a problem with msi
Andreas Petlund75e07fc2008-11-20 20:42:25 -08002348 * for the MCP55 NIC. It is not yet determined whether the msi problem
2349 * also affects other devices. As for now, turn off msi for this device.
2350 */
2351static void __devinit nvenet_msi_disable(struct pci_dev *dev)
2352{
Jean Delvare9251bac2011-05-15 18:13:46 +02002353 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2354
2355 if (board_name &&
2356 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2357 strstr(board_name, "P5N32-E SLI"))) {
Andreas Petlund75e07fc2008-11-20 20:42:25 -08002358 dev_info(&dev->dev,
Ben Hutchingse4146bb2010-05-16 02:28:49 +01002359 "Disabling msi for MCP55 NIC on P5N32-SLI\n");
Andreas Petlund75e07fc2008-11-20 20:42:25 -08002360 dev->no_msi = 1;
2361 }
2362}
2363DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2364 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2365 nvenet_msi_disable);
2366
Neil Horman66db60e2010-09-21 13:54:39 -04002367/*
2368 * Some versions of the MCP55 bridge from nvidia have a legacy irq routing
2369 * config register. This register controls the routing of legacy interrupts
2370 * from devices that route through the MCP55. If this register is misprogramed
2371 * interrupts are only sent to the bsp, unlike conventional systems where the
2372 * irq is broadxast to all online cpus. Not having this register set
2373 * properly prevents kdump from booting up properly, so lets make sure that
2374 * we have it set correctly.
2375 * Note this is an undocumented register.
2376 */
2377static void __devinit nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2378{
2379 u32 cfg;
2380
Neil Horman49c2fa082010-12-08 09:47:48 -05002381 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2382 return;
2383
Neil Horman66db60e2010-09-21 13:54:39 -04002384 pci_read_config_dword(dev, 0x74, &cfg);
2385
2386 if (cfg & ((1 << 2) | (1 << 15))) {
2387 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2388 cfg &= ~((1 << 2) | (1 << 15));
2389 pci_write_config_dword(dev, 0x74, cfg);
2390 }
2391}
2392
2393DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2394 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2395 nvbridge_check_legacy_irq_routing);
2396
2397DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2398 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2399 nvbridge_check_legacy_irq_routing);
2400
Yinghai Lude745302009-03-20 19:29:41 -07002401static int __devinit ht_check_msi_mapping(struct pci_dev *dev)
2402{
2403 int pos, ttl = 48;
2404 int found = 0;
2405
2406 /* check if there is HT MSI cap or enabled on this device */
2407 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2408 while (pos && ttl--) {
2409 u8 flags;
2410
2411 if (found < 1)
2412 found = 1;
2413 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2414 &flags) == 0) {
2415 if (flags & HT_MSI_FLAGS_ENABLE) {
2416 if (found < 2) {
2417 found = 2;
2418 break;
2419 }
2420 }
2421 }
2422 pos = pci_find_next_ht_capability(dev, pos,
2423 HT_CAPTYPE_MSI_MAPPING);
2424 }
2425
2426 return found;
2427}
2428
2429static int __devinit host_bridge_with_leaf(struct pci_dev *host_bridge)
2430{
2431 struct pci_dev *dev;
2432 int pos;
2433 int i, dev_no;
2434 int found = 0;
2435
2436 dev_no = host_bridge->devfn >> 3;
2437 for (i = dev_no + 1; i < 0x20; i++) {
2438 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2439 if (!dev)
2440 continue;
2441
2442 /* found next host bridge ?*/
2443 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2444 if (pos != 0) {
2445 pci_dev_put(dev);
2446 break;
2447 }
2448
2449 if (ht_check_msi_mapping(dev)) {
2450 found = 1;
2451 pci_dev_put(dev);
2452 break;
2453 }
2454 pci_dev_put(dev);
2455 }
2456
2457 return found;
2458}
2459
Yinghai Lueeafda72009-03-29 12:30:05 -07002460#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2461#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2462
2463static int __devinit is_end_of_ht_chain(struct pci_dev *dev)
2464{
2465 int pos, ctrl_off;
2466 int end = 0;
2467 u16 flags, ctrl;
2468
2469 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2470
2471 if (!pos)
2472 goto out;
2473
2474 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2475
2476 ctrl_off = ((flags >> 10) & 1) ?
2477 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2478 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2479
2480 if (ctrl & (1 << 6))
2481 end = 1;
2482
2483out:
2484 return end;
2485}
2486
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002487static void __devinit nv_ht_enable_msi_mapping(struct pci_dev *dev)
2488{
2489 struct pci_dev *host_bridge;
2490 int pos;
2491 int i, dev_no;
2492 int found = 0;
2493
2494 dev_no = dev->devfn >> 3;
2495 for (i = dev_no; i >= 0; i--) {
2496 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2497 if (!host_bridge)
2498 continue;
2499
2500 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2501 if (pos != 0) {
2502 found = 1;
2503 break;
2504 }
2505 pci_dev_put(host_bridge);
2506 }
2507
2508 if (!found)
2509 return;
2510
Yinghai Lueeafda72009-03-29 12:30:05 -07002511 /* don't enable end_device/host_bridge with leaf directly here */
2512 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2513 host_bridge_with_leaf(host_bridge))
Yinghai Lude745302009-03-20 19:29:41 -07002514 goto out;
2515
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002516 /* root did that ! */
2517 if (msi_ht_cap_enabled(host_bridge))
2518 goto out;
2519
2520 ht_enable_msi_mapping(dev);
2521
2522out:
2523 pci_dev_put(host_bridge);
2524}
2525
2526static void __devinit ht_disable_msi_mapping(struct pci_dev *dev)
2527{
2528 int pos, ttl = 48;
2529
2530 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2531 while (pos && ttl--) {
2532 u8 flags;
2533
2534 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2535 &flags) == 0) {
Prakash Punnoor6a958d52009-03-06 10:10:35 +01002536 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002537
2538 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2539 flags & ~HT_MSI_FLAGS_ENABLE);
2540 }
2541 pos = pci_find_next_ht_capability(dev, pos,
2542 HT_CAPTYPE_MSI_MAPPING);
2543 }
2544}
2545
Yinghai Lude745302009-03-20 19:29:41 -07002546static void __devinit __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
Peer Chen9dc625e2008-02-04 23:50:13 -08002547{
2548 struct pci_dev *host_bridge;
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002549 int pos;
2550 int found;
2551
Rafael J. Wysocki3d2a5312010-07-23 22:19:55 +02002552 if (!pci_msi_enabled())
2553 return;
2554
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002555 /* check if there is HT MSI cap or enabled on this device */
2556 found = ht_check_msi_mapping(dev);
2557
2558 /* no HT MSI CAP */
2559 if (found == 0)
2560 return;
Peer Chen9dc625e2008-02-04 23:50:13 -08002561
2562 /*
2563 * HT MSI mapping should be disabled on devices that are below
2564 * a non-Hypertransport host bridge. Locate the host bridge...
2565 */
2566 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2567 if (host_bridge == NULL) {
2568 dev_warn(&dev->dev,
2569 "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2570 return;
2571 }
2572
2573 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2574 if (pos != 0) {
2575 /* Host bridge is to HT */
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002576 if (found == 1) {
2577 /* it is not enabled, try to enable it */
Yinghai Lude745302009-03-20 19:29:41 -07002578 if (all)
2579 ht_enable_msi_mapping(dev);
2580 else
2581 nv_ht_enable_msi_mapping(dev);
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002582 }
Peer Chen9dc625e2008-02-04 23:50:13 -08002583 return;
2584 }
2585
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002586 /* HT MSI is not enabled */
2587 if (found == 1)
2588 return;
Peer Chen9dc625e2008-02-04 23:50:13 -08002589
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002590 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2591 ht_disable_msi_mapping(dev);
Peer Chen9dc625e2008-02-04 23:50:13 -08002592}
Yinghai Lude745302009-03-20 19:29:41 -07002593
2594static void __devinit nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2595{
2596 return __nv_msi_ht_cap_quirk(dev, 1);
2597}
2598
2599static void __devinit nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2600{
2601 return __nv_msi_ht_cap_quirk(dev, 0);
2602}
2603
2604DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
Tejun Heo6dab62e2009-07-21 16:08:43 -07002605DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
Yinghai Lude745302009-03-20 19:29:41 -07002606
2607DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
Tejun Heo6dab62e2009-07-21 16:08:43 -07002608DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
Peer Chen9dc625e2008-02-04 23:50:13 -08002609
David Millerba698ad2007-10-25 01:16:30 -07002610static void __devinit quirk_msi_intx_disable_bug(struct pci_dev *dev)
2611{
2612 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2613}
Shane Huang4600c9d72008-01-25 15:46:24 +09002614static void __devinit quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2615{
2616 struct pci_dev *p;
2617
2618 /* SB700 MSI issue will be fixed at HW level from revision A21,
2619 * we need check PCI REVISION ID of SMBus controller to get SB700
2620 * revision.
2621 */
2622 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2623 NULL);
2624 if (!p)
2625 return;
2626
2627 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2628 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2629 pci_dev_put(p);
2630}
David Millerba698ad2007-10-25 01:16:30 -07002631DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2632 PCI_DEVICE_ID_TIGON3_5780,
2633 quirk_msi_intx_disable_bug);
2634DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2635 PCI_DEVICE_ID_TIGON3_5780S,
2636 quirk_msi_intx_disable_bug);
2637DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2638 PCI_DEVICE_ID_TIGON3_5714,
2639 quirk_msi_intx_disable_bug);
2640DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2641 PCI_DEVICE_ID_TIGON3_5714S,
2642 quirk_msi_intx_disable_bug);
2643DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2644 PCI_DEVICE_ID_TIGON3_5715,
2645 quirk_msi_intx_disable_bug);
2646DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2647 PCI_DEVICE_ID_TIGON3_5715S,
2648 quirk_msi_intx_disable_bug);
2649
David Millerbc38b412007-10-25 01:16:52 -07002650DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
Shane Huang4600c9d72008-01-25 15:46:24 +09002651 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002652DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
Shane Huang4600c9d72008-01-25 15:46:24 +09002653 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002654DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
Shane Huang4600c9d72008-01-25 15:46:24 +09002655 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002656DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
Shane Huang4600c9d72008-01-25 15:46:24 +09002657 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002658DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
Shane Huang4600c9d72008-01-25 15:46:24 +09002659 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002660
2661DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2662 quirk_msi_intx_disable_bug);
2663DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2664 quirk_msi_intx_disable_bug);
2665DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2666 quirk_msi_intx_disable_bug);
2667
Brice Goglin3f79e102006-08-31 01:54:56 -04002668#endif /* CONFIG_PCI_MSI */
Thomas Petazzoni3d137312008-08-19 10:28:24 +02002669
Felix Radensky33223402010-03-28 16:02:02 +03002670/* Allow manual resource allocation for PCI hotplug bridges
2671 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2672 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
2673 * kernel fails to allocate resources when hotplug device is
2674 * inserted and PCI bus is rescanned.
2675 */
2676static void __devinit quirk_hotplug_bridge(struct pci_dev *dev)
2677{
2678 dev->is_hotplug_bridge = 1;
2679}
2680
2681DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2682
Maxim Levitsky03cd8f72010-03-05 13:43:20 -08002683/*
2684 * This is a quirk for the Ricoh MMC controller found as a part of
2685 * some mulifunction chips.
2686
Lucas De Marchi25985ed2011-03-30 22:57:33 -03002687 * This is very similar and based on the ricoh_mmc driver written by
Maxim Levitsky03cd8f72010-03-05 13:43:20 -08002688 * Philip Langdale. Thank you for these magic sequences.
2689 *
2690 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2691 * and one or both of cardbus or firewire.
2692 *
2693 * It happens that they implement SD and MMC
2694 * support as separate controllers (and PCI functions). The linux SDHCI
2695 * driver supports MMC cards but the chip detects MMC cards in hardware
2696 * and directs them to the MMC controller - so the SDHCI driver never sees
2697 * them.
2698 *
2699 * To get around this, we must disable the useless MMC controller.
2700 * At that point, the SDHCI controller will start seeing them
2701 * It seems to be the case that the relevant PCI registers to deactivate the
2702 * MMC controller live on PCI function 0, which might be the cardbus controller
2703 * or the firewire controller, depending on the particular chip in question
2704 *
2705 * This has to be done early, because as soon as we disable the MMC controller
2706 * other pci functions shift up one level, e.g. function #2 becomes function
2707 * #1, and this will confuse the pci core.
2708 */
2709
2710#ifdef CONFIG_MMC_RICOH_MMC
2711static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2712{
2713 /* disable via cardbus interface */
2714 u8 write_enable;
2715 u8 write_target;
2716 u8 disable;
2717
2718 /* disable must be done via function #0 */
2719 if (PCI_FUNC(dev->devfn))
2720 return;
2721
2722 pci_read_config_byte(dev, 0xB7, &disable);
2723 if (disable & 0x02)
2724 return;
2725
2726 pci_read_config_byte(dev, 0x8E, &write_enable);
2727 pci_write_config_byte(dev, 0x8E, 0xAA);
2728 pci_read_config_byte(dev, 0x8D, &write_target);
2729 pci_write_config_byte(dev, 0x8D, 0xB7);
2730 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2731 pci_write_config_byte(dev, 0x8E, write_enable);
2732 pci_write_config_byte(dev, 0x8D, write_target);
2733
2734 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2735 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2736}
2737DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2738DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2739
2740static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2741{
2742 /* disable via firewire interface */
2743 u8 write_enable;
2744 u8 disable;
2745
2746 /* disable must be done via function #0 */
2747 if (PCI_FUNC(dev->devfn))
2748 return;
Manoj Iyer15bed0f2011-07-11 16:28:35 -05002749 /*
2750 * RICOH 0xe823 SD/MMC card reader fails to recognize
2751 * certain types of SD/MMC cards. Lowering the SD base
2752 * clock frequency from 200Mhz to 50Mhz fixes this issue.
2753 *
2754 * 0x150 - SD2.0 mode enable for changing base clock
2755 * frequency to 50Mhz
2756 * 0xe1 - Base clock frequency
2757 * 0x32 - 50Mhz new clock frequency
2758 * 0xf9 - Key register for 0x150
2759 * 0xfc - key register for 0xe1
2760 */
2761 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
2762 pci_write_config_byte(dev, 0xf9, 0xfc);
2763 pci_write_config_byte(dev, 0x150, 0x10);
2764 pci_write_config_byte(dev, 0xf9, 0x00);
2765 pci_write_config_byte(dev, 0xfc, 0x01);
2766 pci_write_config_byte(dev, 0xe1, 0x32);
2767 pci_write_config_byte(dev, 0xfc, 0x00);
2768
2769 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
2770 }
Josh Boyer3e309cd2011-10-05 11:44:50 -04002771
2772 pci_read_config_byte(dev, 0xCB, &disable);
2773
2774 if (disable & 0x02)
2775 return;
2776
2777 pci_read_config_byte(dev, 0xCA, &write_enable);
2778 pci_write_config_byte(dev, 0xCA, 0x57);
2779 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2780 pci_write_config_byte(dev, 0xCA, write_enable);
2781
2782 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2783 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2784
Maxim Levitsky03cd8f72010-03-05 13:43:20 -08002785}
2786DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2787DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
Manoj Iyerbe98ca62011-05-26 11:19:05 -05002788DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2789DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
Maxim Levitsky03cd8f72010-03-05 13:43:20 -08002790#endif /*CONFIG_MMC_RICOH_MMC*/
2791
Suresh Siddhad3f13812011-08-23 17:05:25 -07002792#ifdef CONFIG_DMAR_TABLE
Suresh Siddha254e4202010-12-06 12:26:30 -08002793#define VTUNCERRMSK_REG 0x1ac
2794#define VTD_MSK_SPEC_ERRORS (1 << 31)
2795/*
2796 * This is a quirk for masking vt-d spec defined errors to platform error
2797 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2798 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2799 * on the RAS config settings of the platform) when a vt-d fault happens.
2800 * The resulting SMI caused the system to hang.
2801 *
2802 * VT-d spec related errors are already handled by the VT-d OS code, so no
2803 * need to report the same error through other channels.
2804 */
2805static void vtd_mask_spec_errors(struct pci_dev *dev)
2806{
2807 u32 word;
2808
2809 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2810 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
2811}
2812DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2813DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2814#endif
Maxim Levitsky03cd8f72010-03-05 13:43:20 -08002815
Hemant Pedanekar63c44082011-04-05 12:32:50 +05302816static void __devinit fixup_ti816x_class(struct pci_dev* dev)
2817{
2818 /* TI 816x devices do not have class code set when in PCIe boot mode */
2819 if (dev->class == PCI_CLASS_NOT_DEFINED) {
2820 dev_info(&dev->dev, "Setting PCI class for 816x PCIe device\n");
2821 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO;
2822 }
2823}
2824DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_TI, 0xb800, fixup_ti816x_class);
2825
Ben Hutchingsa94d0722011-10-05 22:35:03 +01002826/* Some PCIe devices do not work reliably with the claimed maximum
2827 * payload size supported.
2828 */
2829static void __devinit fixup_mpss_256(struct pci_dev *dev)
2830{
2831 dev->pcie_mpss = 1; /* 256 bytes */
2832}
2833DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2834 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
2835DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2836 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
2837DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2838 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
2839
Jon Masond387a8d2011-10-14 14:56:13 -05002840/* Intel 5000 and 5100 Memory controllers have an errata with read completion
2841 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
2842 * Since there is no way of knowing what the PCIE MPS on each fabric will be
2843 * until all of the devices are discovered and buses walked, read completion
2844 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
2845 * it is possible to hotplug a device with MPS of 256B.
2846 */
2847static void __devinit quirk_intel_mc_errata(struct pci_dev *dev)
2848{
2849 int err;
2850 u16 rcc;
2851
2852 if (pcie_bus_config == PCIE_BUS_TUNE_OFF)
2853 return;
2854
2855 /* Intel errata specifies bits to change but does not say what they are.
2856 * Keeping them magical until such time as the registers and values can
2857 * be explained.
2858 */
2859 err = pci_read_config_word(dev, 0x48, &rcc);
2860 if (err) {
2861 dev_err(&dev->dev, "Error attempting to read the read "
2862 "completion coalescing register.\n");
2863 return;
2864 }
2865
2866 if (!(rcc & (1 << 10)))
2867 return;
2868
2869 rcc &= ~(1 << 10);
2870
2871 err = pci_write_config_word(dev, 0x48, rcc);
2872 if (err) {
2873 dev_err(&dev->dev, "Error attempting to write the read "
2874 "completion coalescing register.\n");
2875 return;
2876 }
2877
2878 pr_info_once("Read completion coalescing disabled due to hardware "
2879 "errata relating to 256B MPS.\n");
2880}
2881/* Intel 5000 series memory controllers and ports 2-7 */
2882DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
2883DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
2884DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
2885DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
2886DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
2887DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
2888DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
2889DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
2890DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
2891DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
2892DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
2893DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
2894DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
2895DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
2896/* Intel 5100 series memory controllers and ports 2-7 */
2897DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
2898DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
2899DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
2900DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
2901DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
2902DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
2903DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
2904DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
2905DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
2906DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
2907DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
2908
Jesse Barnesbfb0f332008-10-27 17:50:21 -07002909static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
2910 struct pci_fixup *end)
Thomas Petazzoni3d137312008-08-19 10:28:24 +02002911{
2912 while (f < end) {
2913 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
Jesse Barnesbfb0f332008-10-27 17:50:21 -07002914 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
Yinghai Luc9bbb4a2008-09-24 19:04:33 -07002915 dev_dbg(&dev->dev, "calling %pF\n", f->hook);
Thomas Petazzoni3d137312008-08-19 10:28:24 +02002916 f->hook(dev);
2917 }
2918 f++;
2919 }
2920}
2921
2922extern struct pci_fixup __start_pci_fixups_early[];
2923extern struct pci_fixup __end_pci_fixups_early[];
2924extern struct pci_fixup __start_pci_fixups_header[];
2925extern struct pci_fixup __end_pci_fixups_header[];
2926extern struct pci_fixup __start_pci_fixups_final[];
2927extern struct pci_fixup __end_pci_fixups_final[];
2928extern struct pci_fixup __start_pci_fixups_enable[];
2929extern struct pci_fixup __end_pci_fixups_enable[];
2930extern struct pci_fixup __start_pci_fixups_resume[];
2931extern struct pci_fixup __end_pci_fixups_resume[];
2932extern struct pci_fixup __start_pci_fixups_resume_early[];
2933extern struct pci_fixup __end_pci_fixups_resume_early[];
2934extern struct pci_fixup __start_pci_fixups_suspend[];
2935extern struct pci_fixup __end_pci_fixups_suspend[];
2936
2937
2938void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
2939{
2940 struct pci_fixup *start, *end;
2941
2942 switch(pass) {
2943 case pci_fixup_early:
2944 start = __start_pci_fixups_early;
2945 end = __end_pci_fixups_early;
2946 break;
2947
2948 case pci_fixup_header:
2949 start = __start_pci_fixups_header;
2950 end = __end_pci_fixups_header;
2951 break;
2952
2953 case pci_fixup_final:
2954 start = __start_pci_fixups_final;
2955 end = __end_pci_fixups_final;
2956 break;
2957
2958 case pci_fixup_enable:
2959 start = __start_pci_fixups_enable;
2960 end = __end_pci_fixups_enable;
2961 break;
2962
2963 case pci_fixup_resume:
2964 start = __start_pci_fixups_resume;
2965 end = __end_pci_fixups_resume;
2966 break;
2967
2968 case pci_fixup_resume_early:
2969 start = __start_pci_fixups_resume_early;
2970 end = __end_pci_fixups_resume_early;
2971 break;
2972
2973 case pci_fixup_suspend:
2974 start = __start_pci_fixups_suspend;
2975 end = __end_pci_fixups_suspend;
2976 break;
2977
2978 default:
2979 /* stupid compiler warning, you would think with an enum... */
2980 return;
2981 }
2982 pci_do_fixups(dev, start, end);
2983}
Rafael J. Wysocki93177a72010-01-02 22:57:24 +01002984EXPORT_SYMBOL(pci_fixup_device);
David Woodhouse8d86fb22009-10-12 12:48:43 +01002985
David Woodhouse00010262009-10-12 12:50:34 +01002986static int __init pci_apply_final_quirks(void)
David Woodhouse8d86fb22009-10-12 12:48:43 +01002987{
2988 struct pci_dev *dev = NULL;
Jesse Barnesac1aa472009-10-26 13:20:44 -07002989 u8 cls = 0;
2990 u8 tmp;
2991
2992 if (pci_cache_line_size)
2993 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
2994 pci_cache_line_size << 2);
David Woodhouse8d86fb22009-10-12 12:48:43 +01002995
Kulikov Vasiliy4e344b12010-07-03 20:04:39 +04002996 for_each_pci_dev(dev) {
David Woodhouse8d86fb22009-10-12 12:48:43 +01002997 pci_fixup_device(pci_fixup_final, dev);
Jesse Barnesac1aa472009-10-26 13:20:44 -07002998 /*
2999 * If arch hasn't set it explicitly yet, use the CLS
3000 * value shared by all PCI devices. If there's a
3001 * mismatch, fall back to the default value.
3002 */
3003 if (!pci_cache_line_size) {
3004 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
3005 if (!cls)
3006 cls = tmp;
3007 if (!tmp || cls == tmp)
3008 continue;
3009
3010 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), "
3011 "using %u bytes\n", cls << 2, tmp << 2,
3012 pci_dfl_cache_line_size << 2);
3013 pci_cache_line_size = pci_dfl_cache_line_size;
3014 }
3015 }
3016 if (!pci_cache_line_size) {
3017 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3018 cls << 2, pci_dfl_cache_line_size << 2);
Csaba Henk2820f332009-12-15 17:55:25 +05303019 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
David Woodhouse8d86fb22009-10-12 12:48:43 +01003020 }
3021
3022 return 0;
3023}
3024
David Woodhousecf6f3bf2009-10-12 12:51:22 +01003025fs_initcall_sync(pci_apply_final_quirks);
Dexuan Cuib9c3b262009-12-07 13:03:21 +08003026
3027/*
3028 * Followings are device-specific reset methods which can be used to
3029 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3030 * not available.
3031 */
Dexuan Cuiaeb30012009-12-07 13:03:22 +08003032static int reset_intel_generic_dev(struct pci_dev *dev, int probe)
3033{
3034 int pos;
3035
3036 /* only implement PCI_CLASS_SERIAL_USB at present */
3037 if (dev->class == PCI_CLASS_SERIAL_USB) {
3038 pos = pci_find_capability(dev, PCI_CAP_ID_VNDR);
3039 if (!pos)
3040 return -ENOTTY;
3041
3042 if (probe)
3043 return 0;
3044
3045 pci_write_config_byte(dev, pos + 0x4, 1);
3046 msleep(100);
3047
3048 return 0;
3049 } else {
3050 return -ENOTTY;
3051 }
3052}
3053
Dexuan Cuic763e7b2009-12-07 13:03:23 +08003054static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3055{
3056 int pos;
3057
3058 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
3059 if (!pos)
3060 return -ENOTTY;
3061
3062 if (probe)
3063 return 0;
3064
3065 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL,
3066 PCI_EXP_DEVCTL_BCR_FLR);
3067 msleep(100);
3068
3069 return 0;
3070}
3071
3072#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3073
Rafael J. Wysocki5b889bf2009-12-31 19:06:35 +01003074static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
Dexuan Cuic763e7b2009-12-07 13:03:23 +08003075 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3076 reset_intel_82599_sfp_virtfn },
Dexuan Cuiaeb30012009-12-07 13:03:22 +08003077 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
3078 reset_intel_generic_dev },
Dexuan Cuib9c3b262009-12-07 13:03:21 +08003079 { 0 }
3080};
Rafael J. Wysocki5b889bf2009-12-31 19:06:35 +01003081
3082int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3083{
Linus Torvaldsdf9d1e82009-12-31 16:44:43 -08003084 const struct pci_dev_reset_methods *i;
Rafael J. Wysocki5b889bf2009-12-31 19:06:35 +01003085
3086 for (i = pci_dev_reset_methods; i->reset; i++) {
3087 if ((i->vendor == dev->vendor ||
3088 i->vendor == (u16)PCI_ANY_ID) &&
3089 (i->device == dev->device ||
3090 i->device == (u16)PCI_ANY_ID))
3091 return i->reset(dev, probe);
3092 }
3093
3094 return -ENOTTY;
3095}