blob: 23c8a7bf24de5d0d1db8a09e832bf91f61d8246a [file] [log] [blame]
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/socionext,uniphier-mio-dmac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: UniPhier Media IO DMA controller
description: |
This works as an external DMA engine for SD/eMMC controllers etc.
found in UniPhier LD4, Pro4, sLD8 SoCs.
maintainers:
- Masahiro Yamada <yamada.masahiro@socionext.com>
allOf:
- $ref: dma-controller.yaml#
properties:
compatible:
const: socionext,uniphier-mio-dmac
reg:
maxItems: 1
interrupts:
description: |
A list of interrupt specifiers associated with the DMA channels.
The number of interrupt lines is SoC-dependent.
clocks:
maxItems: 1
resets:
maxItems: 1
'#dma-cells':
description: The single cell represents the channel index.
const: 1
required:
- compatible
- reg
- interrupts
- clocks
- '#dma-cells'
additionalProperties: false
examples:
- |
// In the example below, "interrupts = <0 68 4>, <0 68 4>, ..." is not a
// typo. The first two channels share a single interrupt line.
dmac: dma-controller@5a000000 {
compatible = "socionext,uniphier-mio-dmac";
reg = <0x5a000000 0x1000>;
interrupts = <0 68 4>, <0 68 4>, <0 69 4>, <0 70 4>,
<0 71 4>, <0 72 4>, <0 73 4>, <0 74 4>;
clocks = <&mio_clk 7>;
resets = <&mio_rst 7>;
#dma-cells = <1>;
};