| [ |
| { |
| "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)", |
| "EventCode": "0x12", |
| "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", |
| "SampleAfterValue": "100003", |
| "UMask": "0xe", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)", |
| "EventCode": "0x13", |
| "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", |
| "SampleAfterValue": "100003", |
| "UMask": "0xe", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.", |
| "EventCode": "0x85", |
| "EventName": "ITLB_MISSES.WALK_COMPLETED", |
| "SampleAfterValue": "200003", |
| "UMask": "0xe", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)", |
| "EventCode": "0x11", |
| "EventName": "ITLB_MISSES.WALK_COMPLETED", |
| "SampleAfterValue": "100003", |
| "UMask": "0xe", |
| "Unit": "cpu_core" |
| } |
| ] |
