| [ |
| { |
| "BriefDescription": "Counts the total number of branch instructions retired for all branch types.", |
| "EventCode": "0xc4", |
| "EventName": "BR_INST_RETIRED.ALL_BRANCHES", |
| "PEBS": "1", |
| "SampleAfterValue": "200003", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "All branch instructions retired.", |
| "EventCode": "0xc4", |
| "EventName": "BR_INST_RETIRED.ALL_BRANCHES", |
| "PEBS": "1", |
| "SampleAfterValue": "400009", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.", |
| "EventCode": "0xc5", |
| "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", |
| "PEBS": "1", |
| "SampleAfterValue": "200003", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "All mispredicted branch instructions retired.", |
| "EventCode": "0xc5", |
| "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", |
| "PEBS": "1", |
| "SampleAfterValue": "400009", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", |
| "EventName": "CPU_CLK_UNHALTED.CORE", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x2", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Counts the number of unhalted core clock cycles[This event is alias to CPU_CLK_UNHALTED.THREAD_P]", |
| "EventCode": "0x3c", |
| "EventName": "CPU_CLK_UNHALTED.CORE_P", |
| "SampleAfterValue": "2000003", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles", |
| "EventName": "CPU_CLK_UNHALTED.REF_TSC", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x3", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Reference cycles when the core is not in halt state.", |
| "EventName": "CPU_CLK_UNHALTED.REF_TSC", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x3", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Reference cycles when the core is not in halt state.", |
| "EventCode": "0x3c", |
| "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", |
| "EventName": "CPU_CLK_UNHALTED.THREAD", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x2", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Core cycles when the thread is not in halt state", |
| "EventName": "CPU_CLK_UNHALTED.THREAD", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x2", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Counts the number of unhalted core clock cycles[This event is alias to CPU_CLK_UNHALTED.CORE_P]", |
| "EventCode": "0x3c", |
| "EventName": "CPU_CLK_UNHALTED.THREAD_P", |
| "SampleAfterValue": "2000003", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Thread cycles when thread is not in halt state", |
| "EventCode": "0x3c", |
| "EventName": "CPU_CLK_UNHALTED.THREAD_P", |
| "SampleAfterValue": "2000003", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Fixed Counter: Counts the number of instructions retired", |
| "EventName": "INST_RETIRED.ANY", |
| "PEBS": "1", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x1", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event", |
| "EventName": "INST_RETIRED.ANY", |
| "PEBS": "1", |
| "SampleAfterValue": "2000003", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Counts the number of instructions retired", |
| "EventCode": "0xc0", |
| "EventName": "INST_RETIRED.ANY_P", |
| "PEBS": "1", |
| "SampleAfterValue": "2000003", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Number of instructions retired. General Counter - architectural event", |
| "EventCode": "0xc0", |
| "EventName": "INST_RETIRED.ANY_P", |
| "PEBS": "1", |
| "SampleAfterValue": "2000003", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.", |
| "EventCode": "0x03", |
| "EventName": "LD_BLOCKS.STORE_FORWARD", |
| "SampleAfterValue": "100003", |
| "UMask": "0x82", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event", |
| "EventName": "TOPDOWN.SLOTS", |
| "SampleAfterValue": "10000003", |
| "UMask": "0x4", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event", |
| "EventCode": "0xa4", |
| "EventName": "TOPDOWN.SLOTS_P", |
| "SampleAfterValue": "10000003", |
| "UMask": "0x1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.", |
| "EventCode": "0x73", |
| "EventName": "TOPDOWN_BAD_SPECULATION.ALL", |
| "SampleAfterValue": "1000003", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Counts the number of retirement slots not consumed due to backend stalls", |
| "EventCode": "0x74", |
| "EventName": "TOPDOWN_BE_BOUND.ALL", |
| "SampleAfterValue": "1000003", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Counts the number of retirement slots not consumed due to front end stalls", |
| "EventCode": "0x71", |
| "EventName": "TOPDOWN_FE_BOUND.ALL", |
| "SampleAfterValue": "1000003", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Counts the number of consumed retirement slots. Similar to UOPS_RETIRED.ALL", |
| "EventCode": "0x72", |
| "EventName": "TOPDOWN_RETIRING.ALL", |
| "PEBS": "1", |
| "SampleAfterValue": "1000003", |
| "Unit": "cpu_atom" |
| } |
| ] |
