| [ |
| { |
| "BriefDescription": "L2 code requests", |
| "EventCode": "0x24", |
| "EventName": "L2_RQSTS.ALL_CODE_RD", |
| "SampleAfterValue": "200003", |
| "UMask": "0xe4", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Demand Data Read access L2 cache", |
| "EventCode": "0x24", |
| "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", |
| "SampleAfterValue": "200003", |
| "UMask": "0xe1", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.", |
| "EventCode": "0x2e", |
| "EventName": "LONGEST_LAT_CACHE.MISS", |
| "SampleAfterValue": "200003", |
| "UMask": "0x41", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)", |
| "EventCode": "0x2e", |
| "EventName": "LONGEST_LAT_CACHE.MISS", |
| "SampleAfterValue": "100003", |
| "UMask": "0x41", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.", |
| "EventCode": "0x2e", |
| "EventName": "LONGEST_LAT_CACHE.REFERENCE", |
| "SampleAfterValue": "200003", |
| "UMask": "0x4f", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)", |
| "EventCode": "0x2e", |
| "EventName": "LONGEST_LAT_CACHE.REFERENCE", |
| "SampleAfterValue": "100003", |
| "UMask": "0x4f", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Retired load instructions.", |
| "Data_LA": "1", |
| "EventCode": "0xd0", |
| "EventName": "MEM_INST_RETIRED.ALL_LOADS", |
| "PEBS": "1", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x81", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Retired store instructions.", |
| "Data_LA": "1", |
| "EventCode": "0xd0", |
| "EventName": "MEM_INST_RETIRED.ALL_STORES", |
| "PEBS": "1", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x82", |
| "Unit": "cpu_core" |
| }, |
| { |
| "BriefDescription": "Counts the number of load ops retired.", |
| "Data_LA": "1", |
| "EventCode": "0xd0", |
| "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", |
| "PEBS": "1", |
| "SampleAfterValue": "200003", |
| "UMask": "0x81", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Counts the number of store ops retired.", |
| "Data_LA": "1", |
| "EventCode": "0xd0", |
| "EventName": "MEM_UOPS_RETIRED.ALL_STORES", |
| "PEBS": "1", |
| "SampleAfterValue": "200003", |
| "UMask": "0x82", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", |
| "Data_LA": "1", |
| "EventCode": "0xd0", |
| "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x80", |
| "PEBS": "2", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x5", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", |
| "Data_LA": "1", |
| "EventCode": "0xd0", |
| "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x10", |
| "PEBS": "2", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x5", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", |
| "Data_LA": "1", |
| "EventCode": "0xd0", |
| "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x100", |
| "PEBS": "2", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x5", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", |
| "Data_LA": "1", |
| "EventCode": "0xd0", |
| "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x20", |
| "PEBS": "2", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x5", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", |
| "Data_LA": "1", |
| "EventCode": "0xd0", |
| "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x4", |
| "PEBS": "2", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x5", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", |
| "Data_LA": "1", |
| "EventCode": "0xd0", |
| "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x200", |
| "PEBS": "2", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x5", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", |
| "Data_LA": "1", |
| "EventCode": "0xd0", |
| "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x40", |
| "PEBS": "2", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x5", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled.", |
| "Data_LA": "1", |
| "EventCode": "0xd0", |
| "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8", |
| "MSRIndex": "0x3F6", |
| "MSRValue": "0x8", |
| "PEBS": "2", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x5", |
| "Unit": "cpu_atom" |
| }, |
| { |
| "BriefDescription": "Counts the number of stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES", |
| "Data_LA": "1", |
| "EventCode": "0xd0", |
| "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY", |
| "PEBS": "2", |
| "SampleAfterValue": "1000003", |
| "UMask": "0x6", |
| "Unit": "cpu_atom" |
| } |
| ] |
