| [ |
| { |
| "ArchStdEvent": "SW_INCR" |
| }, |
| { |
| "ArchStdEvent": "INST_RETIRED" |
| }, |
| { |
| "ArchStdEvent": "EXC_RETURN" |
| }, |
| { |
| "ArchStdEvent": "CID_WRITE_RETIRED" |
| }, |
| { |
| "ArchStdEvent": "PC_WRITE_RETIRED" |
| }, |
| { |
| "ArchStdEvent": "BR_IMMED_RETIRED" |
| }, |
| { |
| "ArchStdEvent": "BR_RETURN_RETIRED" |
| }, |
| { |
| "ArchStdEvent": "INST_SPEC" |
| }, |
| { |
| "ArchStdEvent": "TTBR_WRITE_RETIRED" |
| }, |
| { |
| "ArchStdEvent": "BR_RETIRED" |
| }, |
| { |
| "ArchStdEvent": "LDREX_SPEC" |
| }, |
| { |
| "ArchStdEvent": "STREX_PASS_SPEC" |
| }, |
| { |
| "ArchStdEvent": "STREX_FAIL_SPEC" |
| }, |
| { |
| "ArchStdEvent": "STREX_SPEC" |
| }, |
| { |
| "ArchStdEvent": "LD_SPEC" |
| }, |
| { |
| "ArchStdEvent": "ST_SPEC" |
| }, |
| { |
| "ArchStdEvent": "LDST_SPEC" |
| }, |
| { |
| "ArchStdEvent": "DP_SPEC" |
| }, |
| { |
| "ArchStdEvent": "ASE_SPEC" |
| }, |
| { |
| "ArchStdEvent": "VFP_SPEC" |
| }, |
| { |
| "ArchStdEvent": "CRYPTO_SPEC" |
| }, |
| { |
| "ArchStdEvent": "ISB_SPEC" |
| }, |
| { |
| "ArchStdEvent": "DSB_SPEC" |
| }, |
| { |
| "ArchStdEvent": "DMB_SPEC" |
| } |
| ] |
