| [ |
| { |
| "ArchStdEvent": "LD_RETIRED" |
| }, |
| { |
| "ArchStdEvent": "ST_RETIRED" |
| }, |
| { |
| "ArchStdEvent": "INST_RETIRED" |
| }, |
| { |
| "ArchStdEvent": "EXC_RETURN" |
| }, |
| { |
| "ArchStdEvent": "CID_WRITE_RETIRED" |
| }, |
| { |
| "ArchStdEvent": "PC_WRITE_RETIRED" |
| }, |
| { |
| "ArchStdEvent": "BR_IMMED_RETIRED" |
| }, |
| { |
| "ArchStdEvent": "BR_RETURN_RETIRED" |
| }, |
| { |
| "ArchStdEvent": "INST_SPEC" |
| }, |
| { |
| "ArchStdEvent": "TTBR_WRITE_RETIRED" |
| }, |
| { |
| "ArchStdEvent": "BR_RETIRED" |
| }, |
| { |
| "ArchStdEvent": "BR_MIS_PRED_RETIRED" |
| }, |
| { |
| "ArchStdEvent": "OP_RETIRED" |
| }, |
| { |
| "ArchStdEvent": "OP_SPEC" |
| }, |
| { |
| "ArchStdEvent": "LD_SPEC" |
| }, |
| { |
| "ArchStdEvent": "ST_SPEC" |
| }, |
| { |
| "ArchStdEvent": "LDST_SPEC" |
| }, |
| { |
| "ArchStdEvent": "DP_SPEC" |
| }, |
| { |
| "ArchStdEvent": "ASE_SPEC" |
| }, |
| { |
| "ArchStdEvent": "VFP_SPEC" |
| }, |
| { |
| "ArchStdEvent": "PC_WRITE_SPEC" |
| }, |
| { |
| "ArchStdEvent": "CRYPTO_SPEC" |
| }, |
| { |
| "ArchStdEvent": "SVE_INST_RETIRED" |
| }, |
| { |
| "ArchStdEvent": "SVE_INST_SPEC" |
| }, |
| { |
| "ArchStdEvent": "FP_HP_SPEC" |
| }, |
| { |
| "ArchStdEvent": "FP_SP_SPEC" |
| }, |
| { |
| "ArchStdEvent": "FP_DP_SPEC" |
| }, |
| { |
| "ArchStdEvent": "ASE_SVE_INT8_SPEC" |
| }, |
| { |
| "ArchStdEvent": "ASE_SVE_INT16_SPEC" |
| }, |
| { |
| "ArchStdEvent": "ASE_SVE_INT32_SPEC" |
| }, |
| { |
| "ArchStdEvent": "ASE_SVE_INT64_SPEC" |
| } |
| ] |
