| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Device Tree Source for AM62A SoC Family Main Domain peripherals |
| * |
| * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ |
| */ |
| |
| &cbass_main { |
| oc_sram: sram@70000000 { |
| compatible = "mmio-sram"; |
| reg = <0x00 0x70000000 0x00 0x10000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x00 0x70000000 0x10000>; |
| }; |
| |
| gic500: interrupt-controller@1800000 { |
| compatible = "arm,gic-v3"; |
| reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ |
| <0x00 0x01880000 0x00 0xc0000>, /* GICR */ |
| <0x00 0x01880000 0x00 0xc0000>, /* GICR */ |
| <0x01 0x00000000 0x00 0x2000>, /* GICC */ |
| <0x01 0x00010000 0x00 0x1000>, /* GICH */ |
| <0x01 0x00020000 0x00 0x2000>; /* GICV */ |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| /* |
| * vcpumntirq: |
| * virtual CPU interface maintenance interrupt |
| */ |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| |
| gic_its: msi-controller@1820000 { |
| compatible = "arm,gic-v3-its"; |
| reg = <0x00 0x01820000 0x00 0x10000>; |
| socionext,synquacer-pre-its = <0x1000000 0x400000>; |
| msi-controller; |
| #msi-cells = <1>; |
| }; |
| }; |
| |
| main_conf: syscon@100000 { |
| compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; |
| reg = <0x00 0x00100000 0x00 0x20000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x00 0x00 0x00100000 0x20000>; |
| }; |
| |
| dmss: bus@48000000 { |
| compatible = "simple-bus"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| dma-ranges; |
| ranges = <0x00 0x48000000 0x00 0x48000000 0x00 0x06000000>; |
| |
| ti,sci-dev-id = <25>; |
| |
| secure_proxy_main: mailbox@4d000000 { |
| compatible = "ti,am654-secure-proxy"; |
| reg = <0x00 0x4d000000 0x00 0x80000>, |
| <0x00 0x4a600000 0x00 0x80000>, |
| <0x00 0x4a400000 0x00 0x80000>; |
| reg-names = "target_data", "rt", "scfg"; |
| #mbox-cells = <1>; |
| interrupt-names = "rx_012"; |
| interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| }; |
| |
| dmsc: system-controller@44043000 { |
| compatible = "ti,k2g-sci"; |
| reg = <0x00 0x44043000 0x00 0xfe0>; |
| reg-names = "debug_messages"; |
| ti,host-id = <12>; |
| mbox-names = "rx", "tx"; |
| mboxes= <&secure_proxy_main 12>, |
| <&secure_proxy_main 13>; |
| |
| k3_pds: power-controller { |
| compatible = "ti,sci-pm-domain"; |
| #power-domain-cells = <2>; |
| }; |
| |
| k3_clks: clock-controller { |
| compatible = "ti,k2g-sci-clk"; |
| #clock-cells = <2>; |
| }; |
| |
| k3_reset: reset-controller { |
| compatible = "ti,sci-reset"; |
| #reset-cells = <2>; |
| }; |
| }; |
| |
| main_pmx0: pinctrl@f4000 { |
| compatible = "pinctrl-single"; |
| reg = <0x00 0xf4000 0x00 0x2ac>; |
| #pinctrl-cells = <1>; |
| pinctrl-single,register-width = <32>; |
| pinctrl-single,function-mask = <0xffffffff>; |
| }; |
| |
| main_uart0: serial@2800000 { |
| compatible = "ti,am64-uart", "ti,am654-uart"; |
| reg = <0x00 0x02800000 0x00 0x100>; |
| interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 146 0>; |
| clock-names = "fclk"; |
| status = "disabled"; |
| }; |
| |
| main_uart1: serial@2810000 { |
| compatible = "ti,am64-uart", "ti,am654-uart"; |
| reg = <0x00 0x02810000 0x00 0x100>; |
| interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 152 0>; |
| clock-names = "fclk"; |
| status = "disabled"; |
| }; |
| |
| main_uart2: serial@2820000 { |
| compatible = "ti,am64-uart", "ti,am654-uart"; |
| reg = <0x00 0x02820000 0x00 0x100>; |
| interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 153 0>; |
| clock-names = "fclk"; |
| status = "disabled"; |
| }; |
| |
| main_uart3: serial@2830000 { |
| compatible = "ti,am64-uart", "ti,am654-uart"; |
| reg = <0x00 0x02830000 0x00 0x100>; |
| interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 154 0>; |
| clock-names = "fclk"; |
| status = "disabled"; |
| }; |
| |
| main_uart4: serial@2840000 { |
| compatible = "ti,am64-uart", "ti,am654-uart"; |
| reg = <0x00 0x02840000 0x00 0x100>; |
| interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&k3_pds 155 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 155 0>; |
| clock-names = "fclk"; |
| status = "disabled"; |
| }; |
| |
| main_uart5: serial@2850000 { |
| compatible = "ti,am64-uart", "ti,am654-uart"; |
| reg = <0x00 0x02850000 0x00 0x100>; |
| interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 156 0>; |
| clock-names = "fclk"; |
| status = "disabled"; |
| }; |
| |
| main_uart6: serial@2860000 { |
| compatible = "ti,am64-uart", "ti,am654-uart"; |
| reg = <0x00 0x02860000 0x00 0x100>; |
| interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 158 0>; |
| clock-names = "fclk"; |
| status = "disabled"; |
| }; |
| |
| main_i2c0: i2c@20000000 { |
| compatible = "ti,am64-i2c", "ti,omap4-i2c"; |
| reg = <0x00 0x20000000 0x00 0x100>; |
| interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 102 2>; |
| clock-names = "fck"; |
| status = "disabled"; |
| }; |
| |
| main_i2c1: i2c@20010000 { |
| compatible = "ti,am64-i2c", "ti,omap4-i2c"; |
| reg = <0x00 0x20010000 0x00 0x100>; |
| interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 103 2>; |
| clock-names = "fck"; |
| status = "disabled"; |
| }; |
| |
| main_i2c2: i2c@20020000 { |
| compatible = "ti,am64-i2c", "ti,omap4-i2c"; |
| reg = <0x00 0x20020000 0x00 0x100>; |
| interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 104 2>; |
| clock-names = "fck"; |
| status = "disabled"; |
| }; |
| |
| main_i2c3: i2c@20030000 { |
| compatible = "ti,am64-i2c", "ti,omap4-i2c"; |
| reg = <0x00 0x20030000 0x00 0x100>; |
| interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 105 2>; |
| clock-names = "fck"; |
| status = "disabled"; |
| }; |
| |
| main_gpio_intr: interrupt-controller@a00000 { |
| compatible = "ti,sci-intr"; |
| reg = <0x00 0x00a00000 0x00 0x800>; |
| ti,intr-trigger-type = <1>; |
| interrupt-controller; |
| interrupt-parent = <&gic500>; |
| #interrupt-cells = <1>; |
| ti,sci = <&dmsc>; |
| ti,sci-dev-id = <3>; |
| ti,interrupt-ranges = <0 32 16>; |
| status = "disabled"; |
| }; |
| |
| main_gpio0: gpio@600000 { |
| compatible = "ti,am64-gpio", "ti,keystone-gpio"; |
| reg = <0x00 0x00600000 0x0 0x100>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-parent = <&main_gpio_intr>; |
| interrupts = <190>, <191>, <192>, |
| <193>, <194>, <195>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| ti,ngpio = <87>; |
| ti,davinci-gpio-unbanked = <0>; |
| power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 77 0>; |
| clock-names = "gpio"; |
| status = "disabled"; |
| }; |
| |
| main_gpio1: gpio@601000 { |
| compatible = "ti,am64-gpio", "ti,keystone-gpio"; |
| reg = <0x00 0x00601000 0x0 0x100>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-parent = <&main_gpio_intr>; |
| interrupts = <180>, <181>, <182>, |
| <183>, <184>, <185>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| ti,ngpio = <88>; |
| ti,davinci-gpio-unbanked = <0>; |
| power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 78 0>; |
| clock-names = "gpio"; |
| status = "disabled"; |
| }; |
| |
| sdhci1: mmc@fa00000 { |
| compatible = "ti,am62-sdhci"; |
| reg = <0x00 0xfa00000 0x00 0x260>, <0x00 0xfa08000 0x00 0x134>; |
| interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&k3_pds 58 TI_SCI_PD_EXCLUSIVE>; |
| clocks = <&k3_clks 58 5>, <&k3_clks 58 6>; |
| clock-names = "clk_ahb", "clk_xin"; |
| ti,trm-icp = <0x2>; |
| ti,otap-del-sel-legacy = <0x0>; |
| ti,otap-del-sel-sd-hs = <0x0>; |
| ti,otap-del-sel-sdr12 = <0xf>; |
| ti,otap-del-sel-sdr25 = <0xf>; |
| ti,otap-del-sel-sdr50 = <0xc>; |
| ti,otap-del-sel-sdr104 = <0x6>; |
| ti,otap-del-sel-ddr50 = <0x9>; |
| ti,itap-del-sel-legacy = <0x0>; |
| ti,itap-del-sel-sd-hs = <0x0>; |
| ti,itap-del-sel-sdr12 = <0x0>; |
| ti,itap-del-sel-sdr25 = <0x0>; |
| ti,clkbuf-sel = <0x7>; |
| bus-width = <4>; |
| no-1-8-v; |
| status = "disabled"; |
| }; |
| }; |
