arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi

// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
 * Device Tree Source for the RZ/G2LC SMARC EVK parts
 *
 * Copyright (C) 2022 Renesas Electronics Corp.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>

#include "rzg2lc-smarc-pinfunction.dtsi"
#include "rz-smarc-common.dtsi"


/ {
	aliases {
		serial1 = &scif1;
		i2c2 = &i2c2;
	};
};

#if (SW_SCIF_CAN || SW_RSPI_CAN)
&canfd {
	pinctrl-0 = <&can1_pins>;
	/delete-node/ channel@0;
};
#else
&canfd {
	/delete-property/ pinctrl-0;
	/delete-property/ pinctrl-names;
	status = "disabled";
};
#endif

&cpu_dai {
	sound-dai = <&ssi0>;
};

&i2c2 {
	pinctrl-0 = <&i2c2_pins>;
	pinctrl-names = "default";
	clock-frequency = <400000>;

	status = "okay";

	wm8978: codec@1a {
		compatible = "wlf,wm8978";
		#sound-dai-cells = <0>;
		reg = <0x1a>;
	};
};

/*
 * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board
 * SW1 should be at position 2->3 so that SER0_CTS# line is activated
 * SW2 should be at position 2->3 so that SER0_TX line is activated
 * SW3 should be at position 2->3 so that SER0_RX line is activated
 * SW4 should be at position 2->3 so that SER0_RTS# line is activated
 */
#if (!SW_SCIF_CAN && PMOD1_SER0)
&scif1 {
	pinctrl-0 = <&scif1_pins>;
	pinctrl-names = "default";

	uart-has-rtscts;
	status = "okay";
};
#endif

&ssi0 {
	pinctrl-0 = <&ssi0_pins>;
	pinctrl-names = "default";

	status = "okay";
};

#if (SW_RSPI_CAN)
&spi1 {
	/delete-property/ pinctrl-0;
	/delete-property/ pinctrl-names;
	status = "disabled";
};
#endif

&vccq_sdhi1 {
	gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
};