| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * SDM845 SoC device tree source |
| * |
| * Copyright (c) 2018, The Linux Foundation. All rights reserved. |
| */ |
| |
| #include <dt-bindings/clock/qcom,dispcc-sdm845.h> |
| #include <dt-bindings/clock/qcom,gcc-sdm845.h> |
| #include <dt-bindings/clock/qcom,gpucc-sdm845.h> |
| #include <dt-bindings/clock/qcom,lpass-sdm845.h> |
| #include <dt-bindings/clock/qcom,rpmh.h> |
| #include <dt-bindings/clock/qcom,videocc-sdm845.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/phy/phy-qcom-qusb2.h> |
| #include <dt-bindings/reset/qcom,sdm845-aoss.h> |
| #include <dt-bindings/reset/qcom,sdm845-pdc.h> |
| #include <dt-bindings/soc/qcom,rpmh-rsc.h> |
| #include <dt-bindings/clock/qcom,gcc-sdm845.h> |
| #include <dt-bindings/thermal/thermal.h> |
| |
| / { |
| interrupt-parent = <&intc>; |
| |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| aliases { |
| i2c0 = &i2c0; |
| i2c1 = &i2c1; |
| i2c2 = &i2c2; |
| i2c3 = &i2c3; |
| i2c4 = &i2c4; |
| i2c5 = &i2c5; |
| i2c6 = &i2c6; |
| i2c7 = &i2c7; |
| i2c8 = &i2c8; |
| i2c9 = &i2c9; |
| i2c10 = &i2c10; |
| i2c11 = &i2c11; |
| i2c12 = &i2c12; |
| i2c13 = &i2c13; |
| i2c14 = &i2c14; |
| i2c15 = &i2c15; |
| spi0 = &spi0; |
| spi1 = &spi1; |
| spi2 = &spi2; |
| spi3 = &spi3; |
| spi4 = &spi4; |
| spi5 = &spi5; |
| spi6 = &spi6; |
| spi7 = &spi7; |
| spi8 = &spi8; |
| spi9 = &spi9; |
| spi10 = &spi10; |
| spi11 = &spi11; |
| spi12 = &spi12; |
| spi13 = &spi13; |
| spi14 = &spi14; |
| spi15 = &spi15; |
| }; |
| |
| chosen { }; |
| |
| memory@80000000 { |
| device_type = "memory"; |
| /* We expect the bootloader to fill in the size */ |
| reg = <0 0x80000000 0 0>; |
| }; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| memory@85fc0000 { |
| reg = <0 0x85fc0000 0 0x20000>; |
| no-map; |
| }; |
| |
| memory@85fe0000 { |
| compatible = "qcom,cmd-db"; |
| reg = <0x0 0x85fe0000 0x0 0x20000>; |
| no-map; |
| }; |
| |
| smem_mem: memory@86000000 { |
| reg = <0x0 0x86000000 0x0 0x200000>; |
| no-map; |
| }; |
| |
| memory@86200000 { |
| reg = <0 0x86200000 0 0x2d00000>; |
| no-map; |
| }; |
| |
| wlan_msa_mem: memory@96700000 { |
| reg = <0 0x96700000 0 0x100000>; |
| no-map; |
| }; |
| |
| mpss_region: memory@8e000000 { |
| reg = <0 0x8e000000 0 0x7800000>; |
| no-map; |
| }; |
| |
| mba_region: memory@96500000 { |
| reg = <0 0x96500000 0 0x200000>; |
| no-map; |
| }; |
| }; |
| |
| cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| CPU0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo385"; |
| reg = <0x0 0x0>; |
| enable-method = "psci"; |
| qcom,freq-domain = <&cpufreq_hw 0>; |
| #cooling-cells = <2>; |
| next-level-cache = <&L2_0>; |
| L2_0: l2-cache { |
| compatible = "cache"; |
| next-level-cache = <&L3_0>; |
| L3_0: l3-cache { |
| compatible = "cache"; |
| }; |
| }; |
| }; |
| |
| CPU1: cpu@100 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo385"; |
| reg = <0x0 0x100>; |
| enable-method = "psci"; |
| qcom,freq-domain = <&cpufreq_hw 0>; |
| #cooling-cells = <2>; |
| next-level-cache = <&L2_100>; |
| L2_100: l2-cache { |
| compatible = "cache"; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU2: cpu@200 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo385"; |
| reg = <0x0 0x200>; |
| enable-method = "psci"; |
| qcom,freq-domain = <&cpufreq_hw 0>; |
| #cooling-cells = <2>; |
| next-level-cache = <&L2_200>; |
| L2_200: l2-cache { |
| compatible = "cache"; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU3: cpu@300 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo385"; |
| reg = <0x0 0x300>; |
| enable-method = "psci"; |
| qcom,freq-domain = <&cpufreq_hw 0>; |
| #cooling-cells = <2>; |
| next-level-cache = <&L2_300>; |
| L2_300: l2-cache { |
| compatible = "cache"; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU4: cpu@400 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo385"; |
| reg = <0x0 0x400>; |
| enable-method = "psci"; |
| qcom,freq-domain = <&cpufreq_hw 1>; |
| #cooling-cells = <2>; |
| next-level-cache = <&L2_400>; |
| L2_400: l2-cache { |
| compatible = "cache"; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU5: cpu@500 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo385"; |
| reg = <0x0 0x500>; |
| enable-method = "psci"; |
| qcom,freq-domain = <&cpufreq_hw 1>; |
| #cooling-cells = <2>; |
| next-level-cache = <&L2_500>; |
| L2_500: l2-cache { |
| compatible = "cache"; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU6: cpu@600 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo385"; |
| reg = <0x0 0x600>; |
| enable-method = "psci"; |
| qcom,freq-domain = <&cpufreq_hw 1>; |
| #cooling-cells = <2>; |
| next-level-cache = <&L2_600>; |
| L2_600: l2-cache { |
| compatible = "cache"; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU7: cpu@700 { |
| device_type = "cpu"; |
| compatible = "qcom,kryo385"; |
| reg = <0x0 0x700>; |
| enable-method = "psci"; |
| qcom,freq-domain = <&cpufreq_hw 1>; |
| #cooling-cells = <2>; |
| next-level-cache = <&L2_700>; |
| L2_700: l2-cache { |
| compatible = "cache"; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| }; |
| |
| pmu { |
| compatible = "arm,armv8-pmuv3"; |
| interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, |
| <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; |
| }; |
| |
| clocks { |
| xo_board: xo-board { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <38400000>; |
| clock-output-names = "xo_board"; |
| }; |
| |
| sleep_clk: sleep-clk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <32764>; |
| }; |
| }; |
| |
| firmware { |
| scm { |
| compatible = "qcom,scm-sdm845", "qcom,scm"; |
| }; |
| }; |
| |
| tcsr_mutex: hwlock { |
| compatible = "qcom,tcsr-mutex"; |
| syscon = <&tcsr_mutex_regs 0 0x1000>; |
| #hwlock-cells = <1>; |
| }; |
| |
| smem { |
| compatible = "qcom,smem"; |
| memory-region = <&smem_mem>; |
| hwlocks = <&tcsr_mutex 3>; |
| }; |
| |
| smp2p-cdsp { |
| compatible = "qcom,smp2p"; |
| qcom,smem = <94>, <432>; |
| |
| interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; |
| |
| mboxes = <&apss_shared 6>; |
| |
| qcom,local-pid = <0>; |
| qcom,remote-pid = <5>; |
| |
| cdsp_smp2p_out: master-kernel { |
| qcom,entry-name = "master-kernel"; |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| cdsp_smp2p_in: slave-kernel { |
| qcom,entry-name = "slave-kernel"; |
| |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| }; |
| |
| smp2p-lpass { |
| compatible = "qcom,smp2p"; |
| qcom,smem = <443>, <429>; |
| |
| interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; |
| |
| mboxes = <&apss_shared 10>; |
| |
| qcom,local-pid = <0>; |
| qcom,remote-pid = <2>; |
| |
| adsp_smp2p_out: master-kernel { |
| qcom,entry-name = "master-kernel"; |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| adsp_smp2p_in: slave-kernel { |
| qcom,entry-name = "slave-kernel"; |
| |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| }; |
| |
| smp2p-mpss { |
| compatible = "qcom,smp2p"; |
| qcom,smem = <435>, <428>; |
| interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; |
| mboxes = <&apss_shared 14>; |
| qcom,local-pid = <0>; |
| qcom,remote-pid = <1>; |
| |
| modem_smp2p_out: master-kernel { |
| qcom,entry-name = "master-kernel"; |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| modem_smp2p_in: slave-kernel { |
| qcom,entry-name = "slave-kernel"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| }; |
| |
| smp2p-slpi { |
| compatible = "qcom,smp2p"; |
| qcom,smem = <481>, <430>; |
| interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; |
| mboxes = <&apss_shared 26>; |
| qcom,local-pid = <0>; |
| qcom,remote-pid = <3>; |
| |
| slpi_smp2p_out: master-kernel { |
| qcom,entry-name = "master-kernel"; |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| slpi_smp2p_in: slave-kernel { |
| qcom,entry-name = "slave-kernel"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| }; |
| |
| soc: soc { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0 0 0 0 0x10 0>; |
| dma-ranges = <0 0 0 0 0x10 0>; |
| compatible = "simple-bus"; |
| |
| gcc: clock-controller@100000 { |
| compatible = "qcom,gcc-sdm845"; |
| reg = <0 0x00100000 0 0x1f0000>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| #power-domain-cells = <1>; |
| }; |
| |
| qfprom@784000 { |
| compatible = "qcom,qfprom"; |
| reg = <0 0x00784000 0 0x8ff>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| qusb2p_hstx_trim: hstx-trim-primary@1eb { |
| reg = <0x1eb 0x1>; |
| bits = <1 4>; |
| }; |
| |
| qusb2s_hstx_trim: hstx-trim-secondary@1eb { |
| reg = <0x1eb 0x2>; |
| bits = <6 4>; |
| }; |
| }; |
| |
| rng: rng@793000 { |
| compatible = "qcom,prng-ee"; |
| reg = <0 0x00793000 0 0x1000>; |
| clocks = <&gcc GCC_PRNG_AHB_CLK>; |
| clock-names = "core"; |
| }; |
| |
| qupv3_id_0: geniqup@8c0000 { |
| compatible = "qcom,geni-se-qup"; |
| reg = <0 0x008c0000 0 0x6000>; |
| clock-names = "m-ahb", "s-ahb"; |
| clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| status = "disabled"; |
| |
| i2c0: i2c@880000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00880000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c0_default>; |
| interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi0: spi@880000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00880000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_spi0_default>; |
| interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart0: serial@880000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0 0x00880000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart0_default>; |
| interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@884000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00884000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c1_default>; |
| interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi1: spi@884000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00884000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_spi1_default>; |
| interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart1: serial@884000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0 0x00884000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart1_default>; |
| interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@888000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00888000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c2_default>; |
| interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi2: spi@888000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00888000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_spi2_default>; |
| interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart2: serial@888000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0 0x00888000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart2_default>; |
| interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@88c000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x0088c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c3_default>; |
| interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi3: spi@88c000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x0088c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_spi3_default>; |
| interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart3: serial@88c000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0 0x0088c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart3_default>; |
| interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@890000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00890000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c4_default>; |
| interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi4: spi@890000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00890000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_spi4_default>; |
| interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart4: serial@890000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0 0x00890000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart4_default>; |
| interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| i2c5: i2c@894000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00894000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c5_default>; |
| interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi5: spi@894000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00894000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_spi5_default>; |
| interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart5: serial@894000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0 0x00894000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart5_default>; |
| interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| i2c6: i2c@898000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00898000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c6_default>; |
| interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi6: spi@898000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00898000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_spi6_default>; |
| interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart6: serial@898000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0 0x00898000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart6_default>; |
| interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| i2c7: i2c@89c000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x0089c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c7_default>; |
| interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi7: spi@89c000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x0089c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_spi7_default>; |
| interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart7: serial@89c000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0 0x0089c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart7_default>; |
| interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| }; |
| |
| qupv3_id_1: geniqup@ac0000 { |
| compatible = "qcom,geni-se-qup"; |
| reg = <0 0x00ac0000 0 0x6000>; |
| clock-names = "m-ahb", "s-ahb"; |
| clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| status = "disabled"; |
| |
| i2c8: i2c@a80000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a80000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c8_default>; |
| interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi8: spi@a80000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00a80000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_spi8_default>; |
| interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart8: serial@a80000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0 0x00a80000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart8_default>; |
| interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| i2c9: i2c@a84000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a84000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c9_default>; |
| interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi9: spi@a84000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00a84000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_spi9_default>; |
| interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart9: serial@a84000 { |
| compatible = "qcom,geni-debug-uart"; |
| reg = <0 0x00a84000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart9_default>; |
| interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| i2c10: i2c@a88000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a88000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c10_default>; |
| interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi10: spi@a88000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00a88000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_spi10_default>; |
| interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart10: serial@a88000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0 0x00a88000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart10_default>; |
| interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| i2c11: i2c@a8c000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a8c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c11_default>; |
| interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi11: spi@a8c000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00a8c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_spi11_default>; |
| interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart11: serial@a8c000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0 0x00a8c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart11_default>; |
| interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| i2c12: i2c@a90000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a90000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c12_default>; |
| interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi12: spi@a90000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00a90000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_spi12_default>; |
| interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart12: serial@a90000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0 0x00a90000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart12_default>; |
| interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| i2c13: i2c@a94000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a94000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c13_default>; |
| interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi13: spi@a94000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00a94000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_spi13_default>; |
| interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart13: serial@a94000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0 0x00a94000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart13_default>; |
| interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| i2c14: i2c@a98000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a98000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c14_default>; |
| interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi14: spi@a98000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00a98000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_spi14_default>; |
| interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart14: serial@a98000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0 0x00a98000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart14_default>; |
| interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| i2c15: i2c@a9c000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a9c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_i2c15_default>; |
| interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| spi15: spi@a9c000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00a9c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_spi15_default>; |
| interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| uart15: serial@a9c000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0 0x00a9c000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&qup_uart15_default>; |
| interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| }; |
| |
| ufs_mem_hc: ufshc@1d84000 { |
| compatible = "qcom,sdm845-ufshc", "qcom,ufshc", |
| "jedec,ufs-2.0"; |
| reg = <0 0x01d84000 0 0x2500>; |
| interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; |
| phys = <&ufs_mem_phy_lanes>; |
| phy-names = "ufsphy"; |
| lanes-per-direction = <2>; |
| power-domains = <&gcc UFS_PHY_GDSC>; |
| |
| iommus = <&apps_smmu 0x100 0xf>; |
| |
| clock-names = |
| "core_clk", |
| "bus_aggr_clk", |
| "iface_clk", |
| "core_clk_unipro", |
| "ref_clk", |
| "tx_lane0_sync_clk", |
| "rx_lane0_sync_clk", |
| "rx_lane1_sync_clk"; |
| clocks = |
| <&gcc GCC_UFS_PHY_AXI_CLK>, |
| <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, |
| <&gcc GCC_UFS_PHY_AHB_CLK>, |
| <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, |
| <&rpmhcc RPMH_CXO_CLK>, |
| <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, |
| <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, |
| <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; |
| freq-table-hz = |
| <50000000 200000000>, |
| <0 0>, |
| <0 0>, |
| <37500000 150000000>, |
| <0 0>, |
| <0 0>, |
| <0 0>, |
| <0 0>; |
| |
| status = "disabled"; |
| }; |
| |
| ufs_mem_phy: phy@1d87000 { |
| compatible = "qcom,sdm845-qmp-ufs-phy"; |
| reg = <0 0x01d87000 0 0x18c>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| clock-names = "ref", |
| "ref_aux"; |
| clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>, |
| <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; |
| |
| status = "disabled"; |
| |
| ufs_mem_phy_lanes: lanes@1d87400 { |
| reg = <0 0x01d87400 0 0x108>, |
| <0 0x01d87600 0 0x1e0>, |
| <0 0x01d87c00 0 0x1dc>, |
| <0 0x01d87800 0 0x108>, |
| <0 0x01d87a00 0 0x1e0>; |
| #phy-cells = <0>; |
| }; |
| }; |
| |
| tcsr_mutex_regs: syscon@1f40000 { |
| compatible = "syscon"; |
| reg = <0 0x01f40000 0 0x40000>; |
| }; |
| |
| tlmm: pinctrl@3400000 { |
| compatible = "qcom,sdm845-pinctrl"; |
| reg = <0 0x03400000 0 0xc00000>; |
| interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| gpio-ranges = <&tlmm 0 0 150>; |
| |
| qspi_clk: qspi-clk { |
| pinmux { |
| pins = "gpio95"; |
| function = "qspi_clk"; |
| }; |
| }; |
| |
| qspi_cs0: qspi-cs0 { |
| pinmux { |
| pins = "gpio90"; |
| function = "qspi_cs"; |
| }; |
| }; |
| |
| qspi_cs1: qspi-cs1 { |
| pinmux { |
| pins = "gpio89"; |
| function = "qspi_cs"; |
| }; |
| }; |
| |
| qspi_data01: qspi-data01 { |
| pinmux-data { |
| pins = "gpio91", "gpio92"; |
| function = "qspi_data"; |
| }; |
| }; |
| |
| qspi_data12: qspi-data12 { |
| pinmux-data { |
| pins = "gpio93", "gpio94"; |
| function = "qspi_data"; |
| }; |
| }; |
| |
| qup_i2c0_default: qup-i2c0-default { |
| pinmux { |
| pins = "gpio0", "gpio1"; |
| function = "qup0"; |
| }; |
| }; |
| |
| qup_i2c1_default: qup-i2c1-default { |
| pinmux { |
| pins = "gpio17", "gpio18"; |
| function = "qup1"; |
| }; |
| }; |
| |
| qup_i2c2_default: qup-i2c2-default { |
| pinmux { |
| pins = "gpio27", "gpio28"; |
| function = "qup2"; |
| }; |
| }; |
| |
| qup_i2c3_default: qup-i2c3-default { |
| pinmux { |
| pins = "gpio41", "gpio42"; |
| function = "qup3"; |
| }; |
| }; |
| |
| qup_i2c4_default: qup-i2c4-default { |
| pinmux { |
| pins = "gpio89", "gpio90"; |
| function = "qup4"; |
| }; |
| }; |
| |
| qup_i2c5_default: qup-i2c5-default { |
| pinmux { |
| pins = "gpio85", "gpio86"; |
| function = "qup5"; |
| }; |
| }; |
| |
| qup_i2c6_default: qup-i2c6-default { |
| pinmux { |
| pins = "gpio45", "gpio46"; |
| function = "qup6"; |
| }; |
| }; |
| |
| qup_i2c7_default: qup-i2c7-default { |
| pinmux { |
| pins = "gpio93", "gpio94"; |
| function = "qup7"; |
| }; |
| }; |
| |
| qup_i2c8_default: qup-i2c8-default { |
| pinmux { |
| pins = "gpio65", "gpio66"; |
| function = "qup8"; |
| }; |
| }; |
| |
| qup_i2c9_default: qup-i2c9-default { |
| pinmux { |
| pins = "gpio6", "gpio7"; |
| function = "qup9"; |
| }; |
| }; |
| |
| qup_i2c10_default: qup-i2c10-default { |
| pinmux { |
| pins = "gpio55", "gpio56"; |
| function = "qup10"; |
| }; |
| }; |
| |
| qup_i2c11_default: qup-i2c11-default { |
| pinmux { |
| pins = "gpio31", "gpio32"; |
| function = "qup11"; |
| }; |
| }; |
| |
| qup_i2c12_default: qup-i2c12-default { |
| pinmux { |
| pins = "gpio49", "gpio50"; |
| function = "qup12"; |
| }; |
| }; |
| |
| qup_i2c13_default: qup-i2c13-default { |
| pinmux { |
| pins = "gpio105", "gpio106"; |
| function = "qup13"; |
| }; |
| }; |
| |
| qup_i2c14_default: qup-i2c14-default { |
| pinmux { |
| pins = "gpio33", "gpio34"; |
| function = "qup14"; |
| }; |
| }; |
| |
| qup_i2c15_default: qup-i2c15-default { |
| pinmux { |
| pins = "gpio81", "gpio82"; |
| function = "qup15"; |
| }; |
| }; |
| |
| qup_spi0_default: qup-spi0-default { |
| pinmux { |
| pins = "gpio0", "gpio1", |
| "gpio2", "gpio3"; |
| function = "qup0"; |
| }; |
| }; |
| |
| qup_spi1_default: qup-spi1-default { |
| pinmux { |
| pins = "gpio17", "gpio18", |
| "gpio19", "gpio20"; |
| function = "qup1"; |
| }; |
| }; |
| |
| qup_spi2_default: qup-spi2-default { |
| pinmux { |
| pins = "gpio27", "gpio28", |
| "gpio29", "gpio30"; |
| function = "qup2"; |
| }; |
| }; |
| |
| qup_spi3_default: qup-spi3-default { |
| pinmux { |
| pins = "gpio41", "gpio42", |
| "gpio43", "gpio44"; |
| function = "qup3"; |
| }; |
| }; |
| |
| qup_spi4_default: qup-spi4-default { |
| pinmux { |
| pins = "gpio89", "gpio90", |
| "gpio91", "gpio92"; |
| function = "qup4"; |
| }; |
| }; |
| |
| qup_spi5_default: qup-spi5-default { |
| pinmux { |
| pins = "gpio85", "gpio86", |
| "gpio87", "gpio88"; |
| function = "qup5"; |
| }; |
| }; |
| |
| qup_spi6_default: qup-spi6-default { |
| pinmux { |
| pins = "gpio45", "gpio46", |
| "gpio47", "gpio48"; |
| function = "qup6"; |
| }; |
| }; |
| |
| qup_spi7_default: qup-spi7-default { |
| pinmux { |
| pins = "gpio93", "gpio94", |
| "gpio95", "gpio96"; |
| function = "qup7"; |
| }; |
| }; |
| |
| qup_spi8_default: qup-spi8-default { |
| pinmux { |
| pins = "gpio65", "gpio66", |
| "gpio67", "gpio68"; |
| function = "qup8"; |
| }; |
| }; |
| |
| qup_spi9_default: qup-spi9-default { |
| pinmux { |
| pins = "gpio6", "gpio7", |
| "gpio4", "gpio5"; |
| function = "qup9"; |
| }; |
| }; |
| |
| qup_spi10_default: qup-spi10-default { |
| pinmux { |
| pins = "gpio55", "gpio56", |
| "gpio53", "gpio54"; |
| function = "qup10"; |
| }; |
| }; |
| |
| qup_spi11_default: qup-spi11-default { |
| pinmux { |
| pins = "gpio31", "gpio32", |
| "gpio33", "gpio34"; |
| function = "qup11"; |
| }; |
| }; |
| |
| qup_spi12_default: qup-spi12-default { |
| pinmux { |
| pins = "gpio49", "gpio50", |
| "gpio51", "gpio52"; |
| function = "qup12"; |
| }; |
| }; |
| |
| qup_spi13_default: qup-spi13-default { |
| pinmux { |
| pins = "gpio105", "gpio106", |
| "gpio107", "gpio108"; |
| function = "qup13"; |
| }; |
| }; |
| |
| qup_spi14_default: qup-spi14-default { |
| pinmux { |
| pins = "gpio33", "gpio34", |
| "gpio31", "gpio32"; |
| function = "qup14"; |
| }; |
| }; |
| |
| qup_spi15_default: qup-spi15-default { |
| pinmux { |
| pins = "gpio81", "gpio82", |
| "gpio83", "gpio84"; |
| function = "qup15"; |
| }; |
| }; |
| |
| qup_uart0_default: qup-uart0-default { |
| pinmux { |
| pins = "gpio2", "gpio3"; |
| function = "qup0"; |
| }; |
| }; |
| |
| qup_uart1_default: qup-uart1-default { |
| pinmux { |
| pins = "gpio19", "gpio20"; |
| function = "qup1"; |
| }; |
| }; |
| |
| qup_uart2_default: qup-uart2-default { |
| pinmux { |
| pins = "gpio29", "gpio30"; |
| function = "qup2"; |
| }; |
| }; |
| |
| qup_uart3_default: qup-uart3-default { |
| pinmux { |
| pins = "gpio43", "gpio44"; |
| function = "qup3"; |
| }; |
| }; |
| |
| qup_uart4_default: qup-uart4-default { |
| pinmux { |
| pins = "gpio91", "gpio92"; |
| function = "qup4"; |
| }; |
| }; |
| |
| qup_uart5_default: qup-uart5-default { |
| pinmux { |
| pins = "gpio87", "gpio88"; |
| function = "qup5"; |
| }; |
| }; |
| |
| qup_uart6_default: qup-uart6-default { |
| pinmux { |
| pins = "gpio47", "gpio48"; |
| function = "qup6"; |
| }; |
| }; |
| |
| qup_uart7_default: qup-uart7-default { |
| pinmux { |
| pins = "gpio95", "gpio96"; |
| function = "qup7"; |
| }; |
| }; |
| |
| qup_uart8_default: qup-uart8-default { |
| pinmux { |
| pins = "gpio67", "gpio68"; |
| function = "qup8"; |
| }; |
| }; |
| |
| qup_uart9_default: qup-uart9-default { |
| pinmux { |
| pins = "gpio4", "gpio5"; |
| function = "qup9"; |
| }; |
| }; |
| |
| qup_uart10_default: qup-uart10-default { |
| pinmux { |
| pins = "gpio53", "gpio54"; |
| function = "qup10"; |
| }; |
| }; |
| |
| qup_uart11_default: qup-uart11-default { |
| pinmux { |
| pins = "gpio33", "gpio34"; |
| function = "qup11"; |
| }; |
| }; |
| |
| qup_uart12_default: qup-uart12-default { |
| pinmux { |
| pins = "gpio51", "gpio52"; |
| function = "qup12"; |
| }; |
| }; |
| |
| qup_uart13_default: qup-uart13-default { |
| pinmux { |
| pins = "gpio107", "gpio108"; |
| function = "qup13"; |
| }; |
| }; |
| |
| qup_uart14_default: qup-uart14-default { |
| pinmux { |
| pins = "gpio31", "gpio32"; |
| function = "qup14"; |
| }; |
| }; |
| |
| qup_uart15_default: qup-uart15-default { |
| pinmux { |
| pins = "gpio83", "gpio84"; |
| function = "qup15"; |
| }; |
| }; |
| }; |
| |
| gpucc: clock-controller@5090000 { |
| compatible = "qcom,sdm845-gpucc"; |
| reg = <0 0x05090000 0 0x9000>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| #power-domain-cells = <1>; |
| clocks = <&rpmhcc RPMH_CXO_CLK>; |
| clock-names = "xo"; |
| }; |
| |
| sdhc_2: sdhci@8804000 { |
| compatible = "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"; |
| reg = <0 0x08804000 0 0x1000>; |
| |
| interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "hc_irq", "pwr_irq"; |
| |
| clocks = <&gcc GCC_SDCC2_AHB_CLK>, |
| <&gcc GCC_SDCC2_APPS_CLK>; |
| clock-names = "iface", "core"; |
| iommus = <&apps_smmu 0xa0 0xf>; |
| |
| status = "disabled"; |
| }; |
| |
| qspi: spi@88df000 { |
| compatible = "qcom,sdm845-qspi", "qcom,qspi-v1"; |
| reg = <0 0x088df000 0 0x600>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, |
| <&gcc GCC_QSPI_CORE_CLK>; |
| clock-names = "iface", "core"; |
| status = "disabled"; |
| }; |
| |
| usb_1_hsphy: phy@88e2000 { |
| compatible = "qcom,sdm845-qusb2-phy"; |
| reg = <0 0x088e2000 0 0x400>; |
| status = "disabled"; |
| #phy-cells = <0>; |
| |
| clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, |
| <&rpmhcc RPMH_CXO_CLK>; |
| clock-names = "cfg_ahb", "ref"; |
| |
| resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; |
| |
| nvmem-cells = <&qusb2p_hstx_trim>; |
| }; |
| |
| usb_2_hsphy: phy@88e3000 { |
| compatible = "qcom,sdm845-qusb2-phy"; |
| reg = <0 0x088e3000 0 0x400>; |
| status = "disabled"; |
| #phy-cells = <0>; |
| |
| clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, |
| <&rpmhcc RPMH_CXO_CLK>; |
| clock-names = "cfg_ahb", "ref"; |
| |
| resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; |
| |
| nvmem-cells = <&qusb2s_hstx_trim>; |
| }; |
| |
| usb_1_qmpphy: phy@88e9000 { |
| compatible = "qcom,sdm845-qmp-usb3-phy"; |
| reg = <0 0x088e9000 0 0x18c>, |
| <0 0x088e8000 0 0x10>; |
| reg-names = "reg-base", "dp_com"; |
| status = "disabled"; |
| #clock-cells = <1>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, |
| <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, |
| <&gcc GCC_USB3_PRIM_CLKREF_CLK>, |
| <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; |
| clock-names = "aux", "cfg_ahb", "ref", "com_aux"; |
| |
| resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, |
| <&gcc GCC_USB3_PHY_PRIM_BCR>; |
| reset-names = "phy", "common"; |
| |
| usb_1_ssphy: lanes@88e9200 { |
| reg = <0 0x088e9200 0 0x128>, |
| <0 0x088e9400 0 0x200>, |
| <0 0x088e9c00 0 0x218>, |
| <0 0x088e9600 0 0x128>, |
| <0 0x088e9800 0 0x200>, |
| <0 0x088e9a00 0 0x100>; |
| #phy-cells = <0>; |
| clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; |
| clock-names = "pipe0"; |
| clock-output-names = "usb3_phy_pipe_clk_src"; |
| }; |
| }; |
| |
| usb_2_qmpphy: phy@88eb000 { |
| compatible = "qcom,sdm845-qmp-usb3-uni-phy"; |
| reg = <0 0x088eb000 0 0x18c>; |
| status = "disabled"; |
| #clock-cells = <1>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>, |
| <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, |
| <&gcc GCC_USB3_SEC_CLKREF_CLK>, |
| <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>; |
| clock-names = "aux", "cfg_ahb", "ref", "com_aux"; |
| |
| resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, |
| <&gcc GCC_USB3_PHY_SEC_BCR>; |
| reset-names = "phy", "common"; |
| |
| usb_2_ssphy: lane@88eb200 { |
| reg = <0 0x088eb200 0 0x128>, |
| <0 0x088eb400 0 0x1fc>, |
| <0 0x088eb800 0 0x218>, |
| <0 0x088eb600 0 0x70>; |
| #phy-cells = <0>; |
| clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>; |
| clock-names = "pipe0"; |
| clock-output-names = "usb3_uni_phy_pipe_clk_src"; |
| }; |
| }; |
| |
| usb_1: usb@a6f8800 { |
| compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; |
| reg = <0 0x0a6f8800 0 0x400>; |
| status = "disabled"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| dma-ranges; |
| |
| clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, |
| <&gcc GCC_USB30_PRIM_MASTER_CLK>, |
| <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, |
| <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, |
| <&gcc GCC_USB30_PRIM_SLEEP_CLK>; |
| clock-names = "cfg_noc", "core", "iface", "mock_utmi", |
| "sleep"; |
| |
| assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, |
| <&gcc GCC_USB30_PRIM_MASTER_CLK>; |
| assigned-clock-rates = <19200000>, <150000000>; |
| |
| interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "hs_phy_irq", "ss_phy_irq", |
| "dm_hs_phy_irq", "dp_hs_phy_irq"; |
| |
| power-domains = <&gcc USB30_PRIM_GDSC>; |
| |
| resets = <&gcc GCC_USB30_PRIM_BCR>; |
| |
| usb_1_dwc3: dwc3@a600000 { |
| compatible = "snps,dwc3"; |
| reg = <0 0x0a600000 0 0xcd00>; |
| interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; |
| iommus = <&apps_smmu 0x740 0>; |
| snps,dis_u2_susphy_quirk; |
| snps,dis_enblslpm_quirk; |
| phys = <&usb_1_hsphy>, <&usb_1_ssphy>; |
| phy-names = "usb2-phy", "usb3-phy"; |
| }; |
| }; |
| |
| usb_2: usb@a8f8800 { |
| compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; |
| reg = <0 0x0a8f8800 0 0x400>; |
| status = "disabled"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| dma-ranges; |
| |
| clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, |
| <&gcc GCC_USB30_SEC_MASTER_CLK>, |
| <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, |
| <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, |
| <&gcc GCC_USB30_SEC_SLEEP_CLK>; |
| clock-names = "cfg_noc", "core", "iface", "mock_utmi", |
| "sleep"; |
| |
| assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, |
| <&gcc GCC_USB30_SEC_MASTER_CLK>; |
| assigned-clock-rates = <19200000>, <150000000>; |
| |
| interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "hs_phy_irq", "ss_phy_irq", |
| "dm_hs_phy_irq", "dp_hs_phy_irq"; |
| |
| power-domains = <&gcc USB30_SEC_GDSC>; |
| |
| resets = <&gcc GCC_USB30_SEC_BCR>; |
| |
| usb_2_dwc3: dwc3@a800000 { |
| compatible = "snps,dwc3"; |
| reg = <0 0x0a800000 0 0xcd00>; |
| interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; |
| iommus = <&apps_smmu 0x760 0>; |
| snps,dis_u2_susphy_quirk; |
| snps,dis_enblslpm_quirk; |
| phys = <&usb_2_hsphy>, <&usb_2_ssphy>; |
| phy-names = "usb2-phy", "usb3-phy"; |
| }; |
| }; |
| |
| videocc: clock-controller@ab00000 { |
| compatible = "qcom,sdm845-videocc"; |
| reg = <0 0x0ab00000 0 0x10000>; |
| #clock-cells = <1>; |
| #power-domain-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| mdss: mdss@ae00000 { |
| compatible = "qcom,sdm845-mdss"; |
| reg = <0 0x0ae00000 0 0x1000>; |
| reg-names = "mdss"; |
| |
| power-domains = <&dispcc MDSS_GDSC>; |
| |
| clocks = <&gcc GCC_DISP_AHB_CLK>, |
| <&gcc GCC_DISP_AXI_CLK>, |
| <&dispcc DISP_CC_MDSS_MDP_CLK>; |
| clock-names = "iface", "bus", "core"; |
| |
| assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>; |
| assigned-clock-rates = <300000000>; |
| |
| interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-controller; |
| #interrupt-cells = <1>; |
| |
| iommus = <&apps_smmu 0x880 0x8>, |
| <&apps_smmu 0xc80 0x8>; |
| |
| status = "disabled"; |
| |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| mdss_mdp: mdp@ae01000 { |
| compatible = "qcom,sdm845-dpu"; |
| reg = <0 0x0ae01000 0 0x8f000>, |
| <0 0x0aeb0000 0 0x2008>; |
| reg-names = "mdp", "vbif"; |
| |
| clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, |
| <&dispcc DISP_CC_MDSS_AXI_CLK>, |
| <&dispcc DISP_CC_MDSS_MDP_CLK>, |
| <&dispcc DISP_CC_MDSS_VSYNC_CLK>; |
| clock-names = "iface", "bus", "core", "vsync"; |
| |
| assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>, |
| <&dispcc DISP_CC_MDSS_VSYNC_CLK>; |
| assigned-clock-rates = <300000000>, |
| <19200000>; |
| |
| interrupt-parent = <&mdss>; |
| interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; |
| |
| status = "disabled"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| dpu_intf1_out: endpoint { |
| remote-endpoint = <&dsi0_in>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| dpu_intf2_out: endpoint { |
| remote-endpoint = <&dsi1_in>; |
| }; |
| }; |
| }; |
| }; |
| |
| dsi0: dsi@ae94000 { |
| compatible = "qcom,mdss-dsi-ctrl"; |
| reg = <0 0x0ae94000 0 0x400>; |
| reg-names = "dsi_ctrl"; |
| |
| interrupt-parent = <&mdss>; |
| interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, |
| <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, |
| <&dispcc DISP_CC_MDSS_PCLK0_CLK>, |
| <&dispcc DISP_CC_MDSS_ESC0_CLK>, |
| <&dispcc DISP_CC_MDSS_AHB_CLK>, |
| <&dispcc DISP_CC_MDSS_AXI_CLK>; |
| clock-names = "byte", |
| "byte_intf", |
| "pixel", |
| "core", |
| "iface", |
| "bus"; |
| |
| phys = <&dsi0_phy>; |
| phy-names = "dsi"; |
| |
| status = "disabled"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| dsi0_in: endpoint { |
| remote-endpoint = <&dpu_intf1_out>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| dsi0_out: endpoint { |
| }; |
| }; |
| }; |
| }; |
| |
| dsi0_phy: dsi-phy@ae94400 { |
| compatible = "qcom,dsi-phy-10nm"; |
| reg = <0 0x0ae94400 0 0x200>, |
| <0 0x0ae94600 0 0x280>, |
| <0 0x0ae94a00 0 0x1e0>; |
| reg-names = "dsi_phy", |
| "dsi_phy_lane", |
| "dsi_pll"; |
| |
| #clock-cells = <1>; |
| #phy-cells = <0>; |
| |
| clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>; |
| clock-names = "iface"; |
| |
| status = "disabled"; |
| }; |
| |
| dsi1: dsi@ae96000 { |
| compatible = "qcom,mdss-dsi-ctrl"; |
| reg = <0 0x0ae96000 0 0x400>; |
| reg-names = "dsi_ctrl"; |
| |
| interrupt-parent = <&mdss>; |
| interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, |
| <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, |
| <&dispcc DISP_CC_MDSS_PCLK1_CLK>, |
| <&dispcc DISP_CC_MDSS_ESC1_CLK>, |
| <&dispcc DISP_CC_MDSS_AHB_CLK>, |
| <&dispcc DISP_CC_MDSS_AXI_CLK>; |
| clock-names = "byte", |
| "byte_intf", |
| "pixel", |
| "core", |
| "iface", |
| "bus"; |
| |
| phys = <&dsi1_phy>; |
| phy-names = "dsi"; |
| |
| status = "disabled"; |
| |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| dsi1_in: endpoint { |
| remote-endpoint = <&dpu_intf2_out>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| dsi1_out: endpoint { |
| }; |
| }; |
| }; |
| }; |
| |
| dsi1_phy: dsi-phy@ae96400 { |
| compatible = "qcom,dsi-phy-10nm"; |
| reg = <0 0x0ae96400 0 0x200>, |
| <0 0x0ae96600 0 0x280>, |
| <0 0x0ae96a00 0 0x10e>; |
| reg-names = "dsi_phy", |
| "dsi_phy_lane", |
| "dsi_pll"; |
| |
| #clock-cells = <1>; |
| #phy-cells = <0>; |
| |
| clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>; |
| clock-names = "iface"; |
| |
| status = "disabled"; |
| }; |
| }; |
| |
| dispcc: clock-controller@af00000 { |
| compatible = "qcom,sdm845-dispcc"; |
| reg = <0 0x0af00000 0 0x10000>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| #power-domain-cells = <1>; |
| }; |
| |
| pdc_reset: reset-controller@b2e0000 { |
| compatible = "qcom,sdm845-pdc-global"; |
| reg = <0 0x0b2e0000 0 0x20000>; |
| #reset-cells = <1>; |
| }; |
| |
| tsens0: thermal-sensor@c263000 { |
| compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; |
| reg = <0 0x0c263000 0 0x1ff>, /* TM */ |
| <0 0x0c222000 0 0x1ff>; /* SROT */ |
| #qcom,sensors = <13>; |
| #thermal-sensor-cells = <1>; |
| }; |
| |
| tsens1: thermal-sensor@c265000 { |
| compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; |
| reg = <0 0x0c265000 0 0x1ff>, /* TM */ |
| <0 0x0c223000 0 0x1ff>; /* SROT */ |
| #qcom,sensors = <8>; |
| #thermal-sensor-cells = <1>; |
| }; |
| |
| aoss_reset: reset-controller@c2a0000 { |
| compatible = "qcom,sdm845-aoss-cc"; |
| reg = <0 0x0c2a0000 0 0x31000>; |
| #reset-cells = <1>; |
| }; |
| |
| spmi_bus: spmi@c440000 { |
| compatible = "qcom,spmi-pmic-arb"; |
| reg = <0 0x0c440000 0 0x1100>, |
| <0 0x0c600000 0 0x2000000>, |
| <0 0x0e600000 0 0x100000>, |
| <0 0x0e700000 0 0xa0000>, |
| <0 0x0c40a000 0 0x26000>; |
| reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; |
| interrupt-names = "periph_irq"; |
| interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; |
| qcom,ee = <0>; |
| qcom,channel = <0>; |
| #address-cells = <2>; |
| #size-cells = <0>; |
| interrupt-controller; |
| #interrupt-cells = <4>; |
| cell-index = <0>; |
| }; |
| |
| apps_smmu: iommu@15000000 { |
| compatible = "qcom,sdm845-smmu-500", "arm,mmu-500"; |
| reg = <0 0x15000000 0 0x80000>; |
| #iommu-cells = <2>; |
| #global-interrupts = <1>; |
| interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| lpasscc: clock-controller@17014000 { |
| compatible = "qcom,sdm845-lpasscc"; |
| reg = <0 0x17014000 0 0x1f004>, <0 0x17300000 0 0x200>; |
| reg-names = "cc", "qdsp6ss"; |
| #clock-cells = <1>; |
| status = "disabled"; |
| }; |
| |
| apss_shared: mailbox@17990000 { |
| compatible = "qcom,sdm845-apss-shared"; |
| reg = <0 0x17990000 0 0x1000>; |
| #mbox-cells = <1>; |
| }; |
| |
| apps_rsc: rsc@179c0000 { |
| label = "apps_rsc"; |
| compatible = "qcom,rpmh-rsc"; |
| reg = <0 0x179c0000 0 0x10000>, |
| <0 0x179d0000 0 0x10000>, |
| <0 0x179e0000 0 0x10000>; |
| reg-names = "drv-0", "drv-1", "drv-2"; |
| interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
| qcom,tcs-offset = <0xd00>; |
| qcom,drv-id = <2>; |
| qcom,tcs-config = <ACTIVE_TCS 2>, |
| <SLEEP_TCS 3>, |
| <WAKE_TCS 3>, |
| <CONTROL_TCS 1>; |
| |
| rpmhcc: clock-controller { |
| compatible = "qcom,sdm845-rpmh-clk"; |
| #clock-cells = <1>; |
| }; |
| |
| rpmhpd: power-controller { |
| compatible = "qcom,sdm845-rpmhpd"; |
| #power-domain-cells = <1>; |
| operating-points-v2 = <&rpmhpd_opp_table>; |
| |
| rpmhpd_opp_table: opp-table { |
| compatible = "operating-points-v2"; |
| |
| rpmhpd_opp_ret: opp1 { |
| opp-level = <16>; |
| }; |
| |
| rpmhpd_opp_min_svs: opp2 { |
| opp-level = <48>; |
| }; |
| |
| rpmhpd_opp_low_svs: opp3 { |
| opp-level = <64>; |
| }; |
| |
| rpmhpd_opp_svs: opp4 { |
| opp-level = <128>; |
| }; |
| |
| rpmhpd_opp_svs_l1: opp5 { |
| opp-level = <192>; |
| }; |
| |
| rpmhpd_opp_nom: opp6 { |
| opp-level = <256>; |
| }; |
| |
| rpmhpd_opp_nom_l1: opp7 { |
| opp-level = <320>; |
| }; |
| |
| rpmhpd_opp_nom_l2: opp8 { |
| opp-level = <336>; |
| }; |
| |
| rpmhpd_opp_turbo: opp9 { |
| opp-level = <384>; |
| }; |
| |
| rpmhpd_opp_turbo_l1: opp10 { |
| opp-level = <416>; |
| }; |
| }; |
| }; |
| |
| rsc_hlos: interconnect { |
| compatible = "qcom,sdm845-rsc-hlos"; |
| #interconnect-cells = <1>; |
| }; |
| }; |
| |
| intc: interrupt-controller@17a00000 { |
| compatible = "arm,gic-v3"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| reg = <0 0x17a00000 0 0x10000>, /* GICD */ |
| <0 0x17a60000 0 0x100000>; /* GICR * 8 */ |
| interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| |
| gic-its@17a40000 { |
| compatible = "arm,gic-v3-its"; |
| msi-controller; |
| #msi-cells = <1>; |
| reg = <0 0x17a40000 0 0x20000>; |
| status = "disabled"; |
| }; |
| }; |
| |
| timer@17c90000 { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| compatible = "arm,armv7-timer-mem"; |
| reg = <0 0x17c90000 0 0x1000>; |
| |
| frame@17ca0000 { |
| frame-number = <0>; |
| interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0 0x17ca0000 0 0x1000>, |
| <0 0x17cb0000 0 0x1000>; |
| }; |
| |
| frame@17cc0000 { |
| frame-number = <1>; |
| interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0 0x17cc0000 0 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17cd0000 { |
| frame-number = <2>; |
| interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0 0x17cd0000 0 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17ce0000 { |
| frame-number = <3>; |
| interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0 0x17ce0000 0 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17cf0000 { |
| frame-number = <4>; |
| interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0 0x17cf0000 0 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17d00000 { |
| frame-number = <5>; |
| interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0 0x17d00000 0 0x1000>; |
| status = "disabled"; |
| }; |
| |
| frame@17d10000 { |
| frame-number = <6>; |
| interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| reg = <0 0x17d10000 0 0x1000>; |
| status = "disabled"; |
| }; |
| }; |
| |
| cpufreq_hw: cpufreq@17d43000 { |
| compatible = "qcom,cpufreq-hw"; |
| reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; |
| reg-names = "freq-domain0", "freq-domain1"; |
| |
| clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; |
| clock-names = "xo", "alternate"; |
| |
| #freq-domain-cells = <1>; |
| }; |
| |
| wifi: wifi@18800000 { |
| compatible = "qcom,wcn3990-wifi"; |
| status = "disabled"; |
| reg = <0 0x18800000 0 0x800000>; |
| reg-names = "membase"; |
| memory-region = <&wlan_msa_mem>; |
| clock-names = "cxo_ref_clk_pin"; |
| clocks = <&rpmhcc RPMH_RF_CLK2>; |
| interrupts = |
| <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; |
| iommus = <&apps_smmu 0x0040 0x1>; |
| }; |
| }; |
| |
| thermal-zones { |
| cpu0-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens0 1>; |
| |
| trips { |
| cpu0_alert0: trip-point@0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu0_alert1: trip-point@1 { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu0_crit: cpu_crit { |
| temperature = <110000>; |
| hysteresis = <1000>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu0_alert0>; |
| cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| map1 { |
| trip = <&cpu0_alert1>; |
| cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| |
| cpu1-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens0 2>; |
| |
| trips { |
| cpu1_alert0: trip-point@0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu1_alert1: trip-point@1 { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu1_crit: cpu_crit { |
| temperature = <110000>; |
| hysteresis = <1000>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu1_alert0>; |
| cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| map1 { |
| trip = <&cpu1_alert1>; |
| cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| |
| cpu2-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens0 3>; |
| |
| trips { |
| cpu2_alert0: trip-point@0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu2_alert1: trip-point@1 { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu2_crit: cpu_crit { |
| temperature = <110000>; |
| hysteresis = <1000>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu2_alert0>; |
| cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| map1 { |
| trip = <&cpu2_alert1>; |
| cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| |
| cpu3-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens0 4>; |
| |
| trips { |
| cpu3_alert0: trip-point@0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu3_alert1: trip-point@1 { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu3_crit: cpu_crit { |
| temperature = <110000>; |
| hysteresis = <1000>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu3_alert0>; |
| cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| map1 { |
| trip = <&cpu3_alert1>; |
| cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| |
| cpu4-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens0 7>; |
| |
| trips { |
| cpu4_alert0: trip-point@0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu4_alert1: trip-point@1 { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu4_crit: cpu_crit { |
| temperature = <110000>; |
| hysteresis = <1000>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu4_alert0>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| map1 { |
| trip = <&cpu4_alert1>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| |
| cpu5-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens0 8>; |
| |
| trips { |
| cpu5_alert0: trip-point@0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu5_alert1: trip-point@1 { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu5_crit: cpu_crit { |
| temperature = <110000>; |
| hysteresis = <1000>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu5_alert0>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| map1 { |
| trip = <&cpu5_alert1>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| |
| cpu6-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens0 9>; |
| |
| trips { |
| cpu6_alert0: trip-point@0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu6_alert1: trip-point@1 { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu6_crit: cpu_crit { |
| temperature = <110000>; |
| hysteresis = <1000>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu6_alert0>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| map1 { |
| trip = <&cpu6_alert1>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| |
| cpu7-thermal { |
| polling-delay-passive = <250>; |
| polling-delay = <1000>; |
| |
| thermal-sensors = <&tsens0 10>; |
| |
| trips { |
| cpu7_alert0: trip-point@0 { |
| temperature = <90000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu7_alert1: trip-point@1 { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu7_crit: cpu_crit { |
| temperature = <110000>; |
| hysteresis = <1000>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu7_alert0>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| map1 { |
| trip = <&cpu7_alert1>; |
| cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, |
| <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| }; |
| }; |
