| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Device Tree Include file for NXP Layerscape-1088A family SoC. |
| * |
| * Copyright 2017 NXP |
| * |
| * Harninder Rai <harninder.rai@nxp.com> |
| * |
| */ |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/thermal/thermal.h> |
| |
| / { |
| compatible = "fsl,ls1088a"; |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| aliases { |
| crypto = &crypto; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| /* We have 2 clusters having 4 Cortex-A53 cores each */ |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x0>; |
| clocks = <&clockgen 1 0>; |
| cpu-idle-states = <&CPU_PH20>; |
| #cooling-cells = <2>; |
| }; |
| |
| cpu1: cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x1>; |
| clocks = <&clockgen 1 0>; |
| cpu-idle-states = <&CPU_PH20>; |
| #cooling-cells = <2>; |
| }; |
| |
| cpu2: cpu@2 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x2>; |
| clocks = <&clockgen 1 0>; |
| cpu-idle-states = <&CPU_PH20>; |
| #cooling-cells = <2>; |
| }; |
| |
| cpu3: cpu@3 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x3>; |
| clocks = <&clockgen 1 0>; |
| cpu-idle-states = <&CPU_PH20>; |
| #cooling-cells = <2>; |
| }; |
| |
| cpu4: cpu@100 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x100>; |
| clocks = <&clockgen 1 1>; |
| cpu-idle-states = <&CPU_PH20>; |
| #cooling-cells = <2>; |
| }; |
| |
| cpu5: cpu@101 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x101>; |
| clocks = <&clockgen 1 1>; |
| cpu-idle-states = <&CPU_PH20>; |
| #cooling-cells = <2>; |
| }; |
| |
| cpu6: cpu@102 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x102>; |
| clocks = <&clockgen 1 1>; |
| cpu-idle-states = <&CPU_PH20>; |
| #cooling-cells = <2>; |
| }; |
| |
| cpu7: cpu@103 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53"; |
| reg = <0x103>; |
| clocks = <&clockgen 1 1>; |
| cpu-idle-states = <&CPU_PH20>; |
| #cooling-cells = <2>; |
| }; |
| |
| CPU_PH20: cpu-ph20 { |
| compatible = "arm,idle-state"; |
| idle-state-name = "PH20"; |
| arm,psci-suspend-param = <0x0>; |
| entry-latency-us = <1000>; |
| exit-latency-us = <1000>; |
| min-residency-us = <3000>; |
| }; |
| }; |
| |
| gic: interrupt-controller@6000000 { |
| compatible = "arm,gic-v3"; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ |
| <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/ |
| <0x0 0x0c0c0000 0 0x2000>, /* GICC */ |
| <0x0 0x0c0d0000 0 0x1000>, /* GICH */ |
| <0x0 0x0c0e0000 0 0x20000>; /* GICV */ |
| interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| its: gic-its@6020000 { |
| compatible = "arm,gic-v3-its"; |
| msi-controller; |
| reg = <0x0 0x6020000 0 0x20000>; |
| }; |
| }; |
| |
| thermal-zones { |
| cpu_thermal: cpu-thermal { |
| polling-delay-passive = <1000>; |
| polling-delay = <5000>; |
| thermal-sensors = <&tmu 0>; |
| |
| trips { |
| cpu_alert: cpu-alert { |
| temperature = <85000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| |
| cpu_crit: cpu-crit { |
| temperature = <95000>; |
| hysteresis = <2000>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu_alert>; |
| cooling-device = |
| <&cpu0 THERMAL_NO_LIMIT |
| THERMAL_NO_LIMIT>; |
| }; |
| |
| map1 { |
| trip = <&cpu_alert>; |
| cooling-device = |
| <&cpu4 THERMAL_NO_LIMIT |
| THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ |
| <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ |
| <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ |
| <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ |
| }; |
| |
| fsl_mc: fsl-mc@80c000000 { |
| compatible = "fsl,qoriq-mc"; |
| reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ |
| <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ |
| msi-parent = <&its>; |
| #address-cells = <3>; |
| #size-cells = <1>; |
| |
| /* |
| * Region type 0x0 - MC portals |
| * Region type 0x1 - QBMAN portals |
| */ |
| ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 |
| 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; |
| |
| dpmacs { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| dpmac1: dpmac@1 { |
| compatible = "fsl,qoriq-mc-dpmac"; |
| reg = <1>; |
| }; |
| |
| dpmac2: dpmac@2 { |
| compatible = "fsl,qoriq-mc-dpmac"; |
| reg = <2>; |
| }; |
| |
| dpmac3: dpmac@3 { |
| compatible = "fsl,qoriq-mc-dpmac"; |
| reg = <3>; |
| }; |
| |
| dpmac4: dpmac@4 { |
| compatible = "fsl,qoriq-mc-dpmac"; |
| reg = <4>; |
| }; |
| |
| dpmac5: dpmac@5 { |
| compatible = "fsl,qoriq-mc-dpmac"; |
| reg = <5>; |
| }; |
| |
| dpmac6: dpmac@6 { |
| compatible = "fsl,qoriq-mc-dpmac"; |
| reg = <6>; |
| }; |
| |
| dpmac7: dpmac@7 { |
| compatible = "fsl,qoriq-mc-dpmac"; |
| reg = <7>; |
| }; |
| |
| dpmac8: dpmac@8 { |
| compatible = "fsl,qoriq-mc-dpmac"; |
| reg = <8>; |
| }; |
| |
| dpmac9: dpmac@9 { |
| compatible = "fsl,qoriq-mc-dpmac"; |
| reg = <9>; |
| }; |
| |
| dpmac10: dpmac@a { |
| compatible = "fsl,qoriq-mc-dpmac"; |
| reg = <0xa>; |
| }; |
| }; |
| }; |
| |
| psci { |
| compatible = "arm,psci-0.2"; |
| method = "smc"; |
| }; |
| |
| sysclk: sysclk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <100000000>; |
| clock-output-names = "sysclk"; |
| }; |
| |
| soc { |
| compatible = "simple-bus"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| clockgen: clocking@1300000 { |
| compatible = "fsl,ls1088a-clockgen"; |
| reg = <0 0x1300000 0 0xa0000>; |
| #clock-cells = <2>; |
| clocks = <&sysclk>; |
| }; |
| |
| dcfg: dcfg@1e00000 { |
| compatible = "fsl,ls1088a-dcfg", "syscon"; |
| reg = <0x0 0x1e00000 0x0 0x10000>; |
| little-endian; |
| }; |
| |
| tmu: tmu@1f80000 { |
| compatible = "fsl,qoriq-tmu"; |
| reg = <0x0 0x1f80000 0x0 0x10000>; |
| interrupts = <0 23 0x4>; |
| fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; |
| fsl,tmu-calibration = |
| /* Calibration data group 1 */ |
| <0x00000000 0x00000026 |
| 0x00000001 0x0000002d |
| 0x00000002 0x00000032 |
| 0x00000003 0x00000039 |
| 0x00000004 0x0000003f |
| 0x00000005 0x00000046 |
| 0x00000006 0x0000004d |
| 0x00000007 0x00000054 |
| 0x00000008 0x0000005a |
| 0x00000009 0x00000061 |
| 0x0000000a 0x0000006a |
| 0x0000000b 0x00000071 |
| /* Calibration data group 2 */ |
| 0x00010000 0x00000025 |
| 0x00010001 0x0000002c |
| 0x00010002 0x00000035 |
| 0x00010003 0x0000003d |
| 0x00010004 0x00000045 |
| 0x00010005 0x0000004e |
| 0x00010006 0x00000057 |
| 0x00010007 0x00000061 |
| 0x00010008 0x0000006b |
| 0x00010009 0x00000076 |
| /* Calibration data group 3 */ |
| 0x00020000 0x00000029 |
| 0x00020001 0x00000033 |
| 0x00020002 0x0000003d |
| 0x00020003 0x00000049 |
| 0x00020004 0x00000056 |
| 0x00020005 0x00000061 |
| 0x00020006 0x0000006d |
| /* Calibration data group 4 */ |
| 0x00030000 0x00000021 |
| 0x00030001 0x0000002a |
| 0x00030002 0x0000003c |
| 0x00030003 0x0000004e>; |
| little-endian; |
| #thermal-sensor-cells = <1>; |
| }; |
| |
| duart0: serial@21c0500 { |
| compatible = "fsl,ns16550", "ns16550a"; |
| reg = <0x0 0x21c0500 0x0 0x100>; |
| clocks = <&clockgen 4 3>; |
| interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| duart1: serial@21c0600 { |
| compatible = "fsl,ns16550", "ns16550a"; |
| reg = <0x0 0x21c0600 0x0 0x100>; |
| clocks = <&clockgen 4 3>; |
| interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; |
| status = "disabled"; |
| }; |
| |
| gpio0: gpio@2300000 { |
| compatible = "fsl,qoriq-gpio"; |
| reg = <0x0 0x2300000 0x0 0x10000>; |
| interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gpio1: gpio@2310000 { |
| compatible = "fsl,qoriq-gpio"; |
| reg = <0x0 0x2310000 0x0 0x10000>; |
| interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gpio2: gpio@2320000 { |
| compatible = "fsl,qoriq-gpio"; |
| reg = <0x0 0x2320000 0x0 0x10000>; |
| interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gpio3: gpio@2330000 { |
| compatible = "fsl,qoriq-gpio"; |
| reg = <0x0 0x2330000 0x0 0x10000>; |
| interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| ifc: ifc@2240000 { |
| compatible = "fsl,ifc", "simple-bus"; |
| reg = <0x0 0x2240000 0x0 0x20000>; |
| interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; |
| little-endian; |
| #address-cells = <2>; |
| #size-cells = <1>; |
| status = "disabled"; |
| }; |
| |
| i2c0: i2c@2000000 { |
| compatible = "fsl,vf610-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x2000000 0x0 0x10000>; |
| interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen 4 3>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@2010000 { |
| compatible = "fsl,vf610-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x2010000 0x0 0x10000>; |
| interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen 4 3>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@2020000 { |
| compatible = "fsl,vf610-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x2020000 0x0 0x10000>; |
| interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen 4 3>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@2030000 { |
| compatible = "fsl,vf610-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x2030000 0x0 0x10000>; |
| interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen 4 3>; |
| status = "disabled"; |
| }; |
| |
| esdhc: esdhc@2140000 { |
| compatible = "fsl,ls1088a-esdhc", "fsl,esdhc"; |
| reg = <0x0 0x2140000 0x0 0x10000>; |
| interrupts = <0 28 0x4>; /* Level high type */ |
| clock-frequency = <0>; |
| voltage-ranges = <1800 1800 3300 3300>; |
| sdhci,auto-cmd12; |
| little-endian; |
| bus-width = <4>; |
| status = "disabled"; |
| }; |
| |
| usb0: usb3@3100000 { |
| compatible = "snps,dwc3"; |
| reg = <0x0 0x3100000 0x0 0x10000>; |
| interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; |
| dr_mode = "host"; |
| snps,quirk-frame-length-adjustment = <0x20>; |
| snps,dis_rxdet_inp3_quirk; |
| status = "disabled"; |
| }; |
| |
| usb1: usb3@3110000 { |
| compatible = "snps,dwc3"; |
| reg = <0x0 0x3110000 0x0 0x10000>; |
| interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; |
| dr_mode = "host"; |
| snps,quirk-frame-length-adjustment = <0x20>; |
| snps,dis_rxdet_inp3_quirk; |
| status = "disabled"; |
| }; |
| |
| sata: sata@3200000 { |
| compatible = "fsl,ls1088a-ahci"; |
| reg = <0x0 0x3200000 0x0 0x10000>, |
| <0x7 0x100520 0x0 0x4>; |
| reg-names = "ahci", "sata-ecc"; |
| interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clockgen 4 3>; |
| dma-coherent; |
| status = "disabled"; |
| }; |
| |
| crypto: crypto@8000000 { |
| compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; |
| fsl,sec-era = <8>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x00 0x8000000 0x100000>; |
| reg = <0x00 0x8000000 0x0 0x100000>; |
| interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; |
| dma-coherent; |
| |
| sec_jr0: jr@10000 { |
| compatible = "fsl,sec-v5.0-job-ring", |
| "fsl,sec-v4.0-job-ring"; |
| reg = <0x10000 0x10000>; |
| interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| sec_jr1: jr@20000 { |
| compatible = "fsl,sec-v5.0-job-ring", |
| "fsl,sec-v4.0-job-ring"; |
| reg = <0x20000 0x10000>; |
| interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| sec_jr2: jr@30000 { |
| compatible = "fsl,sec-v5.0-job-ring", |
| "fsl,sec-v4.0-job-ring"; |
| reg = <0x30000 0x10000>; |
| interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| sec_jr3: jr@40000 { |
| compatible = "fsl,sec-v5.0-job-ring", |
| "fsl,sec-v4.0-job-ring"; |
| reg = <0x40000 0x10000>; |
| interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| }; |
| |
| pcie@3400000 { |
| compatible = "fsl,ls1088a-pcie", "snps,dw-pcie"; |
| reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ |
| 0x20 0x00000000 0x0 0x00002000>; /* configuration space */ |
| reg-names = "regs", "config"; |
| interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ |
| interrupt-names = "aer"; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| device_type = "pci"; |
| dma-coherent; |
| num-lanes = <4>; |
| bus-range = <0x0 0xff>; |
| ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ |
| 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ |
| msi-parent = <&its>; |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 7>; |
| interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, |
| <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, |
| <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, |
| <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| pcie@3500000 { |
| compatible = "fsl,ls1088a-pcie", "snps,dw-pcie"; |
| reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ |
| 0x28 0x00000000 0x0 0x00002000>; /* configuration space */ |
| reg-names = "regs", "config"; |
| interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ |
| interrupt-names = "aer"; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| device_type = "pci"; |
| dma-coherent; |
| num-lanes = <4>; |
| bus-range = <0x0 0xff>; |
| ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */ |
| 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ |
| msi-parent = <&its>; |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 7>; |
| interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>, |
| <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>, |
| <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>, |
| <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| pcie@3600000 { |
| compatible = "fsl,ls1088a-pcie", "snps,dw-pcie"; |
| reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ |
| 0x30 0x00000000 0x0 0x00002000>; /* configuration space */ |
| reg-names = "regs", "config"; |
| interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ |
| interrupt-names = "aer"; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| device_type = "pci"; |
| dma-coherent; |
| num-lanes = <8>; |
| bus-range = <0x0 0xff>; |
| ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */ |
| 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ |
| msi-parent = <&its>; |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 7>; |
| interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>, |
| <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>, |
| <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>, |
| <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| cluster1_core0_watchdog: wdt@c000000 { |
| compatible = "arm,sp805-wdt", "arm,primecell"; |
| reg = <0x0 0xc000000 0x0 0x1000>; |
| clocks = <&clockgen 4 3>, <&clockgen 4 3>; |
| clock-names = "apb_pclk", "wdog_clk"; |
| }; |
| |
| cluster1_core1_watchdog: wdt@c010000 { |
| compatible = "arm,sp805-wdt", "arm,primecell"; |
| reg = <0x0 0xc010000 0x0 0x1000>; |
| clocks = <&clockgen 4 3>, <&clockgen 4 3>; |
| clock-names = "apb_pclk", "wdog_clk"; |
| }; |
| |
| cluster1_core2_watchdog: wdt@c020000 { |
| compatible = "arm,sp805-wdt", "arm,primecell"; |
| reg = <0x0 0xc020000 0x0 0x1000>; |
| clocks = <&clockgen 4 3>, <&clockgen 4 3>; |
| clock-names = "apb_pclk", "wdog_clk"; |
| }; |
| |
| cluster1_core3_watchdog: wdt@c030000 { |
| compatible = "arm,sp805-wdt", "arm,primecell"; |
| reg = <0x0 0xc030000 0x0 0x1000>; |
| clocks = <&clockgen 4 3>, <&clockgen 4 3>; |
| clock-names = "apb_pclk", "wdog_clk"; |
| }; |
| |
| cluster2_core0_watchdog: wdt@c100000 { |
| compatible = "arm,sp805-wdt", "arm,primecell"; |
| reg = <0x0 0xc100000 0x0 0x1000>; |
| clocks = <&clockgen 4 3>, <&clockgen 4 3>; |
| clock-names = "apb_pclk", "wdog_clk"; |
| }; |
| |
| cluster2_core1_watchdog: wdt@c110000 { |
| compatible = "arm,sp805-wdt", "arm,primecell"; |
| reg = <0x0 0xc110000 0x0 0x1000>; |
| clocks = <&clockgen 4 3>, <&clockgen 4 3>; |
| clock-names = "apb_pclk", "wdog_clk"; |
| }; |
| |
| cluster2_core2_watchdog: wdt@c120000 { |
| compatible = "arm,sp805-wdt", "arm,primecell"; |
| reg = <0x0 0xc120000 0x0 0x1000>; |
| clocks = <&clockgen 4 3>, <&clockgen 4 3>; |
| clock-names = "apb_pclk", "wdog_clk"; |
| }; |
| |
| cluster2_core3_watchdog: wdt@c130000 { |
| compatible = "arm,sp805-wdt", "arm,primecell"; |
| reg = <0x0 0xc130000 0x0 0x1000>; |
| clocks = <&clockgen 4 3>, <&clockgen 4 3>; |
| clock-names = "apb_pclk", "wdog_clk"; |
| }; |
| }; |
| |
| firmware { |
| optee { |
| compatible = "linaro,optee-tz"; |
| method = "smc"; |
| }; |
| }; |
| |
| }; |
