| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Device Tree Include file for Freescale Layerscape-2080A family SoC. |
| * |
| * Copyright 2016 Freescale Semiconductor, Inc. |
| * Copyright 2017 NXP |
| * |
| * Abhimanyu Saini <abhimanyu.saini@nxp.com> |
| * |
| */ |
| |
| #include <dt-bindings/thermal/thermal.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| |
| / { |
| compatible = "fsl,ls2080a"; |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| aliases { |
| crypto = &crypto; |
| serial0 = &serial0; |
| serial1 = &serial1; |
| }; |
| |
| cpu: cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| |
| memory@80000000 { |
| device_type = "memory"; |
| reg = <0x00000000 0x80000000 0 0x80000000>; |
| /* DRAM space - 1, size : 2 GB DRAM */ |
| }; |
| |
| sysclk: sysclk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <100000000>; |
| clock-output-names = "sysclk"; |
| }; |
| |
| gic: interrupt-controller@6000000 { |
| compatible = "arm,gic-v3"; |
| reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ |
| <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */ |
| <0x0 0x0c0c0000 0 0x2000>, /* GICC */ |
| <0x0 0x0c0d0000 0 0x1000>, /* GICH */ |
| <0x0 0x0c0e0000 0 0x20000>; /* GICV */ |
| #interrupt-cells = <3>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| interrupt-controller; |
| interrupts = <1 9 0x4>; |
| |
| its: gic-its@6020000 { |
| compatible = "arm,gic-v3-its"; |
| msi-controller; |
| reg = <0x0 0x6020000 0 0x20000>; |
| }; |
| }; |
| |
| rstcr: syscon@1e60000 { |
| compatible = "fsl,ls2080a-rstcr", "syscon"; |
| reg = <0x0 0x1e60000 0x0 0x4>; |
| }; |
| |
| reboot { |
| compatible ="syscon-reboot"; |
| regmap = <&rstcr>; |
| offset = <0x0>; |
| mask = <0x2>; |
| }; |
| |
| thermal-zones { |
| cpu_thermal: cpu-thermal { |
| polling-delay-passive = <1000>; |
| polling-delay = <5000>; |
| |
| thermal-sensors = <&tmu 4>; |
| |
| trips { |
| cpu_alert: cpu-alert { |
| temperature = <75000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| cpu_crit: cpu-crit { |
| temperature = <85000>; |
| hysteresis = <2000>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| map0 { |
| trip = <&cpu_alert>; |
| cooling-device = |
| <&cpu0 THERMAL_NO_LIMIT |
| THERMAL_NO_LIMIT>; |
| }; |
| map1 { |
| trip = <&cpu_alert>; |
| cooling-device = |
| <&cpu2 THERMAL_NO_LIMIT |
| THERMAL_NO_LIMIT>; |
| }; |
| map2 { |
| trip = <&cpu_alert>; |
| cooling-device = |
| <&cpu4 THERMAL_NO_LIMIT |
| THERMAL_NO_LIMIT>; |
| }; |
| map3 { |
| trip = <&cpu_alert>; |
| cooling-device = |
| <&cpu6 THERMAL_NO_LIMIT |
| THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <1 13 4>, /* Physical Secure PPI, active-low */ |
| <1 14 4>, /* Physical Non-Secure PPI, active-low */ |
| <1 11 4>, /* Virtual PPI, active-low */ |
| <1 10 4>; /* Hypervisor PPI, active-low */ |
| fsl,erratum-a008585; |
| }; |
| |
| pmu { |
| compatible = "arm,armv8-pmuv3"; |
| interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ |
| }; |
| |
| psci { |
| compatible = "arm,psci-0.2"; |
| method = "smc"; |
| }; |
| |
| soc { |
| compatible = "simple-bus"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| clockgen: clocking@1300000 { |
| compatible = "fsl,ls2080a-clockgen"; |
| reg = <0 0x1300000 0 0xa0000>; |
| #clock-cells = <2>; |
| clocks = <&sysclk>; |
| }; |
| |
| dcfg: dcfg@1e00000 { |
| compatible = "fsl,ls2080a-dcfg", "syscon"; |
| reg = <0x0 0x1e00000 0x0 0x10000>; |
| little-endian; |
| }; |
| |
| tmu: tmu@1f80000 { |
| compatible = "fsl,qoriq-tmu"; |
| reg = <0x0 0x1f80000 0x0 0x10000>; |
| interrupts = <0 23 0x4>; |
| fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; |
| fsl,tmu-calibration = <0x00000000 0x00000026 |
| 0x00000001 0x0000002d |
| 0x00000002 0x00000032 |
| 0x00000003 0x00000039 |
| 0x00000004 0x0000003f |
| 0x00000005 0x00000046 |
| 0x00000006 0x0000004d |
| 0x00000007 0x00000054 |
| 0x00000008 0x0000005a |
| 0x00000009 0x00000061 |
| 0x0000000a 0x0000006a |
| 0x0000000b 0x00000071 |
| |
| 0x00010000 0x00000025 |
| 0x00010001 0x0000002c |
| 0x00010002 0x00000035 |
| 0x00010003 0x0000003d |
| 0x00010004 0x00000045 |
| 0x00010005 0x0000004e |
| 0x00010006 0x00000057 |
| 0x00010007 0x00000061 |
| 0x00010008 0x0000006b |
| 0x00010009 0x00000076 |
| |
| 0x00020000 0x00000029 |
| 0x00020001 0x00000033 |
| 0x00020002 0x0000003d |
| 0x00020003 0x00000049 |
| 0x00020004 0x00000056 |
| 0x00020005 0x00000061 |
| 0x00020006 0x0000006d |
| |
| 0x00030000 0x00000021 |
| 0x00030001 0x0000002a |
| 0x00030002 0x0000003c |
| 0x00030003 0x0000004e>; |
| little-endian; |
| #thermal-sensor-cells = <1>; |
| }; |
| |
| serial0: serial@21c0500 { |
| compatible = "fsl,ns16550", "ns16550a"; |
| reg = <0x0 0x21c0500 0x0 0x100>; |
| clocks = <&clockgen 4 3>; |
| interrupts = <0 32 0x4>; /* Level high type */ |
| }; |
| |
| serial1: serial@21c0600 { |
| compatible = "fsl,ns16550", "ns16550a"; |
| reg = <0x0 0x21c0600 0x0 0x100>; |
| clocks = <&clockgen 4 3>; |
| interrupts = <0 32 0x4>; /* Level high type */ |
| }; |
| |
| cluster1_core0_watchdog: wdt@c000000 { |
| compatible = "arm,sp805-wdt", "arm,primecell"; |
| reg = <0x0 0xc000000 0x0 0x1000>; |
| clocks = <&clockgen 4 3>, <&clockgen 4 3>; |
| clock-names = "apb_pclk", "wdog_clk"; |
| }; |
| |
| cluster1_core1_watchdog: wdt@c010000 { |
| compatible = "arm,sp805-wdt", "arm,primecell"; |
| reg = <0x0 0xc010000 0x0 0x1000>; |
| clocks = <&clockgen 4 3>, <&clockgen 4 3>; |
| clock-names = "apb_pclk", "wdog_clk"; |
| }; |
| |
| cluster2_core0_watchdog: wdt@c100000 { |
| compatible = "arm,sp805-wdt", "arm,primecell"; |
| reg = <0x0 0xc100000 0x0 0x1000>; |
| clocks = <&clockgen 4 3>, <&clockgen 4 3>; |
| clock-names = "apb_pclk", "wdog_clk"; |
| }; |
| |
| cluster2_core1_watchdog: wdt@c110000 { |
| compatible = "arm,sp805-wdt", "arm,primecell"; |
| reg = <0x0 0xc110000 0x0 0x1000>; |
| clocks = <&clockgen 4 3>, <&clockgen 4 3>; |
| clock-names = "apb_pclk", "wdog_clk"; |
| }; |
| |
| cluster3_core0_watchdog: wdt@c200000 { |
| compatible = "arm,sp805-wdt", "arm,primecell"; |
| reg = <0x0 0xc200000 0x0 0x1000>; |
| clocks = <&clockgen 4 3>, <&clockgen 4 3>; |
| clock-names = "apb_pclk", "wdog_clk"; |
| }; |
| |
| cluster3_core1_watchdog: wdt@c210000 { |
| compatible = "arm,sp805-wdt", "arm,primecell"; |
| reg = <0x0 0xc210000 0x0 0x1000>; |
| clocks = <&clockgen 4 3>, <&clockgen 4 3>; |
| clock-names = "apb_pclk", "wdog_clk"; |
| }; |
| |
| cluster4_core0_watchdog: wdt@c300000 { |
| compatible = "arm,sp805-wdt", "arm,primecell"; |
| reg = <0x0 0xc300000 0x0 0x1000>; |
| clocks = <&clockgen 4 3>, <&clockgen 4 3>; |
| clock-names = "apb_pclk", "wdog_clk"; |
| }; |
| |
| cluster4_core1_watchdog: wdt@c310000 { |
| compatible = "arm,sp805-wdt", "arm,primecell"; |
| reg = <0x0 0xc310000 0x0 0x1000>; |
| clocks = <&clockgen 4 3>, <&clockgen 4 3>; |
| clock-names = "apb_pclk", "wdog_clk"; |
| }; |
| |
| crypto: crypto@8000000 { |
| compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; |
| fsl,sec-era = <8>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0x0 0x00 0x8000000 0x100000>; |
| reg = <0x00 0x8000000 0x0 0x100000>; |
| interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; |
| dma-coherent; |
| |
| sec_jr0: jr@10000 { |
| compatible = "fsl,sec-v5.0-job-ring", |
| "fsl,sec-v4.0-job-ring"; |
| reg = <0x10000 0x10000>; |
| interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| sec_jr1: jr@20000 { |
| compatible = "fsl,sec-v5.0-job-ring", |
| "fsl,sec-v4.0-job-ring"; |
| reg = <0x20000 0x10000>; |
| interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| sec_jr2: jr@30000 { |
| compatible = "fsl,sec-v5.0-job-ring", |
| "fsl,sec-v4.0-job-ring"; |
| reg = <0x30000 0x10000>; |
| interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| sec_jr3: jr@40000 { |
| compatible = "fsl,sec-v5.0-job-ring", |
| "fsl,sec-v4.0-job-ring"; |
| reg = <0x40000 0x10000>; |
| interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| }; |
| |
| fsl_mc: fsl-mc@80c000000 { |
| compatible = "fsl,qoriq-mc"; |
| reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ |
| <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ |
| msi-parent = <&its>; |
| #address-cells = <3>; |
| #size-cells = <1>; |
| |
| /* |
| * Region type 0x0 - MC portals |
| * Region type 0x1 - QBMAN portals |
| */ |
| ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 |
| 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; |
| |
| /* |
| * Define the maximum number of MACs present on the SoC. |
| */ |
| dpmacs { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| dpmac1: dpmac@1 { |
| compatible = "fsl,qoriq-mc-dpmac"; |
| reg = <0x1>; |
| }; |
| |
| dpmac2: dpmac@2 { |
| compatible = "fsl,qoriq-mc-dpmac"; |
| reg = <0x2>; |
| }; |
| |
| dpmac3: dpmac@3 { |
| compatible = "fsl,qoriq-mc-dpmac"; |
| reg = <0x3>; |
| }; |
| |
| dpmac4: dpmac@4 { |
| compatible = "fsl,qoriq-mc-dpmac"; |
| reg = <0x4>; |
| }; |
| |
| dpmac5: dpmac@5 { |
| compatible = "fsl,qoriq-mc-dpmac"; |
| reg = <0x5>; |
| }; |
| |
| dpmac6: dpmac@6 { |
| compatible = "fsl,qoriq-mc-dpmac"; |
| reg = <0x6>; |
| }; |
| |
| dpmac7: dpmac@7 { |
| compatible = "fsl,qoriq-mc-dpmac"; |
| reg = <0x7>; |
| }; |
| |
| dpmac8: dpmac@8 { |
| compatible = "fsl,qoriq-mc-dpmac"; |
| reg = <0x8>; |
| }; |
| |
| dpmac9: dpmac@9 { |
| compatible = "fsl,qoriq-mc-dpmac"; |
| reg = <0x9>; |
| }; |
| |
| dpmac10: dpmac@a { |
| compatible = "fsl,qoriq-mc-dpmac"; |
| reg = <0xa>; |
| }; |
| |
| dpmac11: dpmac@b { |
| compatible = "fsl,qoriq-mc-dpmac"; |
| reg = <0xb>; |
| }; |
| |
| dpmac12: dpmac@c { |
| compatible = "fsl,qoriq-mc-dpmac"; |
| reg = <0xc>; |
| }; |
| |
| dpmac13: dpmac@d { |
| compatible = "fsl,qoriq-mc-dpmac"; |
| reg = <0xd>; |
| }; |
| |
| dpmac14: dpmac@e { |
| compatible = "fsl,qoriq-mc-dpmac"; |
| reg = <0xe>; |
| }; |
| |
| dpmac15: dpmac@f { |
| compatible = "fsl,qoriq-mc-dpmac"; |
| reg = <0xf>; |
| }; |
| |
| dpmac16: dpmac@10 { |
| compatible = "fsl,qoriq-mc-dpmac"; |
| reg = <0x10>; |
| }; |
| }; |
| }; |
| |
| smmu: iommu@5000000 { |
| compatible = "arm,mmu-500"; |
| reg = <0 0x5000000 0 0x800000>; |
| #global-interrupts = <12>; |
| interrupts = <0 13 4>, /* global secure fault */ |
| <0 14 4>, /* combined secure interrupt */ |
| <0 15 4>, /* global non-secure fault */ |
| <0 16 4>, /* combined non-secure interrupt */ |
| /* performance counter interrupts 0-7 */ |
| <0 211 4>, <0 212 4>, |
| <0 213 4>, <0 214 4>, |
| <0 215 4>, <0 216 4>, |
| <0 217 4>, <0 218 4>, |
| /* per context interrupt, 64 interrupts */ |
| <0 146 4>, <0 147 4>, |
| <0 148 4>, <0 149 4>, |
| <0 150 4>, <0 151 4>, |
| <0 152 4>, <0 153 4>, |
| <0 154 4>, <0 155 4>, |
| <0 156 4>, <0 157 4>, |
| <0 158 4>, <0 159 4>, |
| <0 160 4>, <0 161 4>, |
| <0 162 4>, <0 163 4>, |
| <0 164 4>, <0 165 4>, |
| <0 166 4>, <0 167 4>, |
| <0 168 4>, <0 169 4>, |
| <0 170 4>, <0 171 4>, |
| <0 172 4>, <0 173 4>, |
| <0 174 4>, <0 175 4>, |
| <0 176 4>, <0 177 4>, |
| <0 178 4>, <0 179 4>, |
| <0 180 4>, <0 181 4>, |
| <0 182 4>, <0 183 4>, |
| <0 184 4>, <0 185 4>, |
| <0 186 4>, <0 187 4>, |
| <0 188 4>, <0 189 4>, |
| <0 190 4>, <0 191 4>, |
| <0 192 4>, <0 193 4>, |
| <0 194 4>, <0 195 4>, |
| <0 196 4>, <0 197 4>, |
| <0 198 4>, <0 199 4>, |
| <0 200 4>, <0 201 4>, |
| <0 202 4>, <0 203 4>, |
| <0 204 4>, <0 205 4>, |
| <0 206 4>, <0 207 4>, |
| <0 208 4>, <0 209 4>; |
| mmu-masters = <&fsl_mc 0x300 0>; |
| }; |
| |
| dspi: dspi@2100000 { |
| status = "disabled"; |
| compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x2100000 0x0 0x10000>; |
| interrupts = <0 26 0x4>; /* Level high type */ |
| clocks = <&clockgen 4 3>; |
| clock-names = "dspi"; |
| spi-num-chipselects = <5>; |
| bus-num = <0>; |
| }; |
| |
| esdhc: esdhc@2140000 { |
| status = "disabled"; |
| compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; |
| reg = <0x0 0x2140000 0x0 0x10000>; |
| interrupts = <0 28 0x4>; /* Level high type */ |
| clocks = <&clockgen 4 1>; |
| voltage-ranges = <1800 1800 3300 3300>; |
| sdhci,auto-cmd12; |
| little-endian; |
| bus-width = <4>; |
| }; |
| |
| gpio0: gpio@2300000 { |
| compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; |
| reg = <0x0 0x2300000 0x0 0x10000>; |
| interrupts = <0 36 0x4>; /* Level high type */ |
| gpio-controller; |
| little-endian; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gpio1: gpio@2310000 { |
| compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; |
| reg = <0x0 0x2310000 0x0 0x10000>; |
| interrupts = <0 36 0x4>; /* Level high type */ |
| gpio-controller; |
| little-endian; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gpio2: gpio@2320000 { |
| compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; |
| reg = <0x0 0x2320000 0x0 0x10000>; |
| interrupts = <0 37 0x4>; /* Level high type */ |
| gpio-controller; |
| little-endian; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| gpio3: gpio@2330000 { |
| compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; |
| reg = <0x0 0x2330000 0x0 0x10000>; |
| interrupts = <0 37 0x4>; /* Level high type */ |
| gpio-controller; |
| little-endian; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| i2c0: i2c@2000000 { |
| status = "disabled"; |
| compatible = "fsl,vf610-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x2000000 0x0 0x10000>; |
| interrupts = <0 34 0x4>; /* Level high type */ |
| clock-names = "i2c"; |
| clocks = <&clockgen 4 3>; |
| }; |
| |
| i2c1: i2c@2010000 { |
| status = "disabled"; |
| compatible = "fsl,vf610-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x2010000 0x0 0x10000>; |
| interrupts = <0 34 0x4>; /* Level high type */ |
| clock-names = "i2c"; |
| clocks = <&clockgen 4 3>; |
| }; |
| |
| i2c2: i2c@2020000 { |
| status = "disabled"; |
| compatible = "fsl,vf610-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x2020000 0x0 0x10000>; |
| interrupts = <0 35 0x4>; /* Level high type */ |
| clock-names = "i2c"; |
| clocks = <&clockgen 4 3>; |
| }; |
| |
| i2c3: i2c@2030000 { |
| status = "disabled"; |
| compatible = "fsl,vf610-i2c"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x2030000 0x0 0x10000>; |
| interrupts = <0 35 0x4>; /* Level high type */ |
| clock-names = "i2c"; |
| clocks = <&clockgen 4 3>; |
| }; |
| |
| ifc: ifc@2240000 { |
| compatible = "fsl,ifc", "simple-bus"; |
| reg = <0x0 0x2240000 0x0 0x20000>; |
| interrupts = <0 21 0x4>; /* Level high type */ |
| little-endian; |
| #address-cells = <2>; |
| #size-cells = <1>; |
| |
| ranges = <0 0 0x5 0x80000000 0x08000000 |
| 2 0 0x5 0x30000000 0x00010000 |
| 3 0 0x5 0x20000000 0x00010000>; |
| }; |
| |
| qspi: quadspi@20c0000 { |
| status = "disabled"; |
| compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x0 0x20c0000 0x0 0x10000>, |
| <0x0 0x20000000 0x0 0x10000000>; |
| reg-names = "QuadSPI", "QuadSPI-memory"; |
| interrupts = <0 25 0x4>; /* Level high type */ |
| clocks = <&clockgen 4 3>, <&clockgen 4 3>; |
| clock-names = "qspi_en", "qspi"; |
| }; |
| |
| pcie1: pcie@3400000 { |
| compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", |
| "snps,dw-pcie"; |
| reg-names = "regs", "config"; |
| interrupts = <0 108 0x4>; /* Level high type */ |
| interrupt-names = "intr"; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| device_type = "pci"; |
| dma-coherent; |
| num-lanes = <4>; |
| bus-range = <0x0 0xff>; |
| msi-parent = <&its>; |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 7>; |
| interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>, |
| <0000 0 0 2 &gic 0 0 0 110 4>, |
| <0000 0 0 3 &gic 0 0 0 111 4>, |
| <0000 0 0 4 &gic 0 0 0 112 4>; |
| }; |
| |
| pcie2: pcie@3500000 { |
| compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", |
| "snps,dw-pcie"; |
| reg-names = "regs", "config"; |
| interrupts = <0 113 0x4>; /* Level high type */ |
| interrupt-names = "intr"; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| device_type = "pci"; |
| dma-coherent; |
| num-lanes = <4>; |
| bus-range = <0x0 0xff>; |
| msi-parent = <&its>; |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 7>; |
| interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>, |
| <0000 0 0 2 &gic 0 0 0 115 4>, |
| <0000 0 0 3 &gic 0 0 0 116 4>, |
| <0000 0 0 4 &gic 0 0 0 117 4>; |
| }; |
| |
| pcie3: pcie@3600000 { |
| compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", |
| "snps,dw-pcie"; |
| reg-names = "regs", "config"; |
| interrupts = <0 118 0x4>; /* Level high type */ |
| interrupt-names = "intr"; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| device_type = "pci"; |
| dma-coherent; |
| num-lanes = <8>; |
| bus-range = <0x0 0xff>; |
| msi-parent = <&its>; |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 7>; |
| interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>, |
| <0000 0 0 2 &gic 0 0 0 120 4>, |
| <0000 0 0 3 &gic 0 0 0 121 4>, |
| <0000 0 0 4 &gic 0 0 0 122 4>; |
| }; |
| |
| pcie4: pcie@3700000 { |
| compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", |
| "snps,dw-pcie"; |
| reg-names = "regs", "config"; |
| interrupts = <0 123 0x4>; /* Level high type */ |
| interrupt-names = "intr"; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| device_type = "pci"; |
| dma-coherent; |
| num-lanes = <4>; |
| bus-range = <0x0 0xff>; |
| msi-parent = <&its>; |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 7>; |
| interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>, |
| <0000 0 0 2 &gic 0 0 0 125 4>, |
| <0000 0 0 3 &gic 0 0 0 126 4>, |
| <0000 0 0 4 &gic 0 0 0 127 4>; |
| }; |
| |
| sata0: sata@3200000 { |
| status = "disabled"; |
| compatible = "fsl,ls2080a-ahci"; |
| reg = <0x0 0x3200000 0x0 0x10000>; |
| interrupts = <0 133 0x4>; /* Level high type */ |
| clocks = <&clockgen 4 3>; |
| dma-coherent; |
| }; |
| |
| sata1: sata@3210000 { |
| status = "disabled"; |
| compatible = "fsl,ls2080a-ahci"; |
| reg = <0x0 0x3210000 0x0 0x10000>; |
| interrupts = <0 136 0x4>; /* Level high type */ |
| clocks = <&clockgen 4 3>; |
| dma-coherent; |
| }; |
| |
| usb0: usb3@3100000 { |
| status = "disabled"; |
| compatible = "snps,dwc3"; |
| reg = <0x0 0x3100000 0x0 0x10000>; |
| interrupts = <0 80 0x4>; /* Level high type */ |
| dr_mode = "host"; |
| snps,quirk-frame-length-adjustment = <0x20>; |
| snps,dis_rxdet_inp3_quirk; |
| }; |
| |
| usb1: usb3@3110000 { |
| status = "disabled"; |
| compatible = "snps,dwc3"; |
| reg = <0x0 0x3110000 0x0 0x10000>; |
| interrupts = <0 81 0x4>; /* Level high type */ |
| dr_mode = "host"; |
| snps,quirk-frame-length-adjustment = <0x20>; |
| snps,dis_rxdet_inp3_quirk; |
| }; |
| |
| ccn@4000000 { |
| compatible = "arm,ccn-504"; |
| reg = <0x0 0x04000000 0x0 0x01000000>; |
| interrupts = <0 12 4>; |
| }; |
| }; |
| |
| ddr1: memory-controller@1080000 { |
| compatible = "fsl,qoriq-memory-controller"; |
| reg = <0x0 0x1080000 0x0 0x1000>; |
| interrupts = <0 17 0x4>; |
| little-endian; |
| }; |
| |
| ddr2: memory-controller@1090000 { |
| compatible = "fsl,qoriq-memory-controller"; |
| reg = <0x0 0x1090000 0x0 0x1000>; |
| interrupts = <0 18 0x4>; |
| little-endian; |
| }; |
| |
| firmware { |
| optee { |
| compatible = "linaro,optee-tz"; |
| method = "smc"; |
| }; |
| }; |
| }; |
