[ | |
{ | |
"ArchStdEvent": "L1D_CACHE_RD", | |
}, | |
{ | |
"ArchStdEvent": "L1D_CACHE_WR", | |
}, | |
{ | |
"ArchStdEvent": "L1D_CACHE_REFILL_RD", | |
}, | |
{ | |
"ArchStdEvent": "L1D_CACHE_REFILL_WR", | |
}, | |
{ | |
"ArchStdEvent": "L1D_TLB_REFILL_RD", | |
}, | |
{ | |
"ArchStdEvent": "L1D_TLB_REFILL_WR", | |
}, | |
{ | |
"ArchStdEvent": "L1D_TLB_RD", | |
}, | |
{ | |
"ArchStdEvent": "L1D_TLB_WR", | |
}, | |
{ | |
"ArchStdEvent": "BUS_ACCESS_RD", | |
}, | |
{ | |
"ArchStdEvent": "BUS_ACCESS_WR", | |
} | |
] |