| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Device Tree Source for the r8a77980 SoC |
| * |
| * Copyright (C) 2018 Renesas Electronics Corp. |
| * Copyright (C) 2018 Cogent Embedded, Inc. |
| */ |
| |
| #include <dt-bindings/clock/r8a77980-cpg-mssr.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/power/r8a77980-sysc.h> |
| |
| / { |
| compatible = "renesas,r8a77980"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| aliases { |
| i2c0 = &i2c0; |
| i2c1 = &i2c1; |
| i2c2 = &i2c2; |
| i2c3 = &i2c3; |
| i2c4 = &i2c4; |
| i2c5 = &i2c5; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| a53_0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| reg = <0>; |
| clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; |
| power-domains = <&sysc R8A77980_PD_CA53_CPU0>; |
| next-level-cache = <&L2_CA53>; |
| enable-method = "psci"; |
| }; |
| |
| a53_1: cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| reg = <1>; |
| clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; |
| power-domains = <&sysc R8A77980_PD_CA53_CPU1>; |
| next-level-cache = <&L2_CA53>; |
| enable-method = "psci"; |
| }; |
| |
| a53_2: cpu@2 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| reg = <2>; |
| clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; |
| power-domains = <&sysc R8A77980_PD_CA53_CPU2>; |
| next-level-cache = <&L2_CA53>; |
| enable-method = "psci"; |
| }; |
| |
| a53_3: cpu@3 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a53", "arm,armv8"; |
| reg = <3>; |
| clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; |
| power-domains = <&sysc R8A77980_PD_CA53_CPU3>; |
| next-level-cache = <&L2_CA53>; |
| enable-method = "psci"; |
| }; |
| |
| L2_CA53: cache-controller { |
| compatible = "cache"; |
| power-domains = <&sysc R8A77980_PD_CA53_SCU>; |
| cache-unified; |
| cache-level = <2>; |
| }; |
| }; |
| |
| /* External CAN clock - to be overridden by boards that provide it */ |
| can_clk: can { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <0>; |
| }; |
| |
| extal_clk: extal { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| /* This value must be overridden by the board */ |
| clock-frequency = <0>; |
| }; |
| |
| extalr_clk: extalr { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| /* This value must be overridden by the board */ |
| clock-frequency = <0>; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0", "arm,psci-0.2"; |
| method = "smc"; |
| }; |
| |
| /* External SCIF clock - to be overridden by boards that provide it */ |
| scif_clk: scif { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <0>; |
| }; |
| |
| soc { |
| compatible = "simple-bus"; |
| interrupt-parent = <&gic>; |
| |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| gpio0: gpio@e6050000 { |
| compatible = "renesas,gpio-r8a77980", |
| "renesas,rcar-gen3-gpio"; |
| reg = <0 0xe6050000 0 0x50>; |
| interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 0 22>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 912>; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| resets = <&cpg 912>; |
| }; |
| |
| gpio1: gpio@e6051000 { |
| compatible = "renesas,gpio-r8a77980", |
| "renesas,rcar-gen3-gpio"; |
| reg = <0 0xe6051000 0 0x50>; |
| interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 32 28>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 911>; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| resets = <&cpg 911>; |
| }; |
| |
| gpio2: gpio@e6052000 { |
| compatible = "renesas,gpio-r8a77980", |
| "renesas,rcar-gen3-gpio"; |
| reg = <0 0xe6052000 0 0x50>; |
| interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 64 30>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 910>; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| resets = <&cpg 910>; |
| }; |
| |
| gpio3: gpio@e6053000 { |
| compatible = "renesas,gpio-r8a77980", |
| "renesas,rcar-gen3-gpio"; |
| reg = <0 0xe6053000 0 0x50>; |
| interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 96 17>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 909>; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| resets = <&cpg 909>; |
| }; |
| |
| gpio4: gpio@e6054000 { |
| compatible = "renesas,gpio-r8a77980", |
| "renesas,rcar-gen3-gpio"; |
| reg = <0 0xe6054000 0 0x50>; |
| interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 128 25>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 908>; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| resets = <&cpg 908>; |
| }; |
| |
| gpio5: gpio@e6055000 { |
| compatible = "renesas,gpio-r8a77980", |
| "renesas,rcar-gen3-gpio"; |
| reg = <0 0xe6055000 0 0x50>; |
| interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 160 15>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&cpg CPG_MOD 907>; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| resets = <&cpg 907>; |
| }; |
| |
| pfc: pin-controller@e6060000 { |
| compatible = "renesas,pfc-r8a77980"; |
| reg = <0 0xe6060000 0 0x50c>; |
| }; |
| |
| cpg: clock-controller@e6150000 { |
| compatible = "renesas,r8a77980-cpg-mssr"; |
| reg = <0 0xe6150000 0 0x1000>; |
| clocks = <&extal_clk>, <&extalr_clk>; |
| clock-names = "extal", "extalr"; |
| #clock-cells = <2>; |
| #power-domain-cells = <0>; |
| #reset-cells = <1>; |
| }; |
| |
| rst: reset-controller@e6160000 { |
| compatible = "renesas,r8a77980-rst"; |
| reg = <0 0xe6160000 0 0x200>; |
| }; |
| |
| sysc: system-controller@e6180000 { |
| compatible = "renesas,r8a77980-sysc"; |
| reg = <0 0xe6180000 0 0x440>; |
| #power-domain-cells = <1>; |
| }; |
| |
| intc_ex: interrupt-controller@e61c0000 { |
| compatible = "renesas,intc-ex-r8a77980", "renesas,irqc"; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| reg = <0 0xe61c0000 0 0x200>; |
| interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 407>; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| resets = <&cpg 407>; |
| }; |
| |
| i2c0: i2c@e6500000 { |
| compatible = "renesas,i2c-r8a77980", |
| "renesas,rcar-gen3-i2c"; |
| reg = <0 0xe6500000 0 0x40>; |
| interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 931>; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| resets = <&cpg 931>; |
| dmas = <&dmac1 0x91>, <&dmac1 0x90>, |
| <&dmac2 0x91>, <&dmac2 0x90>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| i2c-scl-internal-delay-ns = <6>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@e6508000 { |
| compatible = "renesas,i2c-r8a77980", |
| "renesas,rcar-gen3-i2c"; |
| reg = <0 0xe6508000 0 0x40>; |
| interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 930>; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| resets = <&cpg 930>; |
| dmas = <&dmac1 0x93>, <&dmac1 0x92>, |
| <&dmac2 0x93>, <&dmac2 0x92>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| i2c-scl-internal-delay-ns = <6>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@e6510000 { |
| compatible = "renesas,i2c-r8a77980", |
| "renesas,rcar-gen3-i2c"; |
| reg = <0 0xe6510000 0 0x40>; |
| interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 929>; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| resets = <&cpg 929>; |
| dmas = <&dmac1 0x95>, <&dmac1 0x94>, |
| <&dmac2 0x95>, <&dmac2 0x94>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| i2c-scl-internal-delay-ns = <6>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@e66d0000 { |
| compatible = "renesas,i2c-r8a77980", |
| "renesas,rcar-gen3-i2c"; |
| reg = <0 0xe66d0000 0 0x40>; |
| interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 928>; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| resets = <&cpg 928>; |
| i2c-scl-internal-delay-ns = <6>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@e66d8000 { |
| compatible = "renesas,i2c-r8a77980", |
| "renesas,rcar-gen3-i2c"; |
| reg = <0 0xe66d8000 0 0x40>; |
| interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 927>; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| resets = <&cpg 927>; |
| i2c-scl-internal-delay-ns = <6>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c5: i2c@e66e0000 { |
| compatible = "renesas,i2c-r8a77980", |
| "renesas,rcar-gen3-i2c"; |
| reg = <0 0xe66e0000 0 0x40>; |
| interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 919>; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| resets = <&cpg 919>; |
| dmas = <&dmac1 0x9b>, <&dmac1 0x9a>, |
| <&dmac2 0x9b>, <&dmac2 0x9a>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| i2c-scl-internal-delay-ns = <6>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| hscif0: serial@e6540000 { |
| compatible = "renesas,hscif-r8a77980", |
| "renesas,rcar-gen3-hscif", |
| "renesas,hscif"; |
| reg = <0 0xe6540000 0 0x60>; |
| interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 520>, |
| <&cpg CPG_CORE R8A77980_CLK_S3D1>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac1 0x31>, <&dmac1 0x30>, |
| <&dmac2 0x31>, <&dmac2 0x30>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| resets = <&cpg 520>; |
| status = "disabled"; |
| }; |
| |
| hscif1: serial@e6550000 { |
| compatible = "renesas,hscif-r8a77980", |
| "renesas,rcar-gen3-hscif", |
| "renesas,hscif"; |
| reg = <0 0xe6550000 0 0x60>; |
| interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 519>, |
| <&cpg CPG_CORE R8A77980_CLK_S3D1>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac1 0x33>, <&dmac1 0x32>, |
| <&dmac2 0x33>, <&dmac2 0x32>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| resets = <&cpg 519>; |
| status = "disabled"; |
| }; |
| |
| hscif2: serial@e6560000 { |
| compatible = "renesas,hscif-r8a77980", |
| "renesas,rcar-gen3-hscif", |
| "renesas,hscif"; |
| reg = <0 0xe6560000 0 0x60>; |
| interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 518>, |
| <&cpg CPG_CORE R8A77980_CLK_S3D1>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac1 0x35>, <&dmac1 0x34>, |
| <&dmac2 0x35>, <&dmac2 0x34>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| resets = <&cpg 518>; |
| status = "disabled"; |
| }; |
| |
| hscif3: serial@e66a0000 { |
| compatible = "renesas,hscif-r8a77980", |
| "renesas,rcar-gen3-hscif", |
| "renesas,hscif"; |
| reg = <0 0xe66a0000 0 0x60>; |
| interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 517>, |
| <&cpg CPG_CORE R8A77980_CLK_S3D1>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac1 0x37>, <&dmac1 0x36>, |
| <&dmac2 0x37>, <&dmac2 0x36>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| resets = <&cpg 517>; |
| status = "disabled"; |
| }; |
| |
| canfd: can@e66c0000 { |
| compatible = "renesas,r8a77980-canfd", |
| "renesas,rcar-gen3-canfd"; |
| reg = <0 0xe66c0000 0 0x8000>; |
| interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 914>, |
| <&cpg CPG_CORE R8A77980_CLK_CANFD>, |
| <&can_clk>; |
| clock-names = "fck", "canfd", "can_clk"; |
| assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>; |
| assigned-clock-rates = <40000000>; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| resets = <&cpg 914>; |
| status = "disabled"; |
| |
| channel0 { |
| status = "disabled"; |
| }; |
| |
| channel1 { |
| status = "disabled"; |
| }; |
| }; |
| |
| ipmmu_ds1: mmu@e7740000 { |
| compatible = "renesas,ipmmu-r8a77980"; |
| reg = <0 0xe7740000 0 0x1000>; |
| renesas,ipmmu-main = <&ipmmu_mm 0>; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| #iommu-cells = <1>; |
| }; |
| |
| ipmmu_vip0: mmu@e7b00000 { |
| compatible = "renesas,ipmmu-r8a77980"; |
| reg = <0 0xe7b00000 0 0x1000>; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| #iommu-cells = <1>; |
| }; |
| |
| ipmmu_vip1: mmu@e7960000 { |
| compatible = "renesas,ipmmu-r8a77980"; |
| reg = <0 0xe7960000 0 0x1000>; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| #iommu-cells = <1>; |
| }; |
| |
| ipmmu_ir: mmu@ff8b0000 { |
| compatible = "renesas,ipmmu-r8a77980"; |
| reg = <0 0xff8b0000 0 0x1000>; |
| renesas,ipmmu-main = <&ipmmu_mm 3>; |
| power-domains = <&sysc R8A77980_PD_A3IR>; |
| #iommu-cells = <1>; |
| }; |
| |
| ipmmu_mm: mmu@e67b0000 { |
| compatible = "renesas,ipmmu-r8a77980"; |
| reg = <0 0xe67b0000 0 0x1000>; |
| interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| #iommu-cells = <1>; |
| }; |
| |
| ipmmu_rt: mmu@ffc80000 { |
| compatible = "renesas,ipmmu-r8a77980"; |
| reg = <0 0xffc80000 0 0x1000>; |
| renesas,ipmmu-main = <&ipmmu_mm 10>; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| #iommu-cells = <1>; |
| }; |
| |
| ipmmu_vc0: mmu@fe6b0000 { |
| compatible = "renesas,ipmmu-r8a77980"; |
| reg = <0 0xfe6b0000 0 0x1000>; |
| renesas,ipmmu-main = <&ipmmu_mm 12>; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| #iommu-cells = <1>; |
| }; |
| |
| ipmmu_vi0: mmu@febd0000 { |
| compatible = "renesas,ipmmu-r8a77980"; |
| reg = <0 0xfebd0000 0 0x1000>; |
| renesas,ipmmu-main = <&ipmmu_mm 14>; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| #iommu-cells = <1>; |
| }; |
| |
| avb: ethernet@e6800000 { |
| compatible = "renesas,etheravb-r8a77980", |
| "renesas,etheravb-rcar-gen3"; |
| reg = <0 0xe6800000 0 0x800>; |
| interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "ch0", "ch1", "ch2", "ch3", |
| "ch4", "ch5", "ch6", "ch7", |
| "ch8", "ch9", "ch10", "ch11", |
| "ch12", "ch13", "ch14", "ch15", |
| "ch16", "ch17", "ch18", "ch19", |
| "ch20", "ch21", "ch22", "ch23", |
| "ch24"; |
| clocks = <&cpg CPG_MOD 812>; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| resets = <&cpg 812>; |
| phy-mode = "rgmii"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| scif0: serial@e6e60000 { |
| compatible = "renesas,scif-r8a77980", |
| "renesas,rcar-gen3-scif", |
| "renesas,scif"; |
| reg = <0 0xe6e60000 0 0x40>; |
| interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 207>, |
| <&cpg CPG_CORE R8A77980_CLK_S3D1>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac1 0x51>, <&dmac1 0x50>, |
| <&dmac2 0x51>, <&dmac2 0x50>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| resets = <&cpg 207>; |
| status = "disabled"; |
| }; |
| |
| scif1: serial@e6e68000 { |
| compatible = "renesas,scif-r8a77980", |
| "renesas,rcar-gen3-scif", |
| "renesas,scif"; |
| reg = <0 0xe6e68000 0 0x40>; |
| interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 206>, |
| <&cpg CPG_CORE R8A77980_CLK_S3D1>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac1 0x53>, <&dmac1 0x52>, |
| <&dmac2 0x53>, <&dmac2 0x52>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| resets = <&cpg 206>; |
| status = "disabled"; |
| }; |
| |
| scif3: serial@e6c50000 { |
| compatible = "renesas,scif-r8a77980", |
| "renesas,rcar-gen3-scif", |
| "renesas,scif"; |
| reg = <0 0xe6c50000 0 0x40>; |
| interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 204>, |
| <&cpg CPG_CORE R8A77980_CLK_S3D1>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac1 0x57>, <&dmac1 0x56>, |
| <&dmac2 0x57>, <&dmac2 0x56>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| resets = <&cpg 204>; |
| status = "disabled"; |
| }; |
| |
| scif4: serial@e6c40000 { |
| compatible = "renesas,scif-r8a77980", |
| "renesas,rcar-gen3-scif", |
| "renesas,scif"; |
| reg = <0 0xe6c40000 0 0x40>; |
| interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 203>, |
| <&cpg CPG_CORE R8A77980_CLK_S3D1>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac1 0x59>, <&dmac1 0x58>, |
| <&dmac2 0x59>, <&dmac2 0x58>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| resets = <&cpg 203>; |
| status = "disabled"; |
| }; |
| |
| dmac1: dma-controller@e7300000 { |
| compatible = "renesas,dmac-r8a77980", |
| "renesas,rcar-dmac"; |
| reg = <0 0xe7300000 0 0x10000>; |
| interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "error", |
| "ch0", "ch1", "ch2", "ch3", |
| "ch4", "ch5", "ch6", "ch7", |
| "ch8", "ch9", "ch10", "ch11", |
| "ch12", "ch13", "ch14", "ch15"; |
| clocks = <&cpg CPG_MOD 218>; |
| clock-names = "fck"; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| resets = <&cpg 218>; |
| #dma-cells = <1>; |
| dma-channels = <16>; |
| }; |
| |
| dmac2: dma-controller@e7310000 { |
| compatible = "renesas,dmac-r8a77980", |
| "renesas,rcar-dmac"; |
| reg = <0 0xe7310000 0 0x10000>; |
| interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "error", |
| "ch0", "ch1", "ch2", "ch3", |
| "ch4", "ch5", "ch6", "ch7", |
| "ch8", "ch9", "ch10", "ch11", |
| "ch12", "ch13", "ch14", "ch15"; |
| clocks = <&cpg CPG_MOD 217>; |
| clock-names = "fck"; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| resets = <&cpg 217>; |
| #dma-cells = <1>; |
| dma-channels = <16>; |
| }; |
| |
| gether: ethernet@e7400000 { |
| compatible = "renesas,gether-r8a77980"; |
| reg = <0 0xe7400000 0 0x1000>; |
| interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 813>; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| resets = <&cpg 813>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| mmc0: mmc@ee140000 { |
| compatible = "renesas,sdhi-r8a77980", |
| "renesas,rcar-gen3-sdhi"; |
| reg = <0 0xee140000 0 0x2000>; |
| interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 314>; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| resets = <&cpg 314>; |
| max-frequency = <200000000>; |
| status = "disabled"; |
| }; |
| |
| gic: interrupt-controller@f1010000 { |
| compatible = "arm,gic-400"; |
| #interrupt-cells = <3>; |
| #address-cells = <0>; |
| interrupt-controller; |
| reg = <0x0 0xf1010000 0 0x1000>, |
| <0x0 0xf1020000 0 0x20000>, |
| <0x0 0xf1040000 0 0x20000>, |
| <0x0 0xf1060000 0 0x20000>; |
| interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | |
| IRQ_TYPE_LEVEL_HIGH)>; |
| clocks = <&cpg CPG_MOD 408>; |
| clock-names = "clk"; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| resets = <&cpg 408>; |
| }; |
| |
| vspd0: vsp@fea20000 { |
| compatible = "renesas,vsp2"; |
| reg = <0 0xfea20000 0 0x5000>; |
| interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 623>; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| resets = <&cpg 623>; |
| renesas,fcp = <&fcpvd0>; |
| }; |
| |
| fcpvd0: fcp@fea27000 { |
| compatible = "renesas,fcpv"; |
| reg = <0 0xfea27000 0 0x200>; |
| clocks = <&cpg CPG_MOD 603>; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| resets = <&cpg 603>; |
| }; |
| |
| du: display@feb00000 { |
| compatible = "renesas,du-r8a77980", |
| "renesas,du-r8a77970"; |
| reg = <0 0xfeb00000 0 0x80000>; |
| interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&cpg CPG_MOD 724>; |
| clock-names = "du.0"; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| resets = <&cpg 724>; |
| vsps = <&vspd0>; |
| status = "disabled"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| du_out_rgb: endpoint { |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| du_out_lvds0: endpoint { |
| remote-endpoint = <&lvds0_in>; |
| }; |
| }; |
| }; |
| }; |
| |
| lvds0: lvds-encoder@feb90000 { |
| compatible = "renesas,r8a77980-lvds"; |
| reg = <0 0xfeb90000 0 0x14>; |
| clocks = <&cpg CPG_MOD 727>; |
| power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; |
| resets = <&cpg 727>; |
| status = "disabled"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| lvds0_in: endpoint { |
| remote-endpoint = |
| <&du_out_lvds0>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| lvds0_out: endpoint { |
| }; |
| }; |
| }; |
| }; |
| |
| prr: chipid@fff00044 { |
| compatible = "renesas,prr"; |
| reg = <0 0xfff00044 0 4>; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | |
| IRQ_TYPE_LEVEL_LOW)>, |
| <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | |
| IRQ_TYPE_LEVEL_LOW)>, |
| <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | |
| IRQ_TYPE_LEVEL_LOW)>, |
| <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | |
| IRQ_TYPE_LEVEL_LOW)>; |
| }; |
| }; |
