| /* |
| * Device Tree Source for AMCC Glacier (460GT) |
| * |
| * Copyright 2008-2010 DENX Software Engineering, Stefan Roese <sr@denx.de> |
| * |
| * This file is licensed under the terms of the GNU General Public |
| * License version 2. This program is licensed "as is" without |
| * any warranty of any kind, whether express or implied. |
| */ |
| |
| /dts-v1/; |
| |
| / { |
| #address-cells = <2>; |
| #size-cells = <1>; |
| model = "amcc,glacier"; |
| compatible = "amcc,glacier"; |
| dcr-parent = <&{/cpus/cpu@0}>; |
| |
| aliases { |
| ethernet0 = &EMAC0; |
| ethernet1 = &EMAC1; |
| ethernet2 = &EMAC2; |
| ethernet3 = &EMAC3; |
| serial0 = &UART0; |
| serial1 = &UART1; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| device_type = "cpu"; |
| model = "PowerPC,460GT"; |
| reg = <0x00000000>; |
| clock-frequency = <0>; /* Filled in by U-Boot */ |
| timebase-frequency = <0>; /* Filled in by U-Boot */ |
| i-cache-line-size = <32>; |
| d-cache-line-size = <32>; |
| i-cache-size = <32768>; |
| d-cache-size = <32768>; |
| dcr-controller; |
| dcr-access-method = "native"; |
| next-level-cache = <&L2C0>; |
| }; |
| }; |
| |
| memory { |
| device_type = "memory"; |
| reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */ |
| }; |
| |
| UIC0: interrupt-controller0 { |
| compatible = "ibm,uic-460gt","ibm,uic"; |
| interrupt-controller; |
| cell-index = <0>; |
| dcr-reg = <0x0c0 0x009>; |
| #address-cells = <0>; |
| #size-cells = <0>; |
| #interrupt-cells = <2>; |
| }; |
| |
| UIC1: interrupt-controller1 { |
| compatible = "ibm,uic-460gt","ibm,uic"; |
| interrupt-controller; |
| cell-index = <1>; |
| dcr-reg = <0x0d0 0x009>; |
| #address-cells = <0>; |
| #size-cells = <0>; |
| #interrupt-cells = <2>; |
| interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */ |
| interrupt-parent = <&UIC0>; |
| }; |
| |
| UIC2: interrupt-controller2 { |
| compatible = "ibm,uic-460gt","ibm,uic"; |
| interrupt-controller; |
| cell-index = <2>; |
| dcr-reg = <0x0e0 0x009>; |
| #address-cells = <0>; |
| #size-cells = <0>; |
| #interrupt-cells = <2>; |
| interrupts = <0xa 0x4 0xb 0x4>; /* cascade */ |
| interrupt-parent = <&UIC0>; |
| }; |
| |
| UIC3: interrupt-controller3 { |
| compatible = "ibm,uic-460gt","ibm,uic"; |
| interrupt-controller; |
| cell-index = <3>; |
| dcr-reg = <0x0f0 0x009>; |
| #address-cells = <0>; |
| #size-cells = <0>; |
| #interrupt-cells = <2>; |
| interrupts = <0x10 0x4 0x11 0x4>; /* cascade */ |
| interrupt-parent = <&UIC0>; |
| }; |
| |
| SDR0: sdr { |
| compatible = "ibm,sdr-460gt"; |
| dcr-reg = <0x00e 0x002>; |
| }; |
| |
| CPR0: cpr { |
| compatible = "ibm,cpr-460gt"; |
| dcr-reg = <0x00c 0x002>; |
| }; |
| |
| L2C0: l2c { |
| compatible = "ibm,l2-cache-460gt", "ibm,l2-cache"; |
| dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */ |
| 0x030 0x008>; /* L2 cache DCR's */ |
| cache-line-size = <32>; /* 32 bytes */ |
| cache-size = <262144>; /* L2, 256K */ |
| interrupt-parent = <&UIC1>; |
| interrupts = <11 1>; |
| }; |
| |
| plb { |
| compatible = "ibm,plb-460gt", "ibm,plb4"; |
| #address-cells = <2>; |
| #size-cells = <1>; |
| ranges; |
| clock-frequency = <0>; /* Filled in by U-Boot */ |
| |
| SDRAM0: sdram { |
| compatible = "ibm,sdram-460gt", "ibm,sdram-405gp"; |
| dcr-reg = <0x010 0x002>; |
| }; |
| |
| CRYPTO: crypto@180000 { |
| compatible = "amcc,ppc460gt-crypto", "amcc,ppc460ex-crypto", |
| "amcc,ppc4xx-crypto"; |
| reg = <4 0x00180000 0x80400>; |
| interrupt-parent = <&UIC0>; |
| interrupts = <0x1d 0x4>; |
| }; |
| |
| HWRNG: hwrng@110000 { |
| compatible = "amcc,ppc460ex-rng", "ppc4xx-rng"; |
| reg = <4 0x00110000 0x50>; |
| }; |
| |
| MAL0: mcmal { |
| compatible = "ibm,mcmal-460gt", "ibm,mcmal2"; |
| dcr-reg = <0x180 0x062>; |
| num-tx-chans = <4>; |
| num-rx-chans = <32>; |
| #address-cells = <0>; |
| #size-cells = <0>; |
| interrupt-parent = <&UIC2>; |
| interrupts = < /*TXEOB*/ 0x6 0x4 |
| /*RXEOB*/ 0x7 0x4 |
| /*SERR*/ 0x3 0x4 |
| /*TXDE*/ 0x4 0x4 |
| /*RXDE*/ 0x5 0x4>; |
| desc-base-addr-high = <0x8>; |
| }; |
| |
| POB0: opb { |
| compatible = "ibm,opb-460gt", "ibm,opb"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>; |
| clock-frequency = <0>; /* Filled in by U-Boot */ |
| |
| EBC0: ebc { |
| compatible = "ibm,ebc-460gt", "ibm,ebc"; |
| dcr-reg = <0x012 0x002>; |
| #address-cells = <2>; |
| #size-cells = <1>; |
| clock-frequency = <0>; /* Filled in by U-Boot */ |
| /* ranges property is supplied by U-Boot */ |
| interrupts = <0x6 0x4>; |
| interrupt-parent = <&UIC1>; |
| |
| nor_flash@0,0 { |
| compatible = "amd,s29gl512n", "cfi-flash"; |
| bank-width = <2>; |
| reg = <0x00000000 0x00000000 0x04000000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| partition@0 { |
| label = "kernel"; |
| reg = <0x00000000 0x001e0000>; |
| }; |
| partition@1e0000 { |
| label = "dtb"; |
| reg = <0x001e0000 0x00020000>; |
| }; |
| partition@200000 { |
| label = "ramdisk"; |
| reg = <0x00200000 0x01400000>; |
| }; |
| partition@1600000 { |
| label = "jffs2"; |
| reg = <0x01600000 0x00400000>; |
| }; |
| partition@1a00000 { |
| label = "user"; |
| reg = <0x01a00000 0x02560000>; |
| }; |
| partition@3f60000 { |
| label = "env"; |
| reg = <0x03f60000 0x00040000>; |
| }; |
| partition@3fa0000 { |
| label = "u-boot"; |
| reg = <0x03fa0000 0x00060000>; |
| }; |
| }; |
| |
| ndfc@3,0 { |
| compatible = "ibm,ndfc"; |
| reg = <0x00000003 0x00000000 0x00002000>; |
| ccr = <0x00001000>; |
| bank-settings = <0x80002222>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| nand { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| partition@0 { |
| label = "u-boot"; |
| reg = <0x00000000 0x00100000>; |
| }; |
| partition@100000 { |
| label = "user"; |
| reg = <0x00000000 0x03f00000>; |
| }; |
| }; |
| }; |
| }; |
| |
| UART0: serial@ef600300 { |
| device_type = "serial"; |
| compatible = "ns16550"; |
| reg = <0xef600300 0x00000008>; |
| virtual-reg = <0xef600300>; |
| clock-frequency = <0>; /* Filled in by U-Boot */ |
| current-speed = <0>; /* Filled in by U-Boot */ |
| interrupt-parent = <&UIC1>; |
| interrupts = <0x1 0x4>; |
| }; |
| |
| UART1: serial@ef600400 { |
| device_type = "serial"; |
| compatible = "ns16550"; |
| reg = <0xef600400 0x00000008>; |
| virtual-reg = <0xef600400>; |
| clock-frequency = <0>; /* Filled in by U-Boot */ |
| current-speed = <0>; /* Filled in by U-Boot */ |
| interrupt-parent = <&UIC0>; |
| interrupts = <0x1 0x4>; |
| }; |
| |
| UART2: serial@ef600500 { |
| device_type = "serial"; |
| compatible = "ns16550"; |
| reg = <0xef600500 0x00000008>; |
| virtual-reg = <0xef600500>; |
| clock-frequency = <0>; /* Filled in by U-Boot */ |
| current-speed = <0>; /* Filled in by U-Boot */ |
| interrupt-parent = <&UIC1>; |
| interrupts = <28 0x4>; |
| }; |
| |
| UART3: serial@ef600600 { |
| device_type = "serial"; |
| compatible = "ns16550"; |
| reg = <0xef600600 0x00000008>; |
| virtual-reg = <0xef600600>; |
| clock-frequency = <0>; /* Filled in by U-Boot */ |
| current-speed = <0>; /* Filled in by U-Boot */ |
| interrupt-parent = <&UIC1>; |
| interrupts = <29 0x4>; |
| }; |
| |
| IIC0: i2c@ef600700 { |
| compatible = "ibm,iic-460gt", "ibm,iic"; |
| reg = <0xef600700 0x00000014>; |
| interrupt-parent = <&UIC0>; |
| interrupts = <0x2 0x4>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| rtc@68 { |
| compatible = "st,m41t80"; |
| reg = <0x68>; |
| interrupt-parent = <&UIC2>; |
| interrupts = <0x19 0x8>; |
| }; |
| sttm@48 { |
| compatible = "ad,ad7414"; |
| reg = <0x48>; |
| interrupt-parent = <&UIC1>; |
| interrupts = <0x14 0x8>; |
| }; |
| }; |
| |
| IIC1: i2c@ef600800 { |
| compatible = "ibm,iic-460gt", "ibm,iic"; |
| reg = <0xef600800 0x00000014>; |
| interrupt-parent = <&UIC0>; |
| interrupts = <0x3 0x4>; |
| }; |
| |
| ZMII0: emac-zmii@ef600d00 { |
| compatible = "ibm,zmii-460gt", "ibm,zmii"; |
| reg = <0xef600d00 0x0000000c>; |
| }; |
| |
| RGMII0: emac-rgmii@ef601500 { |
| compatible = "ibm,rgmii-460gt", "ibm,rgmii"; |
| reg = <0xef601500 0x00000008>; |
| has-mdio; |
| }; |
| |
| RGMII1: emac-rgmii@ef601600 { |
| compatible = "ibm,rgmii-460gt", "ibm,rgmii"; |
| reg = <0xef601600 0x00000008>; |
| has-mdio; |
| }; |
| |
| TAH0: emac-tah@ef601350 { |
| compatible = "ibm,tah-460gt", "ibm,tah"; |
| reg = <0xef601350 0x00000030>; |
| }; |
| |
| TAH1: emac-tah@ef601450 { |
| compatible = "ibm,tah-460gt", "ibm,tah"; |
| reg = <0xef601450 0x00000030>; |
| }; |
| |
| EMAC0: ethernet@ef600e00 { |
| device_type = "network"; |
| compatible = "ibm,emac-460gt", "ibm,emac4sync"; |
| interrupt-parent = <&EMAC0>; |
| interrupts = <0x0 0x1>; |
| #interrupt-cells = <1>; |
| #address-cells = <0>; |
| #size-cells = <0>; |
| interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4 |
| /*Wake*/ 0x1 &UIC2 0x14 0x4>; |
| reg = <0xef600e00 0x000000c4>; |
| local-mac-address = [000000000000]; /* Filled in by U-Boot */ |
| mal-device = <&MAL0>; |
| mal-tx-channel = <0>; |
| mal-rx-channel = <0>; |
| cell-index = <0>; |
| max-frame-size = <9000>; |
| rx-fifo-size = <4096>; |
| tx-fifo-size = <2048>; |
| rx-fifo-size-gige = <16384>; |
| phy-mode = "rgmii"; |
| phy-map = <0x00000000>; |
| rgmii-device = <&RGMII0>; |
| rgmii-channel = <0>; |
| tah-device = <&TAH0>; |
| tah-channel = <0>; |
| has-inverted-stacr-oc; |
| has-new-stacr-staopc; |
| }; |
| |
| EMAC1: ethernet@ef600f00 { |
| device_type = "network"; |
| compatible = "ibm,emac-460gt", "ibm,emac4sync"; |
| interrupt-parent = <&EMAC1>; |
| interrupts = <0x0 0x1>; |
| #interrupt-cells = <1>; |
| #address-cells = <0>; |
| #size-cells = <0>; |
| interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4 |
| /*Wake*/ 0x1 &UIC2 0x15 0x4>; |
| reg = <0xef600f00 0x000000c4>; |
| local-mac-address = [000000000000]; /* Filled in by U-Boot */ |
| mal-device = <&MAL0>; |
| mal-tx-channel = <1>; |
| mal-rx-channel = <8>; |
| cell-index = <1>; |
| max-frame-size = <9000>; |
| rx-fifo-size = <4096>; |
| tx-fifo-size = <2048>; |
| rx-fifo-size-gige = <16384>; |
| phy-mode = "rgmii"; |
| phy-map = <0x00000000>; |
| rgmii-device = <&RGMII0>; |
| rgmii-channel = <1>; |
| tah-device = <&TAH1>; |
| tah-channel = <1>; |
| has-inverted-stacr-oc; |
| has-new-stacr-staopc; |
| mdio-device = <&EMAC0>; |
| }; |
| |
| EMAC2: ethernet@ef601100 { |
| device_type = "network"; |
| compatible = "ibm,emac-460gt", "ibm,emac4sync"; |
| interrupt-parent = <&EMAC2>; |
| interrupts = <0x0 0x1>; |
| #interrupt-cells = <1>; |
| #address-cells = <0>; |
| #size-cells = <0>; |
| interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4 |
| /*Wake*/ 0x1 &UIC2 0x16 0x4>; |
| reg = <0xef601100 0x000000c4>; |
| local-mac-address = [000000000000]; /* Filled in by U-Boot */ |
| mal-device = <&MAL0>; |
| mal-tx-channel = <2>; |
| mal-rx-channel = <16>; |
| cell-index = <2>; |
| max-frame-size = <9000>; |
| rx-fifo-size = <4096>; |
| tx-fifo-size = <2048>; |
| rx-fifo-size-gige = <16384>; |
| tx-fifo-size-gige = <16384>; /* emac2&3 only */ |
| phy-mode = "rgmii"; |
| phy-map = <0x00000000>; |
| rgmii-device = <&RGMII1>; |
| rgmii-channel = <0>; |
| has-inverted-stacr-oc; |
| has-new-stacr-staopc; |
| mdio-device = <&EMAC0>; |
| }; |
| |
| EMAC3: ethernet@ef601200 { |
| device_type = "network"; |
| compatible = "ibm,emac-460gt", "ibm,emac4sync"; |
| interrupt-parent = <&EMAC3>; |
| interrupts = <0x0 0x1>; |
| #interrupt-cells = <1>; |
| #address-cells = <0>; |
| #size-cells = <0>; |
| interrupt-map = </*Status*/ 0x0 &UIC2 0x13 0x4 |
| /*Wake*/ 0x1 &UIC2 0x17 0x4>; |
| reg = <0xef601200 0x000000c4>; |
| local-mac-address = [000000000000]; /* Filled in by U-Boot */ |
| mal-device = <&MAL0>; |
| mal-tx-channel = <3>; |
| mal-rx-channel = <24>; |
| cell-index = <3>; |
| max-frame-size = <9000>; |
| rx-fifo-size = <4096>; |
| tx-fifo-size = <2048>; |
| rx-fifo-size-gige = <16384>; |
| tx-fifo-size-gige = <16384>; /* emac2&3 only */ |
| phy-mode = "rgmii"; |
| phy-map = <0x00000000>; |
| rgmii-device = <&RGMII1>; |
| rgmii-channel = <1>; |
| has-inverted-stacr-oc; |
| has-new-stacr-staopc; |
| mdio-device = <&EMAC0>; |
| }; |
| }; |
| |
| PCIX0: pci@c0ec00000 { |
| device_type = "pci"; |
| #interrupt-cells = <1>; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| compatible = "ibm,plb-pcix-460gt", "ibm,plb-pcix"; |
| primary; |
| large-inbound-windows; |
| enable-msi-hole; |
| reg = <0x0000000c 0x0ec00000 0x00000008 /* Config space access */ |
| 0x00000000 0x00000000 0x00000000 /* no IACK cycles */ |
| 0x0000000c 0x0ed00000 0x00000004 /* Special cycles */ |
| 0x0000000c 0x0ec80000 0x00000100 /* Internal registers */ |
| 0x0000000c 0x0ec80100 0x000000fc>; /* Internal messaging registers */ |
| |
| /* Outbound ranges, one memory and one IO, |
| * later cannot be changed |
| */ |
| ranges = <0x02000000 0x00000000 0x80000000 0x0000000d 0x80000000 0x00000000 0x80000000 |
| 0x02000000 0x00000000 0x00000000 0x0000000c 0x0ee00000 0x00000000 0x00100000 |
| 0x01000000 0x00000000 0x00000000 0x0000000c 0x08000000 0x00000000 0x00010000>; |
| |
| /* Inbound 2GB range starting at 0 */ |
| dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; |
| |
| /* This drives busses 0 to 0x3f */ |
| bus-range = <0x0 0x3f>; |
| |
| /* All PCI interrupts are routed to ext IRQ 2 -> UIC1-0 */ |
| interrupt-map-mask = <0x0 0x0 0x0 0x0>; |
| interrupt-map = < 0x0 0x0 0x0 0x0 &UIC1 0x0 0x8 >; |
| }; |
| |
| PCIE0: pciex@d00000000 { |
| device_type = "pci"; |
| #interrupt-cells = <1>; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; |
| primary; |
| port = <0x0>; /* port number */ |
| reg = <0x0000000d 0x00000000 0x20000000 /* Config space access */ |
| 0x0000000c 0x08010000 0x00001000>; /* Registers */ |
| dcr-reg = <0x100 0x020>; |
| sdr-base = <0x300>; |
| |
| /* Outbound ranges, one memory and one IO, |
| * later cannot be changed |
| */ |
| ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x00000000 0x00000000 0x80000000 |
| 0x02000000 0x00000000 0x00000000 0x0000000f 0x00000000 0x00000000 0x00100000 |
| 0x01000000 0x00000000 0x00000000 0x0000000f 0x80000000 0x00000000 0x00010000>; |
| |
| /* Inbound 2GB range starting at 0 */ |
| dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; |
| |
| /* This drives busses 40 to 0x7f */ |
| bus-range = <0x40 0x7f>; |
| |
| /* Legacy interrupts (note the weird polarity, the bridge seems |
| * to invert PCIe legacy interrupts). |
| * We are de-swizzling here because the numbers are actually for |
| * port of the root complex virtual P2P bridge. But I want |
| * to avoid putting a node for it in the tree, so the numbers |
| * below are basically de-swizzled numbers. |
| * The real slot is on idsel 0, so the swizzling is 1:1 |
| */ |
| interrupt-map-mask = <0x0 0x0 0x0 0x7>; |
| interrupt-map = < |
| 0x0 0x0 0x0 0x1 &UIC3 0xc 0x4 /* swizzled int A */ |
| 0x0 0x0 0x0 0x2 &UIC3 0xd 0x4 /* swizzled int B */ |
| 0x0 0x0 0x0 0x3 &UIC3 0xe 0x4 /* swizzled int C */ |
| 0x0 0x0 0x0 0x4 &UIC3 0xf 0x4 /* swizzled int D */>; |
| }; |
| |
| PCIE1: pciex@d20000000 { |
| device_type = "pci"; |
| #interrupt-cells = <1>; |
| #size-cells = <2>; |
| #address-cells = <3>; |
| compatible = "ibm,plb-pciex-460ex", "ibm,plb-pciex"; |
| primary; |
| port = <0x1>; /* port number */ |
| reg = <0x0000000d 0x20000000 0x20000000 /* Config space access */ |
| 0x0000000c 0x08011000 0x00001000>; /* Registers */ |
| dcr-reg = <0x120 0x020>; |
| sdr-base = <0x340>; |
| |
| /* Outbound ranges, one memory and one IO, |
| * later cannot be changed |
| */ |
| ranges = <0x02000000 0x00000000 0x80000000 0x0000000e 0x80000000 0x00000000 0x80000000 |
| 0x02000000 0x00000000 0x00000000 0x0000000f 0x00100000 0x00000000 0x00100000 |
| 0x01000000 0x00000000 0x00000000 0x0000000f 0x80010000 0x00000000 0x00010000>; |
| |
| /* Inbound 2GB range starting at 0 */ |
| dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>; |
| |
| /* This drives busses 80 to 0xbf */ |
| bus-range = <0x80 0xbf>; |
| |
| /* Legacy interrupts (note the weird polarity, the bridge seems |
| * to invert PCIe legacy interrupts). |
| * We are de-swizzling here because the numbers are actually for |
| * port of the root complex virtual P2P bridge. But I want |
| * to avoid putting a node for it in the tree, so the numbers |
| * below are basically de-swizzled numbers. |
| * The real slot is on idsel 0, so the swizzling is 1:1 |
| */ |
| interrupt-map-mask = <0x0 0x0 0x0 0x7>; |
| interrupt-map = < |
| 0x0 0x0 0x0 0x1 &UIC3 0x10 0x4 /* swizzled int A */ |
| 0x0 0x0 0x0 0x2 &UIC3 0x11 0x4 /* swizzled int B */ |
| 0x0 0x0 0x0 0x3 &UIC3 0x12 0x4 /* swizzled int C */ |
| 0x0 0x0 0x0 0x4 &UIC3 0x13 0x4 /* swizzled int D */>; |
| }; |
| }; |
| }; |
