| Freescale Vybrid Miscellaneous System Control - Interrupt Router |
| |
| The MSCM IP contains multiple sub modules, this binding describes the second |
| block of registers which control the interrupt router. The interrupt router |
| allows to configure the recipient of each peripheral interrupt. Furthermore |
| it controls the directed processor interrupts. The module is available in all |
| Vybrid SoC's but is only really useful in dual core configurations (VF6xx |
| which comes with a Cortex-A5/Cortex-M4 combination). |
| |
| Required properties: |
| - compatible: "fsl,vf610-mscm-ir" |
| - reg: the register range of the MSCM Interrupt Router |
| - fsl,cpucfg: The handle to the MSCM CPU configuration node, required |
| to get the current CPU ID |
| - interrupt-controller: Identifies the node as an interrupt controller |
| - #interrupt-cells: Two cells, interrupt number and cells. |
| The hardware interrupt number according to interrupt |
| assignment of the interrupt router is required. |
| Flags get passed only when using GIC as parent. Flags |
| encoding as documented by the GIC bindings. |
| |
| Example: |
| mscm_ir: interrupt-controller@40001800 { |
| compatible = "fsl,vf610-mscm-ir"; |
| reg = <0x40001800 0x400>; |
| fsl,cpucfg = <&mscm_cpucfg>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| interrupt-parent = <&intc>; |
| } |
