| // SPDX-License-Identifier: GPL-2.0 |
| // |
| // Copyright 2013 Freescale Semiconductor, Inc. |
| |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include "imx6sl-pinfunc.h" |
| #include <dt-bindings/clock/imx6sl-clock.h> |
| |
| / { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| /* |
| * The decompressor and also some bootloaders rely on a |
| * pre-existing /chosen node to be available to insert the |
| * command line and merge other ATAGS info. |
| * Also for U-Boot there must be a pre-existing /memory node. |
| */ |
| chosen {}; |
| memory { device_type = "memory"; }; |
| |
| aliases { |
| ethernet0 = &fec; |
| gpio0 = &gpio1; |
| gpio1 = &gpio2; |
| gpio2 = &gpio3; |
| gpio3 = &gpio4; |
| gpio4 = &gpio5; |
| serial0 = &uart1; |
| serial1 = &uart2; |
| serial2 = &uart3; |
| serial3 = &uart4; |
| serial4 = &uart5; |
| spi0 = &ecspi1; |
| spi1 = &ecspi2; |
| spi2 = &ecspi3; |
| spi3 = &ecspi4; |
| usbphy0 = &usbphy1; |
| usbphy1 = &usbphy2; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| compatible = "arm,cortex-a9"; |
| device_type = "cpu"; |
| reg = <0x0>; |
| next-level-cache = <&L2>; |
| operating-points = < |
| /* kHz uV */ |
| 996000 1275000 |
| 792000 1175000 |
| 396000 975000 |
| >; |
| fsl,soc-operating-points = < |
| /* ARM kHz SOC-PU uV */ |
| 996000 1225000 |
| 792000 1175000 |
| 396000 1175000 |
| >; |
| clock-latency = <61036>; /* two CLK32 periods */ |
| #cooling-cells = <2>; |
| clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>, |
| <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>, |
| <&clks IMX6SL_CLK_PLL1_SYS>; |
| clock-names = "arm", "pll2_pfd2_396m", "step", |
| "pll1_sw", "pll1_sys"; |
| arm-supply = <®_arm>; |
| pu-supply = <®_pu>; |
| soc-supply = <®_soc>; |
| }; |
| }; |
| |
| intc: interrupt-controller@a01000 { |
| compatible = "arm,cortex-a9-gic"; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| reg = <0x00a01000 0x1000>, |
| <0x00a00100 0x100>; |
| interrupt-parent = <&intc>; |
| }; |
| |
| clocks { |
| ckil { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <32768>; |
| }; |
| |
| osc { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <24000000>; |
| }; |
| }; |
| |
| tempmon: tempmon { |
| compatible = "fsl,imx6q-tempmon"; |
| interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-parent = <&gpc>; |
| fsl,tempmon = <&anatop>; |
| fsl,tempmon-data = <&ocotp>; |
| clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>; |
| }; |
| |
| pmu { |
| compatible = "arm,cortex-a9-pmu"; |
| interrupt-parent = <&gpc>; |
| interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| soc { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "simple-bus"; |
| interrupt-parent = <&gpc>; |
| ranges; |
| |
| ocram: sram@900000 { |
| compatible = "mmio-sram"; |
| reg = <0x00900000 0x20000>; |
| clocks = <&clks IMX6SL_CLK_OCRAM>; |
| }; |
| |
| L2: l2-cache@a02000 { |
| compatible = "arm,pl310-cache"; |
| reg = <0x00a02000 0x1000>; |
| interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; |
| cache-unified; |
| cache-level = <2>; |
| arm,tag-latency = <4 2 3>; |
| arm,data-latency = <4 2 3>; |
| }; |
| |
| aips1: aips-bus@2000000 { |
| compatible = "fsl,aips-bus", "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x02000000 0x100000>; |
| ranges; |
| |
| spba: spba-bus@2000000 { |
| compatible = "fsl,spba-bus", "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x02000000 0x40000>; |
| ranges; |
| |
| spdif: spdif@2004000 { |
| compatible = "fsl,imx6sl-spdif", |
| "fsl,imx35-spdif"; |
| reg = <0x02004000 0x4000>; |
| interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&sdma 14 18 0>, |
| <&sdma 15 18 0>; |
| dma-names = "rx", "tx"; |
| clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>, |
| <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>, |
| <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>, |
| <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>, |
| <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>; |
| clock-names = "core", "rxtx0", |
| "rxtx1", "rxtx2", |
| "rxtx3", "rxtx4", |
| "rxtx5", "rxtx6", |
| "rxtx7", "spba"; |
| status = "disabled"; |
| }; |
| |
| ecspi1: ecspi@2008000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; |
| reg = <0x02008000 0x4000>; |
| interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_ECSPI1>, |
| <&clks IMX6SL_CLK_ECSPI1>; |
| clock-names = "ipg", "per"; |
| status = "disabled"; |
| }; |
| |
| ecspi2: ecspi@200c000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; |
| reg = <0x0200c000 0x4000>; |
| interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_ECSPI2>, |
| <&clks IMX6SL_CLK_ECSPI2>; |
| clock-names = "ipg", "per"; |
| status = "disabled"; |
| }; |
| |
| ecspi3: ecspi@2010000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; |
| reg = <0x02010000 0x4000>; |
| interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_ECSPI3>, |
| <&clks IMX6SL_CLK_ECSPI3>; |
| clock-names = "ipg", "per"; |
| status = "disabled"; |
| }; |
| |
| ecspi4: ecspi@2014000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; |
| reg = <0x02014000 0x4000>; |
| interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_ECSPI4>, |
| <&clks IMX6SL_CLK_ECSPI4>; |
| clock-names = "ipg", "per"; |
| status = "disabled"; |
| }; |
| |
| uart5: serial@2018000 { |
| compatible = "fsl,imx6sl-uart", |
| "fsl,imx6q-uart", "fsl,imx21-uart"; |
| reg = <0x02018000 0x4000>; |
| interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_UART>, |
| <&clks IMX6SL_CLK_UART_SERIAL>; |
| clock-names = "ipg", "per"; |
| dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| uart1: serial@2020000 { |
| compatible = "fsl,imx6sl-uart", |
| "fsl,imx6q-uart", "fsl,imx21-uart"; |
| reg = <0x02020000 0x4000>; |
| interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_UART>, |
| <&clks IMX6SL_CLK_UART_SERIAL>; |
| clock-names = "ipg", "per"; |
| dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| uart2: serial@2024000 { |
| compatible = "fsl,imx6sl-uart", |
| "fsl,imx6q-uart", "fsl,imx21-uart"; |
| reg = <0x02024000 0x4000>; |
| interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_UART>, |
| <&clks IMX6SL_CLK_UART_SERIAL>; |
| clock-names = "ipg", "per"; |
| dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| ssi1: ssi@2028000 { |
| #sound-dai-cells = <0>; |
| compatible = "fsl,imx6sl-ssi", |
| "fsl,imx51-ssi"; |
| reg = <0x02028000 0x4000>; |
| interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_SSI1_IPG>, |
| <&clks IMX6SL_CLK_SSI1>; |
| clock-names = "ipg", "baud"; |
| dmas = <&sdma 37 1 0>, |
| <&sdma 38 1 0>; |
| dma-names = "rx", "tx"; |
| fsl,fifo-depth = <15>; |
| status = "disabled"; |
| }; |
| |
| ssi2: ssi@202c000 { |
| #sound-dai-cells = <0>; |
| compatible = "fsl,imx6sl-ssi", |
| "fsl,imx51-ssi"; |
| reg = <0x0202c000 0x4000>; |
| interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_SSI2_IPG>, |
| <&clks IMX6SL_CLK_SSI2>; |
| clock-names = "ipg", "baud"; |
| dmas = <&sdma 41 1 0>, |
| <&sdma 42 1 0>; |
| dma-names = "rx", "tx"; |
| fsl,fifo-depth = <15>; |
| status = "disabled"; |
| }; |
| |
| ssi3: ssi@2030000 { |
| #sound-dai-cells = <0>; |
| compatible = "fsl,imx6sl-ssi", |
| "fsl,imx51-ssi"; |
| reg = <0x02030000 0x4000>; |
| interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_SSI3_IPG>, |
| <&clks IMX6SL_CLK_SSI3>; |
| clock-names = "ipg", "baud"; |
| dmas = <&sdma 45 1 0>, |
| <&sdma 46 1 0>; |
| dma-names = "rx", "tx"; |
| fsl,fifo-depth = <15>; |
| status = "disabled"; |
| }; |
| |
| uart3: serial@2034000 { |
| compatible = "fsl,imx6sl-uart", |
| "fsl,imx6q-uart", "fsl,imx21-uart"; |
| reg = <0x02034000 0x4000>; |
| interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_UART>, |
| <&clks IMX6SL_CLK_UART_SERIAL>; |
| clock-names = "ipg", "per"; |
| dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| |
| uart4: serial@2038000 { |
| compatible = "fsl,imx6sl-uart", |
| "fsl,imx6q-uart", "fsl,imx21-uart"; |
| reg = <0x02038000 0x4000>; |
| interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_UART>, |
| <&clks IMX6SL_CLK_UART_SERIAL>; |
| clock-names = "ipg", "per"; |
| dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; |
| dma-names = "rx", "tx"; |
| status = "disabled"; |
| }; |
| }; |
| |
| pwm1: pwm@2080000 { |
| #pwm-cells = <2>; |
| compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; |
| reg = <0x02080000 0x4000>; |
| interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_PWM1>, |
| <&clks IMX6SL_CLK_PWM1>; |
| clock-names = "ipg", "per"; |
| }; |
| |
| pwm2: pwm@2084000 { |
| #pwm-cells = <2>; |
| compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; |
| reg = <0x02084000 0x4000>; |
| interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_PWM2>, |
| <&clks IMX6SL_CLK_PWM2>; |
| clock-names = "ipg", "per"; |
| }; |
| |
| pwm3: pwm@2088000 { |
| #pwm-cells = <2>; |
| compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; |
| reg = <0x02088000 0x4000>; |
| interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_PWM3>, |
| <&clks IMX6SL_CLK_PWM3>; |
| clock-names = "ipg", "per"; |
| }; |
| |
| pwm4: pwm@208c000 { |
| #pwm-cells = <2>; |
| compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; |
| reg = <0x0208c000 0x4000>; |
| interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_PWM4>, |
| <&clks IMX6SL_CLK_PWM4>; |
| clock-names = "ipg", "per"; |
| }; |
| |
| gpt: gpt@2098000 { |
| compatible = "fsl,imx6sl-gpt"; |
| reg = <0x02098000 0x4000>; |
| interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_GPT>, |
| <&clks IMX6SL_CLK_GPT_SERIAL>; |
| clock-names = "ipg", "per"; |
| }; |
| |
| gpio1: gpio@209c000 { |
| compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; |
| reg = <0x0209c000 0x4000>; |
| interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, |
| <0 67 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| gpio-ranges = <&iomuxc 0 22 1>, <&iomuxc 1 20 2>, |
| <&iomuxc 3 23 1>, <&iomuxc 4 25 1>, |
| <&iomuxc 5 24 1>, <&iomuxc 6 19 1>, |
| <&iomuxc 7 36 2>, <&iomuxc 9 44 8>, |
| <&iomuxc 17 38 6>, <&iomuxc 23 68 4>, |
| <&iomuxc 27 64 4>, <&iomuxc 31 52 1>; |
| }; |
| |
| gpio2: gpio@20a0000 { |
| compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; |
| reg = <0x020a0000 0x4000>; |
| interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, |
| <0 69 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| gpio-ranges = <&iomuxc 0 53 3>, <&iomuxc 3 72 2>, |
| <&iomuxc 5 34 2>, <&iomuxc 7 57 4>, |
| <&iomuxc 11 56 1>, <&iomuxc 12 61 3>, |
| <&iomuxc 15 107 1>, <&iomuxc 16 132 2>, |
| <&iomuxc 18 135 1>, <&iomuxc 19 134 1>, |
| <&iomuxc 20 108 2>, <&iomuxc 22 120 1>, |
| <&iomuxc 23 125 7>, <&iomuxc 30 110 2>; |
| }; |
| |
| gpio3: gpio@20a4000 { |
| compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; |
| reg = <0x020a4000 0x4000>; |
| interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, |
| <0 71 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| gpio-ranges = <&iomuxc 0 112 8>, <&iomuxc 8 121 4>, |
| <&iomuxc 12 97 4>, <&iomuxc 16 166 3>, |
| <&iomuxc 19 85 2>, <&iomuxc 21 137 2>, |
| <&iomuxc 23 136 1>, <&iomuxc 24 91 1>, |
| <&iomuxc 25 99 1>, <&iomuxc 26 92 1>, |
| <&iomuxc 27 100 1>, <&iomuxc 28 93 1>, |
| <&iomuxc 29 101 1>, <&iomuxc 30 94 1>, |
| <&iomuxc 31 102 1>; |
| }; |
| |
| gpio4: gpio@20a8000 { |
| compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; |
| reg = <0x020a8000 0x4000>; |
| interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, |
| <0 73 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| gpio-ranges = <&iomuxc 0 95 1>, <&iomuxc 1 103 1>, |
| <&iomuxc 2 96 1>, <&iomuxc 3 104 1>, |
| <&iomuxc 4 97 1>, <&iomuxc 5 105 1>, |
| <&iomuxc 6 98 1>, <&iomuxc 7 106 1>, |
| <&iomuxc 8 28 1>, <&iomuxc 9 27 1>, |
| <&iomuxc 10 26 1>, <&iomuxc 11 29 1>, |
| <&iomuxc 12 32 1>, <&iomuxc 13 31 1>, |
| <&iomuxc 14 30 1>, <&iomuxc 15 33 1>, |
| <&iomuxc 16 84 1>, <&iomuxc 17 79 2>, |
| <&iomuxc 19 78 1>, <&iomuxc 20 76 1>, |
| <&iomuxc 21 81 2>, <&iomuxc 23 75 1>, |
| <&iomuxc 24 83 1>, <&iomuxc 25 74 1>, |
| <&iomuxc 26 77 1>, <&iomuxc 27 159 1>, |
| <&iomuxc 28 154 1>, <&iomuxc 29 157 1>, |
| <&iomuxc 30 152 1>, <&iomuxc 31 156 1>; |
| }; |
| |
| gpio5: gpio@20ac000 { |
| compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; |
| reg = <0x020ac000 0x4000>; |
| interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, |
| <0 75 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| gpio-ranges = <&iomuxc 0 158 1>, <&iomuxc 1 151 1>, |
| <&iomuxc 2 155 1>, <&iomuxc 3 153 1>, |
| <&iomuxc 4 150 1>, <&iomuxc 5 149 1>, |
| <&iomuxc 6 144 1>, <&iomuxc 7 147 1>, |
| <&iomuxc 8 142 1>, <&iomuxc 9 146 1>, |
| <&iomuxc 10 148 1>, <&iomuxc 11 141 1>, |
| <&iomuxc 12 145 1>, <&iomuxc 13 143 1>, |
| <&iomuxc 14 140 1>, <&iomuxc 15 139 1>, |
| <&iomuxc 16 164 2>, <&iomuxc 18 160 1>, |
| <&iomuxc 19 162 1>, <&iomuxc 20 163 1>, |
| <&iomuxc 21 161 1>; |
| }; |
| |
| kpp: kpp@20b8000 { |
| compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp"; |
| reg = <0x020b8000 0x4000>; |
| interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_DUMMY>; |
| status = "disabled"; |
| }; |
| |
| wdog1: wdog@20bc000 { |
| compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; |
| reg = <0x020bc000 0x4000>; |
| interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_DUMMY>; |
| }; |
| |
| wdog2: wdog@20c0000 { |
| compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; |
| reg = <0x020c0000 0x4000>; |
| interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_DUMMY>; |
| status = "disabled"; |
| }; |
| |
| clks: ccm@20c4000 { |
| compatible = "fsl,imx6sl-ccm"; |
| reg = <0x020c4000 0x4000>; |
| interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, |
| <0 88 IRQ_TYPE_LEVEL_HIGH>; |
| #clock-cells = <1>; |
| }; |
| |
| anatop: anatop@20c8000 { |
| compatible = "fsl,imx6sl-anatop", |
| "fsl,imx6q-anatop", |
| "syscon", "simple-bus"; |
| reg = <0x020c8000 0x1000>; |
| interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, |
| <0 54 IRQ_TYPE_LEVEL_HIGH>, |
| <0 127 IRQ_TYPE_LEVEL_HIGH>; |
| |
| regulator-1p1 { |
| compatible = "fsl,anatop-regulator"; |
| regulator-name = "vdd1p1"; |
| regulator-min-microvolt = <1000000>; |
| regulator-max-microvolt = <1200000>; |
| regulator-always-on; |
| anatop-reg-offset = <0x110>; |
| anatop-vol-bit-shift = <8>; |
| anatop-vol-bit-width = <5>; |
| anatop-min-bit-val = <4>; |
| anatop-min-voltage = <800000>; |
| anatop-max-voltage = <1375000>; |
| anatop-enable-bit = <0>; |
| }; |
| |
| regulator-3p0 { |
| compatible = "fsl,anatop-regulator"; |
| regulator-name = "vdd3p0"; |
| regulator-min-microvolt = <2800000>; |
| regulator-max-microvolt = <3150000>; |
| regulator-always-on; |
| anatop-reg-offset = <0x120>; |
| anatop-vol-bit-shift = <8>; |
| anatop-vol-bit-width = <5>; |
| anatop-min-bit-val = <0>; |
| anatop-min-voltage = <2625000>; |
| anatop-max-voltage = <3400000>; |
| anatop-enable-bit = <0>; |
| }; |
| |
| regulator-2p5 { |
| compatible = "fsl,anatop-regulator"; |
| regulator-name = "vdd2p5"; |
| regulator-min-microvolt = <2250000>; |
| regulator-max-microvolt = <2750000>; |
| regulator-always-on; |
| anatop-reg-offset = <0x130>; |
| anatop-vol-bit-shift = <8>; |
| anatop-vol-bit-width = <5>; |
| anatop-min-bit-val = <0>; |
| anatop-min-voltage = <2100000>; |
| anatop-max-voltage = <2850000>; |
| anatop-enable-bit = <0>; |
| }; |
| |
| reg_arm: regulator-vddcore { |
| compatible = "fsl,anatop-regulator"; |
| regulator-name = "vddarm"; |
| regulator-min-microvolt = <725000>; |
| regulator-max-microvolt = <1450000>; |
| regulator-always-on; |
| anatop-reg-offset = <0x140>; |
| anatop-vol-bit-shift = <0>; |
| anatop-vol-bit-width = <5>; |
| anatop-delay-reg-offset = <0x170>; |
| anatop-delay-bit-shift = <24>; |
| anatop-delay-bit-width = <2>; |
| anatop-min-bit-val = <1>; |
| anatop-min-voltage = <725000>; |
| anatop-max-voltage = <1450000>; |
| }; |
| |
| reg_pu: regulator-vddpu { |
| compatible = "fsl,anatop-regulator"; |
| regulator-name = "vddpu"; |
| regulator-min-microvolt = <725000>; |
| regulator-max-microvolt = <1450000>; |
| regulator-always-on; |
| anatop-reg-offset = <0x140>; |
| anatop-vol-bit-shift = <9>; |
| anatop-vol-bit-width = <5>; |
| anatop-delay-reg-offset = <0x170>; |
| anatop-delay-bit-shift = <26>; |
| anatop-delay-bit-width = <2>; |
| anatop-min-bit-val = <1>; |
| anatop-min-voltage = <725000>; |
| anatop-max-voltage = <1450000>; |
| }; |
| |
| reg_soc: regulator-vddsoc { |
| compatible = "fsl,anatop-regulator"; |
| regulator-name = "vddsoc"; |
| regulator-min-microvolt = <725000>; |
| regulator-max-microvolt = <1450000>; |
| regulator-always-on; |
| anatop-reg-offset = <0x140>; |
| anatop-vol-bit-shift = <18>; |
| anatop-vol-bit-width = <5>; |
| anatop-delay-reg-offset = <0x170>; |
| anatop-delay-bit-shift = <28>; |
| anatop-delay-bit-width = <2>; |
| anatop-min-bit-val = <1>; |
| anatop-min-voltage = <725000>; |
| anatop-max-voltage = <1450000>; |
| }; |
| }; |
| |
| usbphy1: usbphy@20c9000 { |
| compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; |
| reg = <0x020c9000 0x1000>; |
| interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_USBPHY1>; |
| fsl,anatop = <&anatop>; |
| }; |
| |
| usbphy2: usbphy@20ca000 { |
| compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; |
| reg = <0x020ca000 0x1000>; |
| interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_USBPHY2>; |
| fsl,anatop = <&anatop>; |
| }; |
| |
| snvs: snvs@20cc000 { |
| compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; |
| reg = <0x020cc000 0x4000>; |
| |
| snvs_rtc: snvs-rtc-lp { |
| compatible = "fsl,sec-v4.0-mon-rtc-lp"; |
| regmap = <&snvs>; |
| offset = <0x34>; |
| interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, |
| <0 20 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| snvs_poweroff: snvs-poweroff { |
| compatible = "syscon-poweroff"; |
| regmap = <&snvs>; |
| offset = <0x38>; |
| value = <0x60>; |
| mask = <0x60>; |
| status = "disabled"; |
| }; |
| }; |
| |
| epit1: epit@20d0000 { |
| reg = <0x020d0000 0x4000>; |
| interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| epit2: epit@20d4000 { |
| reg = <0x020d4000 0x4000>; |
| interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| src: src@20d8000 { |
| compatible = "fsl,imx6sl-src", "fsl,imx51-src"; |
| reg = <0x020d8000 0x4000>; |
| interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, |
| <0 96 IRQ_TYPE_LEVEL_HIGH>; |
| #reset-cells = <1>; |
| }; |
| |
| gpc: gpc@20dc000 { |
| compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc"; |
| reg = <0x020dc000 0x4000>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-parent = <&intc>; |
| clocks = <&clks IMX6SL_CLK_IPG>; |
| clock-names = "ipg"; |
| |
| pgc { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| power-domain@0 { |
| reg = <0>; |
| #power-domain-cells = <0>; |
| }; |
| |
| pd_pu: power-domain@1 { |
| reg = <1>; |
| #power-domain-cells = <0>; |
| power-supply = <®_pu>; |
| clocks = <&clks IMX6SL_CLK_GPU2D_OVG>, |
| <&clks IMX6SL_CLK_GPU2D_PODF>; |
| }; |
| |
| pd_disp: power-domain@2 { |
| reg = <2>; |
| #power-domain-cells = <0>; |
| clocks = <&clks IMX6SL_CLK_LCDIF_AXI>, |
| <&clks IMX6SL_CLK_LCDIF_PIX>, |
| <&clks IMX6SL_CLK_EPDC_AXI>, |
| <&clks IMX6SL_CLK_EPDC_PIX>, |
| <&clks IMX6SL_CLK_PXP_AXI>; |
| }; |
| }; |
| }; |
| |
| gpr: iomuxc-gpr@20e0000 { |
| compatible = "fsl,imx6sl-iomuxc-gpr", |
| "fsl,imx6q-iomuxc-gpr", "syscon"; |
| reg = <0x020e0000 0x38>; |
| }; |
| |
| iomuxc: iomuxc@20e0000 { |
| compatible = "fsl,imx6sl-iomuxc"; |
| reg = <0x020e0000 0x4000>; |
| }; |
| |
| csi: csi@20e4000 { |
| reg = <0x020e4000 0x4000>; |
| interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| spdc: spdc@20e8000 { |
| reg = <0x020e8000 0x4000>; |
| interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| sdma: sdma@20ec000 { |
| compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma"; |
| reg = <0x020ec000 0x4000>; |
| interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_SDMA>, |
| <&clks IMX6SL_CLK_SDMA>; |
| clock-names = "ipg", "ahb"; |
| #dma-cells = <3>; |
| /* imx6sl reuses imx6q sdma firmware */ |
| fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; |
| }; |
| |
| pxp: pxp@20f0000 { |
| reg = <0x020f0000 0x4000>; |
| interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| epdc: epdc@20f4000 { |
| reg = <0x020f4000 0x4000>; |
| interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| lcdif: lcdif@20f8000 { |
| compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif"; |
| reg = <0x020f8000 0x4000>; |
| interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_LCDIF_PIX>, |
| <&clks IMX6SL_CLK_LCDIF_AXI>, |
| <&clks IMX6SL_CLK_DUMMY>; |
| clock-names = "pix", "axi", "disp_axi"; |
| status = "disabled"; |
| power-domains = <&pd_disp>; |
| }; |
| |
| dcp: dcp@20fc000 { |
| compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp"; |
| reg = <0x020fc000 0x4000>; |
| interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>, |
| <0 100 IRQ_TYPE_LEVEL_HIGH>, |
| <0 101 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| }; |
| |
| aips2: aips-bus@2100000 { |
| compatible = "fsl,aips-bus", "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| reg = <0x02100000 0x100000>; |
| ranges; |
| |
| usbotg1: usb@2184000 { |
| compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; |
| reg = <0x02184000 0x200>; |
| interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_USBOH3>; |
| fsl,usbphy = <&usbphy1>; |
| fsl,usbmisc = <&usbmisc 0>; |
| ahb-burst-config = <0x0>; |
| tx-burst-size-dword = <0x10>; |
| rx-burst-size-dword = <0x10>; |
| status = "disabled"; |
| }; |
| |
| usbotg2: usb@2184200 { |
| compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; |
| reg = <0x02184200 0x200>; |
| interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_USBOH3>; |
| fsl,usbphy = <&usbphy2>; |
| fsl,usbmisc = <&usbmisc 1>; |
| ahb-burst-config = <0x0>; |
| tx-burst-size-dword = <0x10>; |
| rx-burst-size-dword = <0x10>; |
| status = "disabled"; |
| }; |
| |
| usbh: usb@2184400 { |
| compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; |
| reg = <0x02184400 0x200>; |
| interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_USBOH3>; |
| fsl,usbmisc = <&usbmisc 2>; |
| dr_mode = "host"; |
| ahb-burst-config = <0x0>; |
| tx-burst-size-dword = <0x10>; |
| rx-burst-size-dword = <0x10>; |
| status = "disabled"; |
| }; |
| |
| usbmisc: usbmisc@2184800 { |
| #index-cells = <1>; |
| compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc"; |
| reg = <0x02184800 0x200>; |
| clocks = <&clks IMX6SL_CLK_USBOH3>; |
| }; |
| |
| fec: ethernet@2188000 { |
| compatible = "fsl,imx6sl-fec", "fsl,imx25-fec"; |
| reg = <0x02188000 0x4000>; |
| interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_ENET>, |
| <&clks IMX6SL_CLK_ENET_REF>; |
| clock-names = "ipg", "ahb"; |
| status = "disabled"; |
| }; |
| |
| usdhc1: usdhc@2190000 { |
| compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; |
| reg = <0x02190000 0x4000>; |
| interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_USDHC1>, |
| <&clks IMX6SL_CLK_USDHC1>, |
| <&clks IMX6SL_CLK_USDHC1>; |
| clock-names = "ipg", "ahb", "per"; |
| bus-width = <4>; |
| status = "disabled"; |
| }; |
| |
| usdhc2: usdhc@2194000 { |
| compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; |
| reg = <0x02194000 0x4000>; |
| interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_USDHC2>, |
| <&clks IMX6SL_CLK_USDHC2>, |
| <&clks IMX6SL_CLK_USDHC2>; |
| clock-names = "ipg", "ahb", "per"; |
| bus-width = <4>; |
| status = "disabled"; |
| }; |
| |
| usdhc3: usdhc@2198000 { |
| compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; |
| reg = <0x02198000 0x4000>; |
| interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_USDHC3>, |
| <&clks IMX6SL_CLK_USDHC3>, |
| <&clks IMX6SL_CLK_USDHC3>; |
| clock-names = "ipg", "ahb", "per"; |
| bus-width = <4>; |
| status = "disabled"; |
| }; |
| |
| usdhc4: usdhc@219c000 { |
| compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; |
| reg = <0x0219c000 0x4000>; |
| interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_USDHC4>, |
| <&clks IMX6SL_CLK_USDHC4>, |
| <&clks IMX6SL_CLK_USDHC4>; |
| clock-names = "ipg", "ahb", "per"; |
| bus-width = <4>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@21a0000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; |
| reg = <0x021a0000 0x4000>; |
| interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_I2C1>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@21a4000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; |
| reg = <0x021a4000 0x4000>; |
| interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_I2C2>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@21a8000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; |
| reg = <0x021a8000 0x4000>; |
| interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_I2C3>; |
| status = "disabled"; |
| }; |
| |
| mmdc: mmdc@21b0000 { |
| compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc"; |
| reg = <0x021b0000 0x4000>; |
| }; |
| |
| rngb: rngb@21b4000 { |
| reg = <0x021b4000 0x4000>; |
| interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| weim: weim@21b8000 { |
| #address-cells = <2>; |
| #size-cells = <1>; |
| reg = <0x021b8000 0x4000>; |
| interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; |
| fsl,weim-cs-gpr = <&gpr>; |
| status = "disabled"; |
| }; |
| |
| ocotp: ocotp@21bc000 { |
| compatible = "fsl,imx6sl-ocotp", "syscon"; |
| reg = <0x021bc000 0x4000>; |
| clocks = <&clks IMX6SL_CLK_OCOTP>; |
| }; |
| |
| audmux: audmux@21d8000 { |
| compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux"; |
| reg = <0x021d8000 0x4000>; |
| status = "disabled"; |
| }; |
| }; |
| |
| gpu_2d: gpu@2200000 { |
| compatible = "vivante,gc"; |
| reg = <0x02200000 0x4000>; |
| interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_MMDC_ROOT>, |
| <&clks IMX6SL_CLK_GPU2D_OVG>; |
| clock-names = "bus", "core"; |
| power-domains = <&pd_pu>; |
| }; |
| |
| gpu_vg: gpu@2204000 { |
| compatible = "vivante,gc"; |
| reg = <0x02204000 0x4000>; |
| interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6SL_CLK_MMDC_ROOT>, |
| <&clks IMX6SL_CLK_GPU2D_OVG>; |
| clock-names = "bus", "core"; |
| power-domains = <&pd_pu>; |
| }; |
| }; |
| }; |
