| # | |
| # EDAC Kconfig | |
| # Copyright (c) 2008 Doug Thompson www.softwarebitmaker.com | |
| # Licensed and distributed under the GPL | |
| # | |
| menuconfig EDAC | |
| bool "EDAC - error detection and reporting" | |
| depends on HAS_IOMEM | |
| depends on X86 || PPC | |
| help | |
| EDAC is designed to report errors in the core system. | |
| These are low-level errors that are reported in the CPU or | |
| supporting chipset or other subsystems: | |
| memory errors, cache errors, PCI errors, thermal throttling, etc.. | |
| If unsure, select 'Y'. | |
| If this code is reporting problems on your system, please | |
| see the EDAC project web pages for more information at: | |
| <http://bluesmoke.sourceforge.net/> | |
| and: | |
| <http://buttersideup.com/edacwiki> | |
| There is also a mailing list for the EDAC project, which can | |
| be found via the sourceforge page. | |
| if EDAC | |
| comment "Reporting subsystems" | |
| config EDAC_DEBUG | |
| bool "Debugging" | |
| help | |
| This turns on debugging information for the entire EDAC | |
| sub-system. You can insert module with "debug_level=x", current | |
| there're four debug levels (x=0,1,2,3 from low to high). | |
| Usually you should select 'N'. | |
| config EDAC_DEBUG_VERBOSE | |
| bool "More verbose debugging" | |
| depends on EDAC_DEBUG | |
| help | |
| This option makes debugging information more verbose. | |
| Source file name and line number where debugging message | |
| printed will be added to debugging message. | |
| config EDAC_MM_EDAC | |
| tristate "Main Memory EDAC (Error Detection And Correction) reporting" | |
| default y | |
| help | |
| Some systems are able to detect and correct errors in main | |
| memory. EDAC can report statistics on memory error | |
| detection and correction (EDAC - or commonly referred to ECC | |
| errors). EDAC will also try to decode where these errors | |
| occurred so that a particular failing memory module can be | |
| replaced. If unsure, select 'Y'. | |
| config EDAC_AMD76X | |
| tristate "AMD 76x (760, 762, 768)" | |
| depends on EDAC_MM_EDAC && PCI && X86_32 | |
| help | |
| Support for error detection and correction on the AMD 76x | |
| series of chipsets used with the Athlon processor. | |
| config EDAC_E7XXX | |
| tristate "Intel e7xxx (e7205, e7500, e7501, e7505)" | |
| depends on EDAC_MM_EDAC && PCI && X86_32 | |
| help | |
| Support for error detection and correction on the Intel | |
| E7205, E7500, E7501 and E7505 server chipsets. | |
| config EDAC_E752X | |
| tristate "Intel e752x (e7520, e7525, e7320) and 3100" | |
| depends on EDAC_MM_EDAC && PCI && X86 && HOTPLUG | |
| help | |
| Support for error detection and correction on the Intel | |
| E7520, E7525, E7320 server chipsets. | |
| config EDAC_I82443BXGX | |
| tristate "Intel 82443BX/GX (440BX/GX)" | |
| depends on EDAC_MM_EDAC && PCI && X86_32 | |
| depends on BROKEN | |
| help | |
| Support for error detection and correction on the Intel | |
| 82443BX/GX memory controllers (440BX/GX chipsets). | |
| config EDAC_I82875P | |
| tristate "Intel 82875p (D82875P, E7210)" | |
| depends on EDAC_MM_EDAC && PCI && X86_32 | |
| help | |
| Support for error detection and correction on the Intel | |
| DP82785P and E7210 server chipsets. | |
| config EDAC_I82975X | |
| tristate "Intel 82975x (D82975x)" | |
| depends on EDAC_MM_EDAC && PCI && X86 | |
| help | |
| Support for error detection and correction on the Intel | |
| DP82975x server chipsets. | |
| config EDAC_I3000 | |
| tristate "Intel 3000/3010" | |
| depends on EDAC_MM_EDAC && PCI && X86 | |
| help | |
| Support for error detection and correction on the Intel | |
| 3000 and 3010 server chipsets. | |
| config EDAC_X38 | |
| tristate "Intel X38" | |
| depends on EDAC_MM_EDAC && PCI && X86 | |
| help | |
| Support for error detection and correction on the Intel | |
| X38 server chipsets. | |
| config EDAC_I5400 | |
| tristate "Intel 5400 (Seaburg) chipsets" | |
| depends on EDAC_MM_EDAC && PCI && X86 | |
| help | |
| Support for error detection and correction the Intel | |
| i5400 MCH chipset (Seaburg). | |
| config EDAC_I82860 | |
| tristate "Intel 82860" | |
| depends on EDAC_MM_EDAC && PCI && X86_32 | |
| help | |
| Support for error detection and correction on the Intel | |
| 82860 chipset. | |
| config EDAC_R82600 | |
| tristate "Radisys 82600 embedded chipset" | |
| depends on EDAC_MM_EDAC && PCI && X86_32 | |
| help | |
| Support for error detection and correction on the Radisys | |
| 82600 embedded chipset. | |
| config EDAC_I5000 | |
| tristate "Intel Greencreek/Blackford chipset" | |
| depends on EDAC_MM_EDAC && X86 && PCI | |
| help | |
| Support for error detection and correction the Intel | |
| Greekcreek/Blackford chipsets. | |
| config EDAC_I5100 | |
| tristate "Intel San Clemente MCH" | |
| depends on EDAC_MM_EDAC && X86 && PCI | |
| help | |
| Support for error detection and correction the Intel | |
| San Clemente MCH. | |
| config EDAC_MPC85XX | |
| tristate "Freescale MPC85xx" | |
| depends on EDAC_MM_EDAC && FSL_SOC && MPC85xx | |
| help | |
| Support for error detection and correction on the Freescale | |
| MPC8560, MPC8540, MPC8548 | |
| config EDAC_MV64X60 | |
| tristate "Marvell MV64x60" | |
| depends on EDAC_MM_EDAC && MV64X60 | |
| help | |
| Support for error detection and correction on the Marvell | |
| MV64360 and MV64460 chipsets. | |
| config EDAC_PASEMI | |
| tristate "PA Semi PWRficient" | |
| depends on EDAC_MM_EDAC && PCI | |
| depends on PPC_PASEMI | |
| help | |
| Support for error detection and correction on PA Semi | |
| PWRficient. | |
| config EDAC_CELL | |
| tristate "Cell Broadband Engine memory controller" | |
| depends on EDAC_MM_EDAC && PPC_CELL_COMMON | |
| help | |
| Support for error detection and correction on the | |
| Cell Broadband Engine internal memory controller | |
| on platform without a hypervisor | |
| config EDAC_PPC4XX | |
| tristate "PPC4xx IBM DDR2 Memory Controller" | |
| depends on EDAC_MM_EDAC && 4xx | |
| help | |
| This enables support for EDAC on the ECC memory used | |
| with the IBM DDR2 memory controller found in various | |
| PowerPC 4xx embedded processors such as the 405EX[r], | |
| 440SP, 440SPe, 460EX, 460GT and 460SX. | |
| config EDAC_AMD8131 | |
| tristate "AMD8131 HyperTransport PCI-X Tunnel" | |
| depends on EDAC_MM_EDAC && PCI | |
| help | |
| Support for error detection and correction on the | |
| AMD8131 HyperTransport PCI-X Tunnel chip. | |
| config EDAC_AMD8111 | |
| tristate "AMD8111 HyperTransport I/O Hub" | |
| depends on EDAC_MM_EDAC && PCI | |
| help | |
| Support for error detection and correction on the | |
| AMD8111 HyperTransport I/O Hub chip. | |
| endif # EDAC |