| # | |
| # DMA engine configuration | |
| # | |
| menuconfig DMADEVICES | |
| bool "DMA Engine support" | |
| depends on !HIGHMEM64G && HAS_DMA | |
| help | |
| DMA engines can do asynchronous data transfers without | |
| involving the host CPU. Currently, this framework can be | |
| used to offload memory copies in the network stack and | |
| RAID operations in the MD driver. This menu only presents | |
| DMA Device drivers supported by the configured arch, it may | |
| be empty in some cases. | |
| if DMADEVICES | |
| comment "DMA Devices" | |
| config INTEL_IOATDMA | |
| tristate "Intel I/OAT DMA support" | |
| depends on PCI && X86 | |
| select DMA_ENGINE | |
| select DCA | |
| help | |
| Enable support for the Intel(R) I/OAT DMA engine present | |
| in recent Intel Xeon chipsets. | |
| Say Y here if you have such a chipset. | |
| If unsure, say N. | |
| config INTEL_IOP_ADMA | |
| tristate "Intel IOP ADMA support" | |
| depends on ARCH_IOP32X || ARCH_IOP33X || ARCH_IOP13XX | |
| select DMA_ENGINE | |
| help | |
| Enable support for the Intel(R) IOP Series RAID engines. | |
| config DW_DMAC | |
| tristate "Synopsys DesignWare AHB DMA support" | |
| depends on AVR32 | |
| select DMA_ENGINE | |
| default y if CPU_AT32AP7000 | |
| help | |
| Support the Synopsys DesignWare AHB DMA controller. This | |
| can be integrated in chips such as the Atmel AT32ap7000. | |
| config FSL_DMA | |
| tristate "Freescale Elo and Elo Plus DMA support" | |
| depends on FSL_SOC | |
| select DMA_ENGINE | |
| ---help--- | |
| Enable support for the Freescale Elo and Elo Plus DMA controllers. | |
| The Elo is the DMA controller on some 82xx and 83xx parts, and the | |
| Elo Plus is the DMA controller on 85xx and 86xx parts. | |
| config MV_XOR | |
| bool "Marvell XOR engine support" | |
| depends on PLAT_ORION | |
| select DMA_ENGINE | |
| ---help--- | |
| Enable support for the Marvell XOR engine. | |
| config MX3_IPU | |
| bool "MX3x Image Processing Unit support" | |
| depends on ARCH_MX3 | |
| select DMA_ENGINE | |
| default y | |
| help | |
| If you plan to use the Image Processing unit in the i.MX3x, say | |
| Y here. If unsure, select Y. | |
| config MX3_IPU_IRQS | |
| int "Number of dynamically mapped interrupts for IPU" | |
| depends on MX3_IPU | |
| range 2 137 | |
| default 4 | |
| help | |
| Out of 137 interrupt sources on i.MX31 IPU only very few are used. | |
| To avoid bloating the irq_desc[] array we allocate a sufficient | |
| number of IRQ slots and map them dynamically to specific sources. | |
| config DMA_ENGINE | |
| bool | |
| comment "DMA Clients" | |
| depends on DMA_ENGINE | |
| config NET_DMA | |
| bool "Network: TCP receive copy offload" | |
| depends on DMA_ENGINE && NET | |
| default (INTEL_IOATDMA || FSL_DMA) | |
| help | |
| This enables the use of DMA engines in the network stack to | |
| offload receive copy-to-user operations, freeing CPU cycles. | |
| Say Y here if you enabled INTEL_IOATDMA or FSL_DMA, otherwise | |
| say N. | |
| config ASYNC_TX_DMA | |
| bool "Async_tx: Offload support for the async_tx api" | |
| depends on DMA_ENGINE | |
| help | |
| This allows the async_tx api to take advantage of offload engines for | |
| memcpy, memset, xor, and raid6 p+q operations. If your platform has | |
| a dma engine that can perform raid operations and you have enabled | |
| MD_RAID456 say Y. | |
| If unsure, say N. | |
| config DMATEST | |
| tristate "DMA Test client" | |
| depends on DMA_ENGINE | |
| help | |
| Simple DMA test client. Say N unless you're debugging a | |
| DMA Device driver. | |
| endif |