| /* SPDX-License-Identifier: GPL-2.0 |
| * |
| * Copyright 2016-2018 HabanaLabs, Ltd. |
| * All Rights Reserved. |
| * |
| */ |
| |
| /************************************ |
| ** This is an auto-generated file ** |
| ** DO NOT EDIT BELOW ** |
| ************************************/ |
| |
| #ifndef ASIC_REG_TPC0_CMDQ_REGS_H_ |
| #define ASIC_REG_TPC0_CMDQ_REGS_H_ |
| |
| /* |
| ***************************************** |
| * TPC0_CMDQ (Prototype: CMDQ) |
| ***************************************** |
| */ |
| |
| #define mmTPC0_CMDQ_GLBL_CFG0 0xE09000 |
| |
| #define mmTPC0_CMDQ_GLBL_CFG1 0xE09004 |
| |
| #define mmTPC0_CMDQ_GLBL_PROT 0xE09008 |
| |
| #define mmTPC0_CMDQ_GLBL_ERR_CFG 0xE0900C |
| |
| #define mmTPC0_CMDQ_GLBL_ERR_ADDR_LO 0xE09010 |
| |
| #define mmTPC0_CMDQ_GLBL_ERR_ADDR_HI 0xE09014 |
| |
| #define mmTPC0_CMDQ_GLBL_ERR_WDATA 0xE09018 |
| |
| #define mmTPC0_CMDQ_GLBL_SECURE_PROPS 0xE0901C |
| |
| #define mmTPC0_CMDQ_GLBL_NON_SECURE_PROPS 0xE09020 |
| |
| #define mmTPC0_CMDQ_GLBL_STS0 0xE09024 |
| |
| #define mmTPC0_CMDQ_GLBL_STS1 0xE09028 |
| |
| #define mmTPC0_CMDQ_CQ_CFG0 0xE090B0 |
| |
| #define mmTPC0_CMDQ_CQ_CFG1 0xE090B4 |
| |
| #define mmTPC0_CMDQ_CQ_ARUSER 0xE090B8 |
| |
| #define mmTPC0_CMDQ_CQ_PTR_LO 0xE090C0 |
| |
| #define mmTPC0_CMDQ_CQ_PTR_HI 0xE090C4 |
| |
| #define mmTPC0_CMDQ_CQ_TSIZE 0xE090C8 |
| |
| #define mmTPC0_CMDQ_CQ_CTL 0xE090CC |
| |
| #define mmTPC0_CMDQ_CQ_PTR_LO_STS 0xE090D4 |
| |
| #define mmTPC0_CMDQ_CQ_PTR_HI_STS 0xE090D8 |
| |
| #define mmTPC0_CMDQ_CQ_TSIZE_STS 0xE090DC |
| |
| #define mmTPC0_CMDQ_CQ_CTL_STS 0xE090E0 |
| |
| #define mmTPC0_CMDQ_CQ_STS0 0xE090E4 |
| |
| #define mmTPC0_CMDQ_CQ_STS1 0xE090E8 |
| |
| #define mmTPC0_CMDQ_CQ_RD_RATE_LIM_EN 0xE090F0 |
| |
| #define mmTPC0_CMDQ_CQ_RD_RATE_LIM_RST_TOKEN 0xE090F4 |
| |
| #define mmTPC0_CMDQ_CQ_RD_RATE_LIM_SAT 0xE090F8 |
| |
| #define mmTPC0_CMDQ_CQ_RD_RATE_LIM_TOUT 0xE090FC |
| |
| #define mmTPC0_CMDQ_CQ_IFIFO_CNT 0xE09108 |
| |
| #define mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_LO 0xE09120 |
| |
| #define mmTPC0_CMDQ_CP_MSG_BASE0_ADDR_HI 0xE09124 |
| |
| #define mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_LO 0xE09128 |
| |
| #define mmTPC0_CMDQ_CP_MSG_BASE1_ADDR_HI 0xE0912C |
| |
| #define mmTPC0_CMDQ_CP_MSG_BASE2_ADDR_LO 0xE09130 |
| |
| #define mmTPC0_CMDQ_CP_MSG_BASE2_ADDR_HI 0xE09134 |
| |
| #define mmTPC0_CMDQ_CP_MSG_BASE3_ADDR_LO 0xE09138 |
| |
| #define mmTPC0_CMDQ_CP_MSG_BASE3_ADDR_HI 0xE0913C |
| |
| #define mmTPC0_CMDQ_CP_LDMA_TSIZE_OFFSET 0xE09140 |
| |
| #define mmTPC0_CMDQ_CP_LDMA_SRC_BASE_LO_OFFSET 0xE09144 |
| |
| #define mmTPC0_CMDQ_CP_LDMA_SRC_BASE_HI_OFFSET 0xE09148 |
| |
| #define mmTPC0_CMDQ_CP_LDMA_DST_BASE_LO_OFFSET 0xE0914C |
| |
| #define mmTPC0_CMDQ_CP_LDMA_DST_BASE_HI_OFFSET 0xE09150 |
| |
| #define mmTPC0_CMDQ_CP_LDMA_COMMIT_OFFSET 0xE09154 |
| |
| #define mmTPC0_CMDQ_CP_FENCE0_RDATA 0xE09158 |
| |
| #define mmTPC0_CMDQ_CP_FENCE1_RDATA 0xE0915C |
| |
| #define mmTPC0_CMDQ_CP_FENCE2_RDATA 0xE09160 |
| |
| #define mmTPC0_CMDQ_CP_FENCE3_RDATA 0xE09164 |
| |
| #define mmTPC0_CMDQ_CP_FENCE0_CNT 0xE09168 |
| |
| #define mmTPC0_CMDQ_CP_FENCE1_CNT 0xE0916C |
| |
| #define mmTPC0_CMDQ_CP_FENCE2_CNT 0xE09170 |
| |
| #define mmTPC0_CMDQ_CP_FENCE3_CNT 0xE09174 |
| |
| #define mmTPC0_CMDQ_CP_STS 0xE09178 |
| |
| #define mmTPC0_CMDQ_CP_CURRENT_INST_LO 0xE0917C |
| |
| #define mmTPC0_CMDQ_CP_CURRENT_INST_HI 0xE09180 |
| |
| #define mmTPC0_CMDQ_CP_BARRIER_CFG 0xE09184 |
| |
| #define mmTPC0_CMDQ_CP_DBG_0 0xE09188 |
| |
| #define mmTPC0_CMDQ_CQ_BUF_ADDR 0xE09308 |
| |
| #define mmTPC0_CMDQ_CQ_BUF_RDATA 0xE0930C |
| |
| #endif /* ASIC_REG_TPC0_CMDQ_REGS_H_ */ |