| [ |
| { |
| "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stores) hitting load buffers. Machine clears can have a significant performance impact if they are happening frequently.", |
| "EventCode": "0xC3", |
| "Counter": "0,1,2,3", |
| "UMask": "0x2", |
| "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "PEBS": "2", |
| "EventCode": "0xCD", |
| "MSRValue": "0x4", |
| "Counter": "3", |
| "UMask": "0x1", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", |
| "MSRIndex": "0x3F6", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Loads with latency value being above 4 .", |
| "TakenAlone": "1", |
| "CounterHTOff": "3" |
| }, |
| { |
| "PEBS": "2", |
| "EventCode": "0xCD", |
| "MSRValue": "0x8", |
| "Counter": "3", |
| "UMask": "0x1", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", |
| "MSRIndex": "0x3F6", |
| "SampleAfterValue": "50021", |
| "BriefDescription": "Loads with latency value being above 8.", |
| "TakenAlone": "1", |
| "CounterHTOff": "3" |
| }, |
| { |
| "PEBS": "2", |
| "EventCode": "0xCD", |
| "MSRValue": "0x10", |
| "Counter": "3", |
| "UMask": "0x1", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", |
| "MSRIndex": "0x3F6", |
| "SampleAfterValue": "20011", |
| "BriefDescription": "Loads with latency value being above 16.", |
| "TakenAlone": "1", |
| "CounterHTOff": "3" |
| }, |
| { |
| "PEBS": "2", |
| "EventCode": "0xCD", |
| "MSRValue": "0x20", |
| "Counter": "3", |
| "UMask": "0x1", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", |
| "MSRIndex": "0x3F6", |
| "SampleAfterValue": "100007", |
| "BriefDescription": "Loads with latency value being above 32.", |
| "TakenAlone": "1", |
| "CounterHTOff": "3" |
| }, |
| { |
| "PEBS": "2", |
| "EventCode": "0xCD", |
| "MSRValue": "0x40", |
| "Counter": "3", |
| "UMask": "0x1", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", |
| "MSRIndex": "0x3F6", |
| "SampleAfterValue": "2003", |
| "BriefDescription": "Loads with latency value being above 64.", |
| "TakenAlone": "1", |
| "CounterHTOff": "3" |
| }, |
| { |
| "PEBS": "2", |
| "EventCode": "0xCD", |
| "MSRValue": "0x80", |
| "Counter": "3", |
| "UMask": "0x1", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", |
| "MSRIndex": "0x3F6", |
| "SampleAfterValue": "1009", |
| "BriefDescription": "Loads with latency value being above 128.", |
| "TakenAlone": "1", |
| "CounterHTOff": "3" |
| }, |
| { |
| "PEBS": "2", |
| "EventCode": "0xCD", |
| "MSRValue": "0x100", |
| "Counter": "3", |
| "UMask": "0x1", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", |
| "MSRIndex": "0x3F6", |
| "SampleAfterValue": "503", |
| "BriefDescription": "Loads with latency value being above 256.", |
| "TakenAlone": "1", |
| "CounterHTOff": "3" |
| }, |
| { |
| "PEBS": "2", |
| "EventCode": "0xCD", |
| "MSRValue": "0x200", |
| "Counter": "3", |
| "UMask": "0x1", |
| "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", |
| "MSRIndex": "0x3F6", |
| "SampleAfterValue": "101", |
| "BriefDescription": "Loads with latency value being above 512.", |
| "TakenAlone": "1", |
| "CounterHTOff": "3" |
| }, |
| { |
| "PEBS": "2", |
| "EventCode": "0xCD", |
| "Counter": "3", |
| "UMask": "0x2", |
| "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "Sample stores and collect precise store operation via PEBS record. PMC3 only. (Precise Event - PEBS).", |
| "PRECISE_STORE": "1", |
| "TakenAlone": "1", |
| "CounterHTOff": "3" |
| }, |
| { |
| "EventCode": "0x05", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "EventName": "MISALIGN_MEM_REF.LOADS", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache.", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x05", |
| "Counter": "0,1,2,3", |
| "UMask": "0x2", |
| "EventName": "MISALIGN_MEM_REF.STORES", |
| "SampleAfterValue": "2000003", |
| "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache.", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x3fffc20004", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts all demand code reads that miss the LLC", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x600400004", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from local dram", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x67f800004", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_DRAM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts all demand code reads that miss the LLC and the data returned from remote dram", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x87f820004", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_FORWARD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts all demand code reads that miss the LLC and the data forwarded from remote cache", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x107fc00004", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts all demand code reads that miss the LLC the data is found in M state in remote cache and forwarded from there", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x67fc00001", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote & local dram", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x3fffc20001", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts demand data reads that miss in the LLC", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x600400001", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from local dram", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x67f800001", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_DRAM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts demand data reads that miss the LLC and the data returned from remote dram", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x87f820001", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts demand data reads that miss the LLC and the data forwarded from remote cache", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x107fc00001", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts demand data reads that miss the LLC the data is found in M state in remote cache and forwarded from there", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x3fffc20040", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) code reads that miss the LLC and the data returned from remote & local dram", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x67fc00010", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_DRAM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote & local dram", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x3fffc20010", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss in the LLC", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x600400010", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.LOCAL_DRAM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from local dram", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x67f800010", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_DRAM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data returned from remote dram", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x87f820010", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC and the data forwarded from remote cache", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x107fc00010", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads that miss the LLC the data is found in M state in remote cache and forwarded from there", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x3fffc20200", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that miss in the LLC", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x3fffc20080", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts prefetch (that bring data to LLC only) data reads that hit in the LLC and the snoops sent to sibling cores return clean response", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x600400077", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.LOCAL_DRAM", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "Counts all local dram accesses for all demand and L2 prefetches. LLC prefetches are excluded.", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x3FFFC20077", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "This event counts all LLC misses for all demand and L2 prefetches. LLC prefetches are excluded.", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "MSRValue": "0x187FC20077", |
| "Counter": "0,1,2,3", |
| "UMask": "0x1", |
| "Offcore": "1", |
| "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.REMOTE_HITM_HIT_FORWARD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "SampleAfterValue": "100003", |
| "BriefDescription": "This event counts all remote cache-to-cache transfers (includes HITM and HIT-Forward) for all demand and L2 prefetches. LLC prefetches are excluded.", |
| "CounterHTOff": "0,1,2,3" |
| } |
| ] |
