# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/intel,ixp4xx-expansion-bus-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Intel IXP4xx Expansion Bus Controller

description: |
  The IXP4xx expansion bus controller handles access to devices on the
  memory-mapped expansion bus on the Intel IXP4xx family of system on chips,
  including IXP42x, IXP43x, IXP45x and IXP46x.

maintainers:
  - Linus Walleij <linus.walleij@linaro.org>

properties:
  $nodename:
    pattern: '^bus@[0-9a-f]+$'

  compatible:
    items:
      - enum:
          - intel,ixp42x-expansion-bus-controller
          - intel,ixp43x-expansion-bus-controller
          - intel,ixp45x-expansion-bus-controller
          - intel,ixp46x-expansion-bus-controller
      - const: syscon

  reg:
    description: Control registers for the expansion bus, these are not
      inside the memory range handled by the expansion bus.
    maxItems: 1

  native-endian:
    $ref: /schemas/types.yaml#/definitions/flag
    description: The IXP4xx has a peculiar MMIO access scheme, as it changes
      the access pattern for words (swizzling) on the bus depending on whether
      the SoC is running in big-endian or little-endian mode. Thus the
      registers must always be accessed using native endianness.

  "#address-cells":
    description: |
      The first cell is the chip select number.
      The second cell is the address offset within the bank.
    const: 2

  "#size-cells":
    const: 1

  ranges: true
  dma-ranges: true

patternProperties:
  "^.*@[0-7],[0-9a-f]+$":
    description: Devices attached to chip selects are represented as
      subnodes.
    type: object
    $ref: /schemas/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml#

required:
  - compatible
  - reg
  - native-endian
  - "#address-cells"
  - "#size-cells"
  - ranges
  - dma-ranges

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>
    bus@50000000 {
        compatible = "intel,ixp42x-expansion-bus-controller", "syscon";
        reg = <0xc4000000 0x28>;
        native-endian;
        #address-cells = <2>;
        #size-cells = <1>;
        ranges = <0 0x0 0x50000000 0x01000000>,
                 <1 0x0 0x51000000 0x01000000>;
        dma-ranges = <0 0x0 0x50000000 0x01000000>,
                     <1 0x0 0x51000000 0x01000000>;
        flash@0,0 {
            compatible = "intel,ixp4xx-flash", "cfi-flash";
            bank-width = <2>;
            reg = <0 0x00000000 0x1000000>;
            intel,ixp4xx-eb-t3 = <3>;
            intel,ixp4xx-eb-cycle-type = <0>;
            intel,ixp4xx-eb-byte-access-on-halfword = <1>;
            intel,ixp4xx-eb-write-enable = <1>;
            intel,ixp4xx-eb-byte-access = <0>;
        };
        serial@1,0 {
            compatible = "exar,xr16l2551", "ns8250";
            reg = <1 0x00000000 0x10>;
            interrupt-parent = <&gpio0>;
            interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
            clock-frequency = <1843200>;
            intel,ixp4xx-eb-t3 = <3>;
            intel,ixp4xx-eb-cycle-type = <1>;
            intel,ixp4xx-eb-write-enable = <1>;
            intel,ixp4xx-eb-byte-access = <1>;
        };
    };