# SPDX-License-Identifier: GPL-2.0-only
if ARCH_TEGRA

# 32-bit ARM SoCs
if ARM

config ARCH_TEGRA_2x_SOC
	bool "Enable support for Tegra20 family"
	select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
	select ARM_ERRATA_720789
	select ARM_ERRATA_754327 if SMP
	select ARM_ERRATA_764369 if SMP
	select PINCTRL_TEGRA20
	select PL310_ERRATA_727915 if CACHE_L2X0
	select PL310_ERRATA_769419 if CACHE_L2X0
	select SOC_TEGRA_FLOWCTRL
	select SOC_TEGRA_PMC
	select SOC_TEGRA20_VOLTAGE_COUPLER if REGULATOR
	select TEGRA_TIMER
	help
	  Support for NVIDIA Tegra AP20 and T20 processors, based on the
	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller

config ARCH_TEGRA_3x_SOC
	bool "Enable support for Tegra30 family"
	select ARM_ERRATA_754322
	select ARM_ERRATA_764369 if SMP
	select PINCTRL_TEGRA30
	select PL310_ERRATA_769419 if CACHE_L2X0
	select SOC_TEGRA_FLOWCTRL
	select SOC_TEGRA_PMC
	select SOC_TEGRA30_VOLTAGE_COUPLER if REGULATOR
	select TEGRA_TIMER
	help
	  Support for NVIDIA Tegra T30 processor family, based on the
	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller

config ARCH_TEGRA_114_SOC
	bool "Enable support for Tegra114 family"
	select ARM_ERRATA_798181 if SMP
	select HAVE_ARM_ARCH_TIMER
	select PINCTRL_TEGRA114
	select SOC_TEGRA_FLOWCTRL
	select SOC_TEGRA_PMC
	select TEGRA_TIMER
	help
	  Support for NVIDIA Tegra T114 processor family, based on the
	  ARM CortexA15MP CPU

config ARCH_TEGRA_124_SOC
	bool "Enable support for Tegra124 family"
	select HAVE_ARM_ARCH_TIMER
	select PINCTRL_TEGRA124
	select SOC_TEGRA_FLOWCTRL
	select SOC_TEGRA_PMC
	select TEGRA_TIMER
	help
	  Support for NVIDIA Tegra T124 processor family, based on the
	  ARM CortexA15MP CPU

endif

# 64-bit ARM SoCs
if ARM64

config ARCH_TEGRA_132_SOC
	bool "NVIDIA Tegra132 SoC"
	select PINCTRL_TEGRA124
	select SOC_TEGRA_FLOWCTRL
	select SOC_TEGRA_PMC
	help
	  Enable support for NVIDIA Tegra132 SoC, based on the Denver
	  ARMv8 CPU.  The Tegra132 SoC is similar to the Tegra124 SoC,
	  but contains an NVIDIA Denver CPU complex in place of
	  Tegra124's "4+1" Cortex-A15 CPU complex.

config ARCH_TEGRA_210_SOC
	bool "NVIDIA Tegra210 SoC"
	select PINCTRL_TEGRA210
	select SOC_TEGRA_FLOWCTRL
	select SOC_TEGRA_PMC
	select TEGRA_TIMER
	help
	  Enable support for the NVIDIA Tegra210 SoC. Also known as Tegra X1,
	  the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53
	  cores in a switched configuration. It features a GPU of the Maxwell
	  architecture with support for DX11, SM4, OpenGL 4.5, OpenGL ES 3.1
	  and providing 256 CUDA cores. It supports hardware-accelerated en-
	  and decoding of various video standards including H.265, H.264 and
	  VP8 at 4K resolution and up to 60 fps.

	  Besides the multimedia features it also comes with a variety of I/O
	  controllers, such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to
	  name only a few.

config ARCH_TEGRA_186_SOC
	bool "NVIDIA Tegra186 SoC"
	depends on !CPU_BIG_ENDIAN
	select MAILBOX
	select TEGRA_BPMP
	select TEGRA_HSP_MBOX
	select TEGRA_IVC
	select SOC_TEGRA_PMC
	help
	  Enable support for the NVIDIA Tegar186 SoC. The Tegra186 features a
	  combination of Denver and Cortex-A57 CPU cores and a GPU based on
	  the Pascal architecture. It contains an ADSP with a Cortex-A9 CPU
	  used for audio processing, hardware video encoders/decoders with
	  multi-format support, ISP for image capture processing and BPMP for
	  power management.

config ARCH_TEGRA_194_SOC
	bool "NVIDIA Tegra194 SoC"
	depends on !CPU_BIG_ENDIAN
	select MAILBOX
	select PINCTRL_TEGRA194
	select TEGRA_BPMP
	select TEGRA_HSP_MBOX
	select TEGRA_IVC
	select SOC_TEGRA_PMC
	help
	  Enable support for the NVIDIA Tegra194 SoC.

config ARCH_TEGRA_234_SOC
	bool "NVIDIA Tegra234 SoC"
	depends on !CPU_BIG_ENDIAN
	select MAILBOX
	select TEGRA_BPMP
	select TEGRA_HSP_MBOX
	select TEGRA_IVC
	select SOC_TEGRA_PMC
	help
	  Enable support for the NVIDIA Tegra234 SoC.

endif
endif

config SOC_TEGRA_FUSE
	def_bool y
	depends on ARCH_TEGRA
	select SOC_BUS

config SOC_TEGRA_FLOWCTRL
	bool

config SOC_TEGRA_PMC
	bool
	select GENERIC_PINCONF
	select IRQ_DOMAIN_HIERARCHY
	select PM_OPP
	select PM_GENERIC_DOMAINS
	select REGMAP

config SOC_TEGRA_POWERGATE_BPMP
	def_bool y
	depends on PM_GENERIC_DOMAINS
	depends on TEGRA_BPMP

config SOC_TEGRA20_VOLTAGE_COUPLER
	bool "Voltage scaling support for Tegra20 SoCs"
	depends on ARCH_TEGRA_2x_SOC || COMPILE_TEST
	depends on REGULATOR

config SOC_TEGRA30_VOLTAGE_COUPLER
	bool "Voltage scaling support for Tegra30 SoCs"
	depends on ARCH_TEGRA_3x_SOC || COMPILE_TEST
	depends on REGULATOR

config SOC_TEGRA_CBB
	tristate "Tegra driver to handle error from CBB"
	depends on ARCH_TEGRA_194_SOC || ARCH_TEGRA_234_SOC
	default y
	help
	  Support for handling error from Tegra Control Backbone(CBB).
	  This driver handles the errors from CBB and prints debug
	  information about the failed transactions.