// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
/*
 * Device Tree Source for the RZ/Five and RZ/G2UL SoCs
 *
 * Copyright (C) 2022 Renesas Electronics Corp.
 */

#include <dt-bindings/clock/r9a07g043-cpg.h>

/ {
	compatible = "renesas,r9a07g043";
	#address-cells = <2>;
	#size-cells = <2>;

	audio_clk1: audio1-clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* This value must be overridden by boards that provide it */
		clock-frequency = <0>;
	};

	audio_clk2: audio2-clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* This value must be overridden by boards that provide it */
		clock-frequency = <0>;
	};

	/* External CAN clock - to be overridden by boards that provide it */
	can_clk: can-clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <0>;
	};

	/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
	extal_clk: extal-clk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		/* This value must be overridden by the board */
		clock-frequency = <0>;
	};

	cluster0_opp: opp-table-0 {
		compatible = "operating-points-v2";
		opp-shared;

		opp-125000000 {
			opp-hz = /bits/ 64 <125000000>;
			opp-microvolt = <1100000>;
			clock-latency-ns = <300000>;
		};
		opp-250000000 {
			opp-hz = /bits/ 64 <250000000>;
			opp-microvolt = <1100000>;
			clock-latency-ns = <300000>;
		};
		opp-500000000 {
			opp-hz = /bits/ 64 <500000000>;
			opp-microvolt = <1100000>;
			clock-latency-ns = <300000>;
		};
		opp-1000000000 {
			opp-hz = /bits/ 64 <1000000000>;
			opp-microvolt = <1100000>;
			clock-latency-ns = <300000>;
			opp-suspend;
		};
	};

	soc: soc {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		ssi0: ssi@10049c00 {
			compatible = "renesas,r9a07g043-ssi",
				     "renesas,rz-ssi";
			reg = <0 0x10049c00 0 0x400>;
			interrupts = <SOC_PERIPHERAL_IRQ(326) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(327) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(328) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(329) IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
			clocks = <&cpg CPG_MOD R9A07G043_SSI0_PCLK2>,
				 <&cpg CPG_MOD R9A07G043_SSI0_PCLK_SFR>,
				 <&audio_clk1>, <&audio_clk2>;
			clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
			resets = <&cpg R9A07G043_SSI0_RST_M2_REG>;
			dmas = <&dmac 0x2655>, <&dmac 0x2656>;
			dma-names = "tx", "rx";
			power-domains = <&cpg>;
			#sound-dai-cells = <0>;
			status = "disabled";
		};

		ssi1: ssi@1004a000 {
			compatible = "renesas,r9a07g043-ssi",
				     "renesas,rz-ssi";
			reg = <0 0x1004a000 0 0x400>;
			interrupts = <SOC_PERIPHERAL_IRQ(330) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(331) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(332) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(333) IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
			clocks = <&cpg CPG_MOD R9A07G043_SSI1_PCLK2>,
				 <&cpg CPG_MOD R9A07G043_SSI1_PCLK_SFR>,
				 <&audio_clk1>, <&audio_clk2>;
			clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
			resets = <&cpg R9A07G043_SSI1_RST_M2_REG>;
			dmas = <&dmac 0x2659>, <&dmac 0x265a>;
			dma-names = "tx", "rx";
			power-domains = <&cpg>;
			#sound-dai-cells = <0>;
			status = "disabled";
		};

		ssi2: ssi@1004a400 {
			compatible = "renesas,r9a07g043-ssi",
				     "renesas,rz-ssi";
			reg = <0 0x1004a400 0 0x400>;
			interrupts = <SOC_PERIPHERAL_IRQ(334) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(335) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(336) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(337) IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
			clocks = <&cpg CPG_MOD R9A07G043_SSI2_PCLK2>,
				 <&cpg CPG_MOD R9A07G043_SSI2_PCLK_SFR>,
				 <&audio_clk1>, <&audio_clk2>;
			clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
			resets = <&cpg R9A07G043_SSI2_RST_M2_REG>;
			dmas = <&dmac 0x265f>;
			dma-names = "rt";
			power-domains = <&cpg>;
			#sound-dai-cells = <0>;
			status = "disabled";
		};

		ssi3: ssi@1004a800 {
			compatible = "renesas,r9a07g043-ssi",
				     "renesas,rz-ssi";
			reg = <0 0x1004a800 0 0x400>;
			interrupts = <SOC_PERIPHERAL_IRQ(338) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(339) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(340) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(341) IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
			clocks = <&cpg CPG_MOD R9A07G043_SSI3_PCLK2>,
				 <&cpg CPG_MOD R9A07G043_SSI3_PCLK_SFR>,
				 <&audio_clk1>, <&audio_clk2>;
			clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
			resets = <&cpg R9A07G043_SSI3_RST_M2_REG>;
			dmas = <&dmac 0x2661>, <&dmac 0x2662>;
			dma-names = "tx", "rx";
			power-domains = <&cpg>;
			#sound-dai-cells = <0>;
			status = "disabled";
		};

		spi0: spi@1004ac00 {
			compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz";
			reg = <0 0x1004ac00 0 0x400>;
			interrupts = <SOC_PERIPHERAL_IRQ(415) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(413) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(414) IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error", "rx", "tx";
			clocks = <&cpg CPG_MOD R9A07G043_RSPI0_CLKB>;
			resets = <&cpg R9A07G043_RSPI0_RST>;
			dmas = <&dmac 0x2e95>, <&dmac 0x2e96>;
			dma-names = "tx", "rx";
			power-domains = <&cpg>;
			num-cs = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi1: spi@1004b000 {
			compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz";
			reg = <0 0x1004b000 0 0x400>;
			interrupts = <SOC_PERIPHERAL_IRQ(418) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(416) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(417) IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error", "rx", "tx";
			clocks = <&cpg CPG_MOD R9A07G043_RSPI1_CLKB>;
			resets = <&cpg R9A07G043_RSPI1_RST>;
			dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>;
			dma-names = "tx", "rx";
			power-domains = <&cpg>;
			num-cs = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		spi2: spi@1004b400 {
			compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz";
			reg = <0 0x1004b400 0 0x400>;
			interrupts = <SOC_PERIPHERAL_IRQ(421) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(419) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(420) IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "error", "rx", "tx";
			clocks = <&cpg CPG_MOD R9A07G043_RSPI2_CLKB>;
			resets = <&cpg R9A07G043_RSPI2_RST>;
			dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>;
			dma-names = "tx", "rx";
			power-domains = <&cpg>;
			num-cs = <1>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		scif0: serial@1004b800 {
			compatible = "renesas,scif-r9a07g043",
				     "renesas,scif-r9a07g044";
			reg = <0 0x1004b800 0 0x400>;
			interrupts = <SOC_PERIPHERAL_IRQ(380) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(382) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(383) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(381) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(384) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(384) IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "eri", "rxi", "txi",
					  "bri", "dri", "tei";
			clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
			clock-names = "fck";
			power-domains = <&cpg>;
			resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
			status = "disabled";
		};

		scif1: serial@1004bc00 {
			compatible = "renesas,scif-r9a07g043",
				     "renesas,scif-r9a07g044";
			reg = <0 0x1004bc00 0 0x400>;
			interrupts = <SOC_PERIPHERAL_IRQ(385) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(387) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(388) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(386) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(389) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(389) IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "eri", "rxi", "txi",
					  "bri", "dri", "tei";
			clocks = <&cpg CPG_MOD R9A07G043_SCIF1_CLK_PCK>;
			clock-names = "fck";
			power-domains = <&cpg>;
			resets = <&cpg R9A07G043_SCIF1_RST_SYSTEM_N>;
			status = "disabled";
		};

		scif2: serial@1004c000 {
			compatible = "renesas,scif-r9a07g043",
				     "renesas,scif-r9a07g044";
			reg = <0 0x1004c000 0 0x400>;
			interrupts = <SOC_PERIPHERAL_IRQ(390) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(392) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(393) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(391) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(394) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(394) IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "eri", "rxi", "txi",
					  "bri", "dri", "tei";
			clocks = <&cpg CPG_MOD R9A07G043_SCIF2_CLK_PCK>;
			clock-names = "fck";
			power-domains = <&cpg>;
			resets = <&cpg R9A07G043_SCIF2_RST_SYSTEM_N>;
			status = "disabled";
		};

		scif3: serial@1004c400 {
			compatible = "renesas,scif-r9a07g043",
				     "renesas,scif-r9a07g044";
			reg = <0 0x1004c400 0 0x400>;
			interrupts = <SOC_PERIPHERAL_IRQ(395) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(397) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(398) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(396) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(399) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(399) IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "eri", "rxi", "txi",
					  "bri", "dri", "tei";
			clocks = <&cpg CPG_MOD R9A07G043_SCIF3_CLK_PCK>;
			clock-names = "fck";
			power-domains = <&cpg>;
			resets = <&cpg R9A07G043_SCIF3_RST_SYSTEM_N>;
			status = "disabled";
		};

		scif4: serial@1004c800 {
			compatible = "renesas,scif-r9a07g043",
				     "renesas,scif-r9a07g044";
			reg = <0 0x1004c800 0 0x400>;
			interrupts = <SOC_PERIPHERAL_IRQ(400) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(402) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(403) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(401) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(404) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(404) IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "eri", "rxi", "txi",
					  "bri", "dri", "tei";
			clocks = <&cpg CPG_MOD R9A07G043_SCIF4_CLK_PCK>;
			clock-names = "fck";
			power-domains = <&cpg>;
			resets = <&cpg R9A07G043_SCIF4_RST_SYSTEM_N>;
			status = "disabled";
		};

		sci0: serial@1004d000 {
			compatible = "renesas,r9a07g043-sci", "renesas,sci";
			reg = <0 0x1004d000 0 0x400>;
			interrupts = <SOC_PERIPHERAL_IRQ(405) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(406) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(407) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(408) IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "eri", "rxi", "txi", "tei";
			clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>;
			clock-names = "fck";
			power-domains = <&cpg>;
			resets = <&cpg R9A07G043_SCI0_RST>;
			status = "disabled";
		};

		sci1: serial@1004d400 {
			compatible = "renesas,r9a07g043-sci", "renesas,sci";
			reg = <0 0x1004d400 0 0x400>;
			interrupts = <SOC_PERIPHERAL_IRQ(409) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(410) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(411) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(412) IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "eri", "rxi", "txi", "tei";
			clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>;
			clock-names = "fck";
			power-domains = <&cpg>;
			resets = <&cpg R9A07G043_SCI1_RST>;
			status = "disabled";
		};

		canfd: can@10050000 {
			compatible = "renesas,r9a07g043-canfd", "renesas,rzg2l-canfd";
			reg = <0 0x10050000 0 0x8000>;
			interrupts = <SOC_PERIPHERAL_IRQ(426) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(427) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(422) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(424) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(428) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(423) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(425) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(429) IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "g_err", "g_recc",
					  "ch0_err", "ch0_rec", "ch0_trx",
					  "ch1_err", "ch1_rec", "ch1_trx";
			clocks = <&cpg CPG_MOD R9A07G043_CANFD_PCLK>,
				 <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>,
				 <&can_clk>;
			clock-names = "fck", "canfd", "can_clk";
			assigned-clocks = <&cpg CPG_CORE R9A07G043_CLK_P0_DIV2>;
			assigned-clock-rates = <50000000>;
			resets = <&cpg R9A07G043_CANFD_RSTP_N>,
				 <&cpg R9A07G043_CANFD_RSTC_N>;
			reset-names = "rstp_n", "rstc_n";
			power-domains = <&cpg>;
			status = "disabled";

			channel0 {
				status = "disabled";
			};
			channel1 {
				status = "disabled";
			};
		};

		i2c0: i2c@10058000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
			reg = <0 0x10058000 0 0x400>;
			interrupts = <SOC_PERIPHERAL_IRQ(350) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(348) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(349) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(352) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(353) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(351) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(354) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(355) IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "tei", "ri", "ti", "spi", "sti",
					  "naki", "ali", "tmoi";
			clocks = <&cpg CPG_MOD R9A07G043_I2C0_PCLK>;
			clock-frequency = <100000>;
			resets = <&cpg R9A07G043_I2C0_MRST>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		i2c1: i2c@10058400 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
			reg = <0 0x10058400 0 0x400>;
			interrupts = <SOC_PERIPHERAL_IRQ(358) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(356) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(357) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(360) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(361) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(359) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(362) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(363) IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "tei", "ri", "ti", "spi", "sti",
					  "naki", "ali", "tmoi";
			clocks = <&cpg CPG_MOD R9A07G043_I2C1_PCLK>;
			clock-frequency = <100000>;
			resets = <&cpg R9A07G043_I2C1_MRST>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		i2c2: i2c@10058800 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
			reg = <0 0x10058800 0 0x400>;
			interrupts = <SOC_PERIPHERAL_IRQ(366) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(364) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(365) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(368) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(369) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(367) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(370) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(371) IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "tei", "ri", "ti", "spi", "sti",
					  "naki", "ali", "tmoi";
			clocks = <&cpg CPG_MOD R9A07G043_I2C2_PCLK>;
			clock-frequency = <100000>;
			resets = <&cpg R9A07G043_I2C2_MRST>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		i2c3: i2c@10058c00 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "renesas,riic-r9a07g043", "renesas,riic-rz";
			reg = <0 0x10058c00 0 0x400>;
			interrupts = <SOC_PERIPHERAL_IRQ(374) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(372) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(373) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(376) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(377) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(375) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(378) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(379) IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "tei", "ri", "ti", "spi", "sti",
					  "naki", "ali", "tmoi";
			clocks = <&cpg CPG_MOD R9A07G043_I2C3_PCLK>;
			clock-frequency = <100000>;
			resets = <&cpg R9A07G043_I2C3_MRST>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		adc: adc@10059000 {
			compatible = "renesas,r9a07g043-adc", "renesas,rzg2l-adc";
			reg = <0 0x10059000 0 0x400>;
			interrupts = <SOC_PERIPHERAL_IRQ(347) IRQ_TYPE_EDGE_RISING>;
			clocks = <&cpg CPG_MOD R9A07G043_ADC_ADCLK>,
				 <&cpg CPG_MOD R9A07G043_ADC_PCLK>;
			clock-names = "adclk", "pclk";
			resets = <&cpg R9A07G043_ADC_PRESETN>,
				 <&cpg R9A07G043_ADC_ADRST_N>;
			reset-names = "presetn", "adrst-n";
			power-domains = <&cpg>;
			status = "disabled";

			#address-cells = <1>;
			#size-cells = <0>;

			channel@0 {
				reg = <0>;
			};
			channel@1 {
				reg = <1>;
			};
		};

		tsu: thermal@10059400 {
			compatible = "renesas,r9a07g043-tsu",
				     "renesas,rzg2l-tsu";
			reg = <0 0x10059400 0 0x400>;
			clocks = <&cpg CPG_MOD R9A07G043_TSU_PCLK>;
			resets = <&cpg R9A07G043_TSU_PRESETN>;
			power-domains = <&cpg>;
			#thermal-sensor-cells = <1>;
		};

		sbc: spi@10060000 {
			compatible = "renesas,r9a07g043-rpc-if",
				     "renesas,rzg2l-rpc-if";
			reg = <0 0x10060000 0 0x10000>,
			      <0 0x20000000 0 0x10000000>,
			      <0 0x10070000 0 0x10000>;
			reg-names = "regs", "dirmap", "wbuf";
			clocks = <&cpg CPG_MOD R9A07G043_SPI_CLK2>,
				 <&cpg CPG_MOD R9A07G043_SPI_CLK>;
			resets = <&cpg R9A07G043_SPI_RST>;
			power-domains = <&cpg>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		cpg: clock-controller@11010000 {
			compatible = "renesas,r9a07g043-cpg";
			reg = <0 0x11010000 0 0x10000>;
			clocks = <&extal_clk>;
			clock-names = "extal";
			#clock-cells = <2>;
			#reset-cells = <1>;
			#power-domain-cells = <0>;
		};

		sysc: system-controller@11020000 {
			compatible = "renesas,r9a07g043-sysc";
			reg = <0 0x11020000 0 0x10000>;
			status = "disabled";
		};

		pinctrl: pinctrl@11030000 {
			compatible = "renesas,r9a07g043-pinctrl";
			reg = <0 0x11030000 0 0x10000>;
			gpio-controller;
			#gpio-cells = <2>;
			gpio-ranges = <&pinctrl 0 0 152>;
			clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
			power-domains = <&cpg>;
			resets = <&cpg R9A07G043_GPIO_RSTN>,
				 <&cpg R9A07G043_GPIO_PORT_RESETN>,
				 <&cpg R9A07G043_GPIO_SPARE_RESETN>;
		};

		dmac: dma-controller@11820000 {
			compatible = "renesas,r9a07g043-dmac",
				     "renesas,rz-dmac";
			reg = <0 0x11820000 0 0x10000>,
			      <0 0x11830000 0 0x10000>;
			interrupts = <SOC_PERIPHERAL_IRQ(141) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(125) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(126) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(127) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(128) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(129) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(130) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(131) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(132) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(133) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(134) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(135) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(136) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(137) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(138) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(139) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(140) IRQ_TYPE_EDGE_RISING>;
			interrupt-names = "error",
					  "ch0", "ch1", "ch2", "ch3",
					  "ch4", "ch5", "ch6", "ch7",
					  "ch8", "ch9", "ch10", "ch11",
					  "ch12", "ch13", "ch14", "ch15";
			clocks = <&cpg CPG_MOD R9A07G043_DMAC_ACLK>,
				 <&cpg CPG_MOD R9A07G043_DMAC_PCLK>;
			power-domains = <&cpg>;
			resets = <&cpg R9A07G043_DMAC_ARESETN>,
				 <&cpg R9A07G043_DMAC_RST_ASYNC>;
			#dma-cells = <1>;
			dma-channels = <16>;
		};

		sdhi0: mmc@11c00000 {
			compatible = "renesas,sdhi-r9a07g043",
				     "renesas,rcar-gen3-sdhi";
			reg = <0x0 0x11c00000 0 0x10000>;
			interrupts = <SOC_PERIPHERAL_IRQ(104) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(105) IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>,
				 <&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>,
				 <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>,
				 <&cpg CPG_MOD R9A07G043_SDHI0_ACLK>;
			clock-names = "core", "clkh", "cd", "aclk";
			resets = <&cpg R9A07G043_SDHI0_IXRST>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		sdhi1: mmc@11c10000 {
			compatible = "renesas,sdhi-r9a07g043",
				     "renesas,rcar-gen3-sdhi";
			reg = <0x0 0x11c10000 0 0x10000>;
			interrupts = <SOC_PERIPHERAL_IRQ(106) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(107) IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK>,
				 <&cpg CPG_MOD R9A07G043_SDHI1_CLK_HS>,
				 <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>,
				 <&cpg CPG_MOD R9A07G043_SDHI1_ACLK>;
			clock-names = "core", "clkh", "cd", "aclk";
			resets = <&cpg R9A07G043_SDHI1_IXRST>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		eth0: ethernet@11c20000 {
			compatible = "renesas,r9a07g043-gbeth",
				     "renesas,rzg2l-gbeth";
			reg = <0 0x11c20000 0 0x10000>;
			interrupts = <SOC_PERIPHERAL_IRQ(84) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(85) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(86) IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "mux", "fil", "arp_ns";
			phy-mode = "rgmii";
			clocks = <&cpg CPG_MOD R9A07G043_ETH0_CLK_AXI>,
				 <&cpg CPG_MOD R9A07G043_ETH0_CLK_CHI>,
				 <&cpg CPG_CORE R9A07G043_CLK_HP>;
			clock-names = "axi", "chi", "refclk";
			resets = <&cpg R9A07G043_ETH0_RST_HW_N>;
			power-domains = <&cpg>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		eth1: ethernet@11c30000 {
			compatible = "renesas,r9a07g043-gbeth",
				     "renesas,rzg2l-gbeth";
			reg = <0 0x11c30000 0 0x10000>;
			interrupts = <SOC_PERIPHERAL_IRQ(87) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(88) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(89) IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "mux", "fil", "arp_ns";
			phy-mode = "rgmii";
			clocks = <&cpg CPG_MOD R9A07G043_ETH1_CLK_AXI>,
				 <&cpg CPG_MOD R9A07G043_ETH1_CLK_CHI>,
				 <&cpg CPG_CORE R9A07G043_CLK_HP>;
			clock-names = "axi", "chi", "refclk";
			resets = <&cpg R9A07G043_ETH1_RST_HW_N>;
			power-domains = <&cpg>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		phyrst: usbphy-ctrl@11c40000 {
			compatible = "renesas,r9a07g043-usbphy-ctrl",
				     "renesas,rzg2l-usbphy-ctrl";
			reg = <0 0x11c40000 0 0x10000>;
			clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>;
			resets = <&cpg R9A07G043_USB_PRESETN>;
			power-domains = <&cpg>;
			#reset-cells = <1>;
			status = "disabled";
		};

		ohci0: usb@11c50000 {
			compatible = "generic-ohci";
			reg = <0 0x11c50000 0 0x100>;
			interrupts = <SOC_PERIPHERAL_IRQ(91) IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
				 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
			resets = <&phyrst 0>,
				 <&cpg R9A07G043_USB_U2H0_HRESETN>;
			phys = <&usb2_phy0 1>;
			phy-names = "usb";
			power-domains = <&cpg>;
			status = "disabled";
		};

		ohci1: usb@11c70000 {
			compatible = "generic-ohci";
			reg = <0 0x11c70000 0 0x100>;
			interrupts = <SOC_PERIPHERAL_IRQ(96) IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
				 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
			resets = <&phyrst 1>,
				 <&cpg R9A07G043_USB_U2H1_HRESETN>;
			phys = <&usb2_phy1 1>;
			phy-names = "usb";
			power-domains = <&cpg>;
			status = "disabled";
		};

		ehci0: usb@11c50100 {
			compatible = "generic-ehci";
			reg = <0 0x11c50100 0 0x100>;
			interrupts = <SOC_PERIPHERAL_IRQ(92) IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
				 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
			resets = <&phyrst 0>,
				 <&cpg R9A07G043_USB_U2H0_HRESETN>;
			phys = <&usb2_phy0 2>;
			phy-names = "usb";
			companion = <&ohci0>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		ehci1: usb@11c70100 {
			compatible = "generic-ehci";
			reg = <0 0x11c70100 0 0x100>;
			interrupts = <SOC_PERIPHERAL_IRQ(97) IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
				 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
			resets = <&phyrst 1>,
				 <&cpg R9A07G043_USB_U2H1_HRESETN>;
			phys = <&usb2_phy1 2>;
			phy-names = "usb";
			companion = <&ohci1>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		usb2_phy0: usb-phy@11c50200 {
			compatible = "renesas,usb2-phy-r9a07g043",
				     "renesas,rzg2l-usb2-phy";
			reg = <0 0x11c50200 0 0x700>;
			interrupts = <SOC_PERIPHERAL_IRQ(94) IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
				 <&cpg CPG_MOD R9A07G043_USB_U2H0_HCLK>;
			resets = <&phyrst 0>;
			#phy-cells = <1>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		usb2_phy1: usb-phy@11c70200 {
			compatible = "renesas,usb2-phy-r9a07g043",
				     "renesas,rzg2l-usb2-phy";
			reg = <0 0x11c70200 0 0x700>;
			interrupts = <SOC_PERIPHERAL_IRQ(99) IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
				 <&cpg CPG_MOD R9A07G043_USB_U2H1_HCLK>;
			resets = <&phyrst 1>;
			#phy-cells = <1>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		hsusb: usb@11c60000 {
			compatible = "renesas,usbhs-r9a07g043",
				     "renesas,rza2-usbhs";
			reg = <0 0x11c60000 0 0x10000>;
			interrupts = <SOC_PERIPHERAL_IRQ(100) IRQ_TYPE_EDGE_RISING>,
				     <SOC_PERIPHERAL_IRQ(101) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(102) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(103) IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&cpg CPG_MOD R9A07G043_USB_PCLK>,
				 <&cpg CPG_MOD R9A07G043_USB_U2P_EXR_CPUCLK>;
			resets = <&phyrst 0>,
				 <&cpg R9A07G043_USB_U2P_EXL_SYSRST>;
			renesas,buswait = <7>;
			phys = <&usb2_phy0 3>;
			phy-names = "usb";
			power-domains = <&cpg>;
			status = "disabled";
		};

		wdt0: watchdog@12800800 {
			compatible = "renesas,r9a07g043-wdt",
				     "renesas,rzg2l-wdt";
			reg = <0 0x12800800 0 0x400>;
			clocks = <&cpg CPG_MOD R9A07G043_WDT0_PCLK>,
				 <&cpg CPG_MOD R9A07G043_WDT0_CLK>;
			clock-names = "pclk", "oscclk";
			interrupts = <SOC_PERIPHERAL_IRQ(49) IRQ_TYPE_LEVEL_HIGH>,
				     <SOC_PERIPHERAL_IRQ(50) IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "wdt", "perrout";
			resets = <&cpg R9A07G043_WDT0_PRESETN>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		ostm0: timer@12801000 {
			compatible = "renesas,r9a07g043-ostm",
				     "renesas,ostm";
			reg = <0x0 0x12801000 0x0 0x400>;
			interrupts = <SOC_PERIPHERAL_IRQ(46) IRQ_TYPE_EDGE_RISING>;
			clocks = <&cpg CPG_MOD R9A07G043_OSTM0_PCLK>;
			resets = <&cpg R9A07G043_OSTM0_PRESETZ>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		ostm1: timer@12801400 {
			compatible = "renesas,r9a07g043-ostm",
				     "renesas,ostm";
			reg = <0x0 0x12801400 0x0 0x400>;
			interrupts = <SOC_PERIPHERAL_IRQ(47) IRQ_TYPE_EDGE_RISING>;
			clocks = <&cpg CPG_MOD R9A07G043_OSTM1_PCLK>;
			resets = <&cpg R9A07G043_OSTM1_PRESETZ>;
			power-domains = <&cpg>;
			status = "disabled";
		};

		ostm2: timer@12801800 {
			compatible = "renesas,r9a07g043-ostm",
				     "renesas,ostm";
			reg = <0x0 0x12801800 0x0 0x400>;
			interrupts = <SOC_PERIPHERAL_IRQ(48) IRQ_TYPE_EDGE_RISING>;
			clocks = <&cpg CPG_MOD R9A07G043_OSTM2_PCLK>;
			resets = <&cpg R9A07G043_OSTM2_PRESETZ>;
			power-domains = <&cpg>;
			status = "disabled";
		};
	};

	thermal-zones {
		cpu-thermal {
			polling-delay-passive = <250>;
			polling-delay = <1000>;
			thermal-sensors = <&tsu 0>;
			sustainable-power = <717>;

			cooling-maps {
				map0 {
					trip = <&target>;
					cooling-device = <&cpu0 0 2>;
					contribution = <1024>;
				};
			};

			trips {
				sensor_crit: sensor-crit {
					temperature = <125000>;
					hysteresis = <1000>;
					type = "critical";
				};

				target: trip-point {
					temperature = <100000>;
					hysteresis = <1000>;
					type = "passive";
				};
			};
		};
	};
};