)]}'
{
  "id": "43bc0da2631b0302898e0e79376faae46d2fce67",
  "entries": [
    {
      "mode": 33188,
      "type": "blob",
      "id": "2c2aaca894bf4aefdfe67500338aa1253533cb14",
      "name": "fpga-bridge.rst"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "82b6dbbd31cdea13fb3d93d1102615a638f52a16",
      "name": "fpga-mgr.rst"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "f30333ce828e9258a4c58e40e15ca90514c1734e",
      "name": "fpga-region.rst"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "c51e5ebd544abc7a4a45b3bd49887a630687c227",
      "name": "index.rst"
    },
    {
      "mode": 33188,
      "type": "blob",
      "id": "50d1cab84950977d6fa2799eb5e4bb8aa5251ba7",
      "name": "intro.rst"
    }
  ]
}