/*
 * Copyright (C) 2016 ARM Ltd.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include <arm/sunxi-h3-h5.dtsi>

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <0>;
			enable-method = "psci";
		};

		cpu@1 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <1>;
			enable-method = "psci";
		};

		cpu@2 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <2>;
			enable-method = "psci";
		};

		cpu@3 {
			compatible = "arm,cortex-a53";
			device_type = "cpu";
			reg = <3>;
			enable-method = "psci";
		};
	};

	psci {
		compatible = "arm,psci-0.2";
		method = "smc";
	};

	timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 10
				(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	soc {
		syscon: system-control@1c00000 {
			compatible = "allwinner,sun50i-h5-system-control";
			reg = <0x01c00000 0x1000>;
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			sram_c1: sram@18000 {
				compatible = "mmio-sram";
				reg = <0x00018000 0x1c000>;
				#address-cells = <1>;
				#size-cells = <1>;
				ranges = <0 0x00018000 0x1c000>;

				ve_sram: sram-section@0 {
					compatible = "allwinner,sun50i-h5-sram-c1",
						     "allwinner,sun4i-a10-sram-c1";
					reg = <0x000000 0x1c000>;
				};
			};
		};

		video-codec@1c0e000 {
			compatible = "allwinner,sun50i-h5-video-engine";
			reg = <0x01c0e000 0x1000>;
			clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
				 <&ccu CLK_DRAM_VE>;
			clock-names = "ahb", "mod", "ram";
			resets = <&ccu RST_BUS_VE>;
			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
			allwinner,sram = <&ve_sram 1>;
		};

		mali: gpu@1e80000 {
			compatible = "allwinner,sun50i-h5-mali", "arm,mali-450";
			reg = <0x01e80000 0x30000>;
			/*
			 * While the datasheet lists an interrupt for the
			 * PMU, the actual silicon does not have the PMU
			 * block. Reads all return zero, and writes are
			 * ignored.
			 */
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "gp",
					  "gpmmu",
					  "pp",
					  "pp0",
					  "ppmmu0",
					  "pp1",
					  "ppmmu1",
					  "pp2",
					  "ppmmu2",
					  "pp3",
					  "ppmmu3",
					  "pmu";
			clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
			clock-names = "bus", "core";
			resets = <&ccu RST_BUS_GPU>;

			assigned-clocks = <&ccu CLK_GPU>;
			assigned-clock-rates = <384000000>;
		};
	};
};

&ccu {
	compatible = "allwinner,sun50i-h5-ccu";
};

&display_clocks {
	compatible = "allwinner,sun50i-h5-de2-clk";
};

&mmc0 {
	compatible = "allwinner,sun50i-h5-mmc",
		     "allwinner,sun50i-a64-mmc";
	clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
	clock-names = "ahb", "mmc";
};

&mmc1 {
	compatible = "allwinner,sun50i-h5-mmc",
		     "allwinner,sun50i-a64-mmc";
	clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
	clock-names = "ahb", "mmc";
};

&mmc2 {
	compatible = "allwinner,sun50i-h5-emmc",
		     "allwinner,sun50i-a64-emmc";
	clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
	clock-names = "ahb", "mmc";
};

&pio {
	interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
		     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
	compatible = "allwinner,sun50i-h5-pinctrl";
};

&rtc {
	compatible = "allwinner,sun50i-h5-rtc";
};