tree 2f320c3eefa309610aa1f6223f51ec682196f56c
parent 75f486c015b51d00412f0671e3dfbb45b42f27ce
parent 635bd69bbe92acfeddcc6f3d7e7eb1a9049f361b
parent d3174bc836d5aadc871f74ed496694c5ea27b104
parent 4b5a59a265f05a41df6bb3449d8c6db50577dca5
parent b35656de2a13298512a558506fa8d97a9eda5494
parent 64f4466c887e2f16cb01467c8064ff1106c980a3
author Stephen Boyd <sboyd@kernel.org> 1552069770 -0800
committer Stephen Boyd <sboyd@kernel.org> 1552069770 -0800

Merge branches 'clk-ingenic', 'clk-mtk-mux', 'clk-qcom-sdm845-pcie', 'clk-mtk-crit' and 'clk-mtk' into clk-next

* clk-ingenic:
  clk: ingenic: Remove set but not used variable 'enable'
  clk: ingenic: Fix doc of ingenic_cgu_div_info
  clk: ingenic: Fix round_rate misbehaving with non-integer dividers
  clk: ingenic: jz4740: Fix gating of UDC clock

* clk-mtk-mux:
  clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel
  clk: mediatek: add MUX_GATE_FLAGS_2

* clk-qcom-sdm845-pcie:
  clk: qcom: gcc-sdm845: Define parent of PCIe PIPE clocks

* clk-mtk-crit:
  clk: mediatek: Mark bus and DRAM related clocks as critical
  clk: mediatek: Add flags to mtk_gate
  clk: mediatek: Add MUX_FLAGS macro

* clk-mtk:
  clk: mediatek: correct cpu clock name for MT8173 SoC