commit ec20a63aa8b8ec3223fb25cdb2a49f9f9dfda88c
author Fugang Duan <fugang.duan@nxp.com> Mon Oct 15 05:19:00 2018 +0000
committer David S. Miller <davem@davemloft.net> Mon Oct 15 22:52:18 2018 -0700
tree 6eef69aee045c42bdc7c42933dc4f18369d6a4e8
parent fbe1222c63b805e946c3af29b0bfbfee4c2fbeff

net: fec: don't dump RX FIFO register when not available

Commit db65f35f50e0 ("net: fec: add support of ethtool get_regs") introduce
ethool "--register-dump" interface to dump all FEC registers.

But not all silicon implementations of the Freescale FEC hardware module
have the FRBR (FIFO Receive Bound Register) and FRSR (FIFO Receive Start
Register) register, so we should not be trying to dump them on those that
don't.

To fix it we create a quirk flag, FEC_QUIRK_HAS_RFREG, and check it before
dump those RX FIFO registers.

Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>