)]}'
{
  "commit": "e1f34e4f27bb85fac783587ff869af3e46a09bb7",
  "tree": "6dd61ec4da52051c6b55a8e04a793e1d4bb09ac7",
  "parents": [
    "033c9b96b260cb88199d5f802dda04a05d7dd3f8"
  ],
  "author": {
    "name": "Abhishek Sahu",
    "email": "absahu@codeaurora.org",
    "time": "Wed Dec 13 19:55:41 2017 +0530"
  },
  "committer": {
    "name": "Stephen Boyd",
    "email": "sboyd@codeaurora.org",
    "time": "Thu Dec 21 16:03:38 2017 -0800"
  },
  "message": "dt-bindings: clock: qcom: add misc resets for PCIE and NSS\n\nPCIE and NSS has MISC reset register in which single register has\nmultiple reset bit. The patch adds the DT bindings for these MISC\nresets.\n\nSigned-off-by: Abhishek Sahu \u003cabsahu@codeaurora.org\u003e\nReviewed-by: Rob Herring \u003crobh@kernel.org\u003e\nSigned-off-by: Stephen Boyd \u003csboyd@codeaurora.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "ff0b4ac53402abea85ff80a67de311bc2a53356a",
      "old_mode": 33188,
      "old_path": "include/dt-bindings/clock/qcom,gcc-ipq8074.h",
      "new_id": "238f872e52f4ba7eca36d7b582e924a4fc1991ea",
      "new_mode": 33188,
      "new_path": "include/dt-bindings/clock/qcom,gcc-ipq8074.h"
    }
  ]
}