d610b54f77002bbddca54c10d9488c2faa7ff102 - linux

commit	d610b54f77002bbddca54c10d9488c2faa7ff102	[log] [tgz]
author	Jerome Brunet <jbrunet@baylibre.com>	Mon Feb 12 15:58:43 2018 +0100
committer	Neil Armstrong <narmstrong@baylibre.com>	Tue Mar 13 10:04:03 2018 +0100
tree	a991e55607dc05c8f35690122bb66dad30ae55ec
parent	722825dcd54b2e427c1aee54a7992eb4ab04a49d [diff]

clk: meson: split divider and gate part of mpll

The mpll clock is a kind of fractional divider which can gate.
When the RW operation have been added, enable/disable ops have been
mistakenly inserted in this driver. These ops are essentially a
poor copy/paste of the generic gate ops.

This change removes the gate ops from the mpll driver and inserts a
generic gate clock on each mpll divider, simplifying the mpll
driver and reducing code duplication.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

drivers/clk/meson/axg.c[diff]
drivers/clk/meson/axg.h[diff]
drivers/clk/meson/clk-mpll.c[diff]
drivers/clk/meson/clkc.h[diff]
drivers/clk/meson/gxbb.c[diff]
drivers/clk/meson/gxbb.h[diff]
drivers/clk/meson/meson8b.c[diff]
drivers/clk/meson/meson8b.h[diff]

8 files changed

tree: a991e55607dc05c8f35690122bb66dad30ae55ec