[WATCHDOG] i6300esb-set_correct_reload_register_bit
This patch writes into bit 8 of the reload register to perform the
correct 'Reload Sequence' instead of writing into bit 4 of Watchdog for
Intel 6300ESB chipset.
Signed-off-by: Naveen Gupta <ngupta@google.com>
Signed-off-by: David Hardeman <david@2gen.com>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
Signed-off-by: Andrew Morton <akpm@osdl.org>
diff --git a/drivers/char/watchdog/i6300esb.c b/drivers/char/watchdog/i6300esb.c
index f0e96fb..c04b246 100644
--- a/drivers/char/watchdog/i6300esb.c
+++ b/drivers/char/watchdog/i6300esb.c
@@ -109,7 +109,7 @@
spin_lock(&esb_lock);
/* First, reset timers as suggested by the docs */
esb_unlock_registers();
- writew(0x10, ESB_RELOAD_REG);
+ writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);
/* Then disable the WDT */
pci_write_config_byte(esb_pci, ESB_LOCK_REG, 0x0);
pci_read_config_byte(esb_pci, ESB_LOCK_REG, &val);
@@ -123,7 +123,7 @@
{
spin_lock(&esb_lock);
esb_unlock_registers();
- writew(0x10, ESB_RELOAD_REG);
+ writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);
/* FIXME: Do we need to flush anything here? */
spin_unlock(&esb_lock);
}
@@ -153,7 +153,7 @@
/* Reload */
esb_unlock_registers();
- writew(0x10, ESB_RELOAD_REG);
+ writew(ESB_WDT_RELOAD, ESB_RELOAD_REG);
/* FIXME: Do we need to flush everything out? */
