Merge tag 'cleanup-fixes-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/cleanup
From Tony Lindgren:
These fixes are needed to fix non-omap build breakage for
twl-core driver and to fix omap1_defconfig compile when
led driver changes and omap sparse IRQ changes are merged
together. Also fix warnings for omaps not using pinctrl
framework yet.
* tag 'cleanup-fixes-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP1: Include gpio-omap.h for board-h2 and board-h3
ARM: OMAP2+: Enable pinctrl dummy states
mfd: Fix compile for twl-core.c by removing cpu_is_omap usage
diff --git a/Documentation/arm/memory.txt b/Documentation/arm/memory.txt
index 208a2d4..4bfb9ff 100644
--- a/Documentation/arm/memory.txt
+++ b/Documentation/arm/memory.txt
@@ -51,6 +51,9 @@
ff000000 ffbfffff Reserved for future expansion of DMA
mapping region.
+fee00000 feffffff Mapping of PCI I/O space. This is a static
+ mapping within the vmalloc space.
+
VMALLOC_START VMALLOC_END-1 vmalloc() / ioremap() space.
Memory returned by vmalloc/ioremap will
be dynamically placed in this region.
diff --git a/Documentation/devicetree/bindings/arm/pmu.txt b/Documentation/devicetree/bindings/arm/pmu.txt
index 1c044eb..343781b 100644
--- a/Documentation/devicetree/bindings/arm/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/pmu.txt
@@ -7,8 +7,12 @@
Required properties:
- compatible : should be one of
+ "arm,cortex-a15-pmu"
"arm,cortex-a9-pmu"
"arm,cortex-a8-pmu"
+ "arm,cortex-a7-pmu"
+ "arm,cortex-a5-pmu"
+ "arm,arm11mpcore-pmu"
"arm,arm1176-pmu"
"arm,arm1136-pmu"
- interrupts : 1 combined interrupt or 1 per core.
diff --git a/Documentation/devicetree/bindings/regulator/tps6586x.txt b/Documentation/devicetree/bindings/regulator/tps6586x.txt
index da80c2a..a2436e1 100644
--- a/Documentation/devicetree/bindings/regulator/tps6586x.txt
+++ b/Documentation/devicetree/bindings/regulator/tps6586x.txt
@@ -8,7 +8,8 @@
- gpio-controller: mark the device as a GPIO controller
- regulators: list of regulators provided by this controller, must have
property "regulator-compatible" to match their hardware counterparts:
- sm[0-2], ldo[0-9] and ldo_rtc
+ sys, sm[0-2], ldo[0-9] and ldo_rtc
+- sys-supply: The input supply for SYS.
- vin-sm0-supply: The input supply for the SM0.
- vin-sm1-supply: The input supply for the SM1.
- vin-sm2-supply: The input supply for the SM2.
@@ -20,6 +21,9 @@
Each regulator is defined using the standard binding for regulators.
+Note: LDO5 and LDO_RTC is supplied by SYS regulator internally and driver
+ take care of making proper parent child relationship.
+
Example:
pmu: tps6586x@34 {
@@ -30,6 +34,7 @@
#gpio-cells = <2>;
gpio-controller;
+ sys-supply = <&some_reg>;
vin-sm0-supply = <&some_reg>;
vin-sm1-supply = <&some_reg>;
vin-sm2-supply = <&some_reg>;
@@ -43,8 +48,16 @@
#address-cells = <1>;
#size-cells = <0>;
- sm0_reg: regulator@0 {
+ sys_reg: regulator@0 {
reg = <0>;
+ regulator-compatible = "sys";
+ regulator-name = "vdd_sys";
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sm0_reg: regulator@1 {
+ reg = <1>;
regulator-compatible = "sm0";
regulator-min-microvolt = < 725000>;
regulator-max-microvolt = <1500000>;
@@ -52,8 +65,8 @@
regulator-always-on;
};
- sm1_reg: regulator@1 {
- reg = <1>;
+ sm1_reg: regulator@2 {
+ reg = <2>;
regulator-compatible = "sm1";
regulator-min-microvolt = < 725000>;
regulator-max-microvolt = <1500000>;
@@ -61,8 +74,8 @@
regulator-always-on;
};
- sm2_reg: regulator@2 {
- reg = <2>;
+ sm2_reg: regulator@3 {
+ reg = <3>;
regulator-compatible = "sm2";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <4550000>;
@@ -70,72 +83,72 @@
regulator-always-on;
};
- ldo0_reg: regulator@3 {
- reg = <3>;
+ ldo0_reg: regulator@4 {
+ reg = <4>;
regulator-compatible = "ldo0";
regulator-name = "PCIE CLK";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
- ldo1_reg: regulator@4 {
- reg = <4>;
+ ldo1_reg: regulator@5 {
+ reg = <5>;
regulator-compatible = "ldo1";
regulator-min-microvolt = < 725000>;
regulator-max-microvolt = <1500000>;
};
- ldo2_reg: regulator@5 {
- reg = <5>;
+ ldo2_reg: regulator@6 {
+ reg = <6>;
regulator-compatible = "ldo2";
regulator-min-microvolt = < 725000>;
regulator-max-microvolt = <1500000>;
};
- ldo3_reg: regulator@6 {
- reg = <6>;
+ ldo3_reg: regulator@7 {
+ reg = <7>;
regulator-compatible = "ldo3";
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <3300000>;
};
- ldo4_reg: regulator@7 {
- reg = <7>;
+ ldo4_reg: regulator@8 {
+ reg = <8>;
regulator-compatible = "ldo4";
regulator-min-microvolt = <1700000>;
regulator-max-microvolt = <2475000>;
};
- ldo5_reg: regulator@8 {
- reg = <8>;
+ ldo5_reg: regulator@9 {
+ reg = <9>;
regulator-compatible = "ldo5";
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <3300000>;
};
- ldo6_reg: regulator@9 {
- reg = <9>;
+ ldo6_reg: regulator@10 {
+ reg = <10>;
regulator-compatible = "ldo6";
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <3300000>;
};
- ldo7_reg: regulator@10 {
- reg = <10>;
+ ldo7_reg: regulator@11 {
+ reg = <11>;
regulator-compatible = "ldo7";
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <3300000>;
};
- ldo8_reg: regulator@11 {
- reg = <11>;
+ ldo8_reg: regulator@12 {
+ reg = <12>;
regulator-compatible = "ldo8";
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <3300000>;
};
- ldo9_reg: regulator@12 {
- reg = <12>;
+ ldo9_reg: regulator@13 {
+ reg = <13>;
regulator-compatible = "ldo9";
regulator-min-microvolt = <1250000>;
regulator-max-microvolt = <3300000>;
diff --git a/MAINTAINERS b/MAINTAINERS
index fdc0119..437a7dd 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -595,7 +595,6 @@
S: Maintained
F: arch/arm/kernel/perf_event*
F: arch/arm/oprofile/common.c
-F: arch/arm/kernel/pmu.c
F: arch/arm/include/asm/pmu.h
F: arch/arm/kernel/hw_breakpoint.c
F: arch/arm/include/asm/hw_breakpoint.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2f88d8d..6d4d438 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -279,7 +279,6 @@
select GENERIC_CLOCKEVENTS
select PLAT_VERSATILE
select PLAT_VERSATILE_FPGA_IRQ
- select NEED_MACH_IO_H
select NEED_MACH_MEMORY_H
select SPARSE_IRQ
select MULTI_IRQ_HANDLER
@@ -312,7 +311,6 @@
select ICST
select GENERIC_CLOCKEVENTS
select ARCH_WANT_OPTIONAL_GPIOLIB
- select NEED_MACH_IO_H if PCI
select PLAT_VERSATILE
select PLAT_VERSATILE_CLOCK
select PLAT_VERSATILE_CLCD
@@ -407,21 +405,19 @@
help
Support for the Cortina Systems Gemini family SoCs
-config ARCH_PRIMA2
- bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
- select CPU_V7
+config ARCH_SIRF
+ bool "CSR SiRF"
select NO_IOPORT
select ARCH_REQUIRE_GPIOLIB
select GENERIC_CLOCKEVENTS
- select CLKDEV_LOOKUP
+ select COMMON_CLK
select GENERIC_IRQ_CHIP
select MIGHT_HAVE_CACHE_L2X0
select PINCTRL
select PINCTRL_SIRF
select USE_OF
- select ZONE_DMA
help
- Support for CSR SiRFSoC ARM Cortex A9 Platform
+ Support for CSR SiRFprimaII/Marco/Polo platforms
config ARCH_EBSA110
bool "EBSA-110"
@@ -456,7 +452,7 @@
select FOOTBRIDGE
select GENERIC_CLOCKEVENTS
select HAVE_IDE
- select NEED_MACH_IO_H
+ select NEED_MACH_IO_H if !MMU
select NEED_MACH_MEMORY_H
help
Support for systems based on the DC21285 companion chip
@@ -513,7 +509,6 @@
select PCI
select ARCH_SUPPORTS_MSI
select VMSPLIT_1G
- select NEED_MACH_IO_H
select NEED_MACH_MEMORY_H
select NEED_RET_TO_USER
help
@@ -523,7 +518,6 @@
bool "IOP32x-based"
depends on MMU
select CPU_XSCALE
- select NEED_MACH_IO_H
select NEED_RET_TO_USER
select PLAT_IOP
select PCI
@@ -536,7 +530,6 @@
bool "IOP33x-based"
depends on MMU
select CPU_XSCALE
- select NEED_MACH_IO_H
select NEED_RET_TO_USER
select PLAT_IOP
select PCI
@@ -576,7 +569,6 @@
select PCI
select ARCH_REQUIRE_GPIOLIB
select GENERIC_CLOCKEVENTS
- select NEED_MACH_IO_H
select PLAT_ORION
help
Support for the Marvell Dove SoC 88AP510
@@ -587,7 +579,6 @@
select PCI
select ARCH_REQUIRE_GPIOLIB
select GENERIC_CLOCKEVENTS
- select NEED_MACH_IO_H
select PLAT_ORION
help
Support for the following Marvell Kirkwood series SoCs:
@@ -614,7 +605,6 @@
select PCI
select ARCH_REQUIRE_GPIOLIB
select GENERIC_CLOCKEVENTS
- select NEED_MACH_IO_H
select PLAT_ORION
help
Support for the following Marvell MV78xx0 series SoCs:
@@ -627,7 +617,6 @@
select PCI
select ARCH_REQUIRE_GPIOLIB
select GENERIC_CLOCKEVENTS
- select NEED_MACH_IO_H
select PLAT_ORION
help
Support for the following Marvell Orion 5x series SoCs:
@@ -652,8 +641,9 @@
bool "Micrel/Kendin KS8695"
select CPU_ARM922T
select ARCH_REQUIRE_GPIOLIB
- select ARCH_USES_GETTIMEOFFSET
select NEED_MACH_MEMORY_H
+ select CLKSRC_MMIO
+ select GENERIC_CLOCKEVENTS
help
Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
System-on-Chip devices.
@@ -683,7 +673,6 @@
select HAVE_CLK
select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0
- select NEED_MACH_IO_H if PCI
select ARCH_HAS_CPUFREQ
select USE_OF
help
@@ -709,14 +698,6 @@
family of Femtocell devices. The picoxcell support requires device tree
for all boards.
-config ARCH_PNX4008
- bool "Philips Nexperia PNX4008 Mobile"
- select CPU_ARM926T
- select CLKDEV_LOOKUP
- select ARCH_USES_GETTIMEOFFSET
- help
- This enables support for Philips PNX4008 mobile platform.
-
config ARCH_PXA
bool "PXA2xx/PXA3xx-based"
depends on MMU
@@ -912,7 +893,6 @@
select PCI
select ARCH_USES_GETTIMEOFFSET
select NEED_MACH_MEMORY_H
- select NEED_MACH_IO_H
help
Support for the StrongARM based Digital DNARD machine, also known
as "Shark" (<http://www.shark-linux.de/shark.html>).
@@ -931,6 +911,7 @@
select COMMON_CLK
select GENERIC_GPIO
select ARCH_REQUIRE_GPIOLIB
+ select SPARSE_IRQ
help
Support for ST-Ericsson U300 series mobile platforms.
@@ -1118,6 +1099,8 @@
source "arch/arm/mach-shmobile/Kconfig"
+source "arch/arm/mach-prima2/Kconfig"
+
source "arch/arm/mach-tegra/Kconfig"
source "arch/arm/mach-u300/Kconfig"
@@ -1179,12 +1162,6 @@
depends on CPU_XSCALE
default y
-config CPU_HAS_PMU
- depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
- (!ARCH_OMAP3 || OMAP3_EMU)
- default y
- bool
-
config MULTI_IRQ_HANDLER
bool
help
@@ -1757,7 +1734,7 @@
config HW_PERF_EVENTS
bool "Enable hardware performance counter support for perf events"
- depends on PERF_EVENTS && CPU_HAS_PMU
+ depends on PERF_EVENTS
default y
help
Enable hardware performance counter support for perf events. If
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 30eae87..210c923 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -167,7 +167,6 @@
machine-$(CONFIG_ARCH_OMAP2PLUS) := omap2
machine-$(CONFIG_ARCH_ORION5X) := orion5x
machine-$(CONFIG_ARCH_PICOXCELL) := picoxcell
-machine-$(CONFIG_ARCH_PNX4008) := pnx4008
machine-$(CONFIG_ARCH_PRIMA2) := prima2
machine-$(CONFIG_ARCH_PXA) := pxa
machine-$(CONFIG_ARCH_REALVIEW) := realview
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore.dts b/arch/arm/boot/dts/imx27-phytec-phycore.dts
index 2b0ff60..2acc86c 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore.dts
@@ -49,7 +49,7 @@
i2c@1001d000 {
clock-frequency = <400000>;
status = "okay";
- at24@4c {
+ at24@52 {
compatible = "at,24c32";
pagesize = <32>;
reg = <0x52>;
diff --git a/arch/arm/boot/dts/tegra20-harmony.dts b/arch/arm/boot/dts/tegra20-harmony.dts
index f146dbf6..b98a1b3 100644
--- a/arch/arm/boot/dts/tegra20-harmony.dts
+++ b/arch/arm/boot/dts/tegra20-harmony.dts
@@ -275,6 +275,160 @@
i2c@7000d000 {
status = "okay";
clock-frequency = <400000>;
+
+ pmic: tps6586x@34 {
+ compatible = "ti,tps6586x";
+ reg = <0x34>;
+ interrupts = <0 86 0x4>;
+
+ ti,system-power-controller;
+
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ sys-supply = <&vdd_5v0_reg>;
+ vin-sm0-supply = <&sys_reg>;
+ vin-sm1-supply = <&sys_reg>;
+ vin-sm2-supply = <&sys_reg>;
+ vinldo01-supply = <&sm2_reg>;
+ vinldo23-supply = <&sm2_reg>;
+ vinldo4-supply = <&sm2_reg>;
+ vinldo678-supply = <&sm2_reg>;
+ vinldo9-supply = <&sm2_reg>;
+
+ regulators {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sys_reg: regulator@0 {
+ reg = <0>;
+ regulator-compatible = "sys";
+ regulator-name = "vdd_sys";
+ regulator-always-on;
+ };
+
+ regulator@1 {
+ reg = <1>;
+ regulator-compatible = "sm0";
+ regulator-name = "vdd_sm0,vdd_core";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-always-on;
+ };
+
+ regulator@2 {
+ reg = <2>;
+ regulator-compatible = "sm1";
+ regulator-name = "vdd_sm1,vdd_cpu";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-always-on;
+ };
+
+ sm2_reg: regulator@3 {
+ reg = <3>;
+ regulator-compatible = "sm2";
+ regulator-name = "vdd_sm2,vin_ldo*";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ regulator-always-on;
+ };
+
+ regulator@4 {
+ reg = <4>;
+ regulator-compatible = "ldo0";
+ regulator-name = "vdd_ldo0,vddio_pex_clk";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ regulator@5 {
+ reg = <5>;
+ regulator-compatible = "ldo1";
+ regulator-name = "vdd_ldo1,avdd_pll*";
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-always-on;
+ };
+
+ regulator@6 {
+ reg = <6>;
+ regulator-compatible = "ldo2";
+ regulator-name = "vdd_ldo2,vdd_rtc";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ };
+
+ regulator@7 {
+ reg = <7>;
+ regulator-compatible = "ldo3";
+ regulator-name = "vdd_ldo3,avdd_usb*";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ regulator@8 {
+ reg = <8>;
+ regulator-compatible = "ldo4";
+ regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ };
+
+ regulator@9 {
+ reg = <9>;
+ regulator-compatible = "ldo5";
+ regulator-name = "vdd_ldo5,vcore_mmc";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ };
+
+ regulator@10 {
+ reg = <10>;
+ regulator-compatible = "ldo6";
+ regulator-name = "vdd_ldo6,avdd_vdac";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ regulator@11 {
+ reg = <11>;
+ regulator-compatible = "ldo7";
+ regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ regulator@12 {
+ reg = <12>;
+ regulator-compatible = "ldo8";
+ regulator-name = "vdd_ldo8,avdd_hdmi_pll";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ regulator@13 {
+ reg = <13>;
+ regulator-compatible = "ldo9";
+ regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
+ regulator-min-microvolt = <2850000>;
+ regulator-max-microvolt = <2850000>;
+ regulator-always-on;
+ };
+
+ regulator@14 {
+ reg = <14>;
+ regulator-compatible = "ldo_rtc";
+ regulator-name = "vdd_rtc_out,vdd_cell";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
+ };
};
pmc {
@@ -310,6 +464,72 @@
bus-width = <8>;
};
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vdd_5v0_reg: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "vdd_5v0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ };
+
+ regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "vdd_1v5";
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ gpio = <&pmic 0 0>;
+ };
+
+ regulator@2 {
+ compatible = "regulator-fixed";
+ reg = <2>;
+ regulator-name = "vdd_1v2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ gpio = <&pmic 1 0>;
+ enable-active-high;
+ };
+
+ regulator@3 {
+ compatible = "regulator-fixed";
+ reg = <3>;
+ regulator-name = "vdd_1v05";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ gpio = <&pmic 2 0>;
+ enable-active-high;
+ /* Hack until board-harmony-pcie.c is removed */
+ status = "disabled";
+ };
+
+ regulator@4 {
+ compatible = "regulator-fixed";
+ reg = <4>;
+ regulator-name = "vdd_pnl";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&gpio 22 0>; /* gpio PC6 */
+ enable-active-high;
+ };
+
+ regulator@5 {
+ compatible = "regulator-fixed";
+ reg = <5>;
+ regulator-name = "vdd_bl";
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ gpio = <&gpio 176 0>; /* gpio PW0 */
+ enable-active-high;
+ };
+ };
+
sound {
compatible = "nvidia,tegra-audio-wm8903-harmony",
"nvidia,tegra-audio-wm8903";
diff --git a/arch/arm/configs/pnx4008_defconfig b/arch/arm/configs/pnx4008_defconfig
deleted file mode 100644
index 35a31cc..0000000
--- a/arch/arm/configs/pnx4008_defconfig
+++ /dev/null
@@ -1,472 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_AUDIT=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-CONFIG_ARCH_PNX4008=y
-CONFIG_PREEMPT=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="mem=64M console=ttyS0,115200"
-CONFIG_FPE_NWFPE=y
-CONFIG_BINFMT_AOUT=m
-CONFIG_BINFMT_MISC=m
-CONFIG_PM=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_IP_ROUTE_MULTIPATH=y
-CONFIG_IP_ROUTE_VERBOSE=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_MROUTE=y
-CONFIG_IP_PIMSM_V1=y
-CONFIG_IP_PIMSM_V2=y
-CONFIG_SYN_COOKIES=y
-CONFIG_INET_AH=m
-CONFIG_INET_ESP=m
-CONFIG_INET_IPCOMP=m
-CONFIG_IPV6_PRIVACY=y
-CONFIG_INET6_AH=m
-CONFIG_INET6_ESP=m
-CONFIG_INET6_IPCOMP=m
-CONFIG_IPV6_TUNNEL=m
-CONFIG_NETFILTER=y
-CONFIG_IP_VS=m
-CONFIG_IP_VS_PROTO_TCP=y
-CONFIG_IP_VS_PROTO_UDP=y
-CONFIG_IP_VS_PROTO_ESP=y
-CONFIG_IP_VS_PROTO_AH=y
-CONFIG_IP_VS_RR=m
-CONFIG_IP_VS_WRR=m
-CONFIG_IP_VS_LC=m
-CONFIG_IP_VS_WLC=m
-CONFIG_IP_VS_LBLC=m
-CONFIG_IP_VS_LBLCR=m
-CONFIG_IP_VS_DH=m
-CONFIG_IP_VS_SH=m
-CONFIG_IP_VS_SED=m
-CONFIG_IP_VS_NQ=m
-CONFIG_IP_VS_FTP=m
-CONFIG_IP_NF_QUEUE=m
-CONFIG_IP6_NF_QUEUE=m
-CONFIG_DECNET_NF_GRABULATOR=m
-CONFIG_BRIDGE_NF_EBTABLES=m
-CONFIG_BRIDGE_EBT_BROUTE=m
-CONFIG_BRIDGE_EBT_T_FILTER=m
-CONFIG_BRIDGE_EBT_T_NAT=m
-CONFIG_BRIDGE_EBT_802_3=m
-CONFIG_BRIDGE_EBT_AMONG=m
-CONFIG_BRIDGE_EBT_ARP=m
-CONFIG_BRIDGE_EBT_IP=m
-CONFIG_BRIDGE_EBT_LIMIT=m
-CONFIG_BRIDGE_EBT_MARK=m
-CONFIG_BRIDGE_EBT_PKTTYPE=m
-CONFIG_BRIDGE_EBT_STP=m
-CONFIG_BRIDGE_EBT_VLAN=m
-CONFIG_BRIDGE_EBT_ARPREPLY=m
-CONFIG_BRIDGE_EBT_DNAT=m
-CONFIG_BRIDGE_EBT_MARK_T=m
-CONFIG_BRIDGE_EBT_REDIRECT=m
-CONFIG_BRIDGE_EBT_SNAT=m
-CONFIG_BRIDGE_EBT_LOG=m
-CONFIG_IP_SCTP=m
-CONFIG_ATM=y
-CONFIG_ATM_CLIP=y
-CONFIG_ATM_LANE=m
-CONFIG_ATM_MPOA=m
-CONFIG_ATM_BR2684=m
-CONFIG_BRIDGE=m
-CONFIG_VLAN_8021Q=m
-CONFIG_DECNET=m
-CONFIG_LLC2=m
-CONFIG_IPX=m
-CONFIG_ATALK=m
-CONFIG_DEV_APPLETALK=m
-CONFIG_IPDDP=m
-CONFIG_IPDDP_ENCAP=y
-CONFIG_IPDDP_DECAP=y
-CONFIG_X25=m
-CONFIG_LAPB=m
-CONFIG_ECONET=m
-CONFIG_ECONET_AUNUDP=y
-CONFIG_ECONET_NATIVE=y
-CONFIG_WAN_ROUTER=m
-CONFIG_NET_SCHED=y
-CONFIG_NET_SCH_CBQ=m
-CONFIG_NET_SCH_HTB=m
-CONFIG_NET_SCH_HFSC=m
-CONFIG_NET_SCH_ATM=m
-CONFIG_NET_SCH_PRIO=m
-CONFIG_NET_SCH_RED=m
-CONFIG_NET_SCH_SFQ=m
-CONFIG_NET_SCH_TEQL=m
-CONFIG_NET_SCH_TBF=m
-CONFIG_NET_SCH_GRED=m
-CONFIG_NET_SCH_DSMARK=m
-CONFIG_NET_SCH_NETEM=m
-CONFIG_NET_CLS_TCINDEX=m
-CONFIG_NET_CLS_ROUTE4=m
-CONFIG_NET_CLS_FW=m
-CONFIG_NET_CLS_U32=m
-CONFIG_NET_CLS_RSVP=m
-CONFIG_NET_CLS_RSVP6=m
-CONFIG_NET_PKTGEN=m
-CONFIG_MTD=y
-CONFIG_MTD_CONCAT=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_REDBOOT_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_SLRAM=m
-CONFIG_MTD_PHRAM=m
-CONFIG_MTD_MTDRAM=m
-CONFIG_MTD_DOC2000=m
-CONFIG_MTD_DOC2001=m
-CONFIG_MTD_DOC2001PLUS=m
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_NANDSIM=m
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_CRYPTOLOOP=y
-CONFIG_BLK_DEV_NBD=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-CONFIG_CDROM_PKTCDVD=m
-CONFIG_EEPROM_LEGACY=m
-CONFIG_SCSI=m
-CONFIG_BLK_DEV_SD=m
-CONFIG_CHR_DEV_ST=m
-CONFIG_CHR_DEV_OSST=m
-CONFIG_BLK_DEV_SR=m
-CONFIG_CHR_DEV_SG=m
-CONFIG_CHR_DEV_SCH=m
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-CONFIG_SCSI_SPI_ATTRS=m
-CONFIG_SCSI_FC_ATTRS=m
-CONFIG_SCSI_DEBUG=m
-CONFIG_NETDEVICES=y
-CONFIG_DUMMY=m
-CONFIG_BONDING=m
-CONFIG_EQUALIZER=m
-CONFIG_TUN=m
-CONFIG_NET_ETHERNET=y
-CONFIG_USB_CATC=m
-CONFIG_USB_KAWETH=m
-CONFIG_USB_PEGASUS=m
-CONFIG_USB_RTL8150=m
-CONFIG_USB_USBNET=m
-# CONFIG_USB_NET_CDC_SUBSET is not set
-CONFIG_WAN=y
-CONFIG_HDLC=m
-CONFIG_HDLC_RAW=m
-CONFIG_HDLC_RAW_ETH=m
-CONFIG_HDLC_CISCO=m
-CONFIG_HDLC_FR=m
-CONFIG_HDLC_PPP=m
-CONFIG_HDLC_X25=m
-CONFIG_DLCI=m
-CONFIG_WAN_ROUTER_DRIVERS=m
-CONFIG_LAPBETHER=m
-CONFIG_X25_ASY=m
-CONFIG_ATM_TCP=m
-CONFIG_PPP=m
-CONFIG_PPP_MULTILINK=y
-CONFIG_PPP_FILTER=y
-CONFIG_PPP_ASYNC=m
-CONFIG_PPP_SYNC_TTY=m
-CONFIG_PPP_DEFLATE=m
-CONFIG_PPP_BSDCOMP=m
-CONFIG_PPP_MPPE=m
-CONFIG_PPPOE=m
-CONFIG_PPPOATM=m
-CONFIG_SLIP=m
-CONFIG_SLIP_COMPRESSED=y
-CONFIG_SLIP_SMART=y
-CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_NETCONSOLE=m
-# CONFIG_INPUT_MOUSEDEV is not set
-CONFIG_INPUT_JOYDEV=m
-CONFIG_INPUT_EVDEV=m
-CONFIG_INPUT_EVBUG=m
-CONFIG_KEYBOARD_LKKBD=m
-CONFIG_KEYBOARD_NEWTON=m
-CONFIG_KEYBOARD_SUNKBD=m
-CONFIG_KEYBOARD_XTKBD=m
-CONFIG_MOUSE_PS2=m
-CONFIG_MOUSE_SERIAL=m
-CONFIG_MOUSE_VSXXXAA=m
-CONFIG_INPUT_JOYSTICK=y
-CONFIG_JOYSTICK_ANALOG=m
-CONFIG_JOYSTICK_A3D=m
-CONFIG_JOYSTICK_ADI=m
-CONFIG_JOYSTICK_COBRA=m
-CONFIG_JOYSTICK_GF2K=m
-CONFIG_JOYSTICK_GRIP=m
-CONFIG_JOYSTICK_GRIP_MP=m
-CONFIG_JOYSTICK_GUILLEMOT=m
-CONFIG_JOYSTICK_INTERACT=m
-CONFIG_JOYSTICK_SIDEWINDER=m
-CONFIG_JOYSTICK_TMDC=m
-CONFIG_JOYSTICK_IFORCE=m
-CONFIG_JOYSTICK_IFORCE_USB=y
-CONFIG_JOYSTICK_IFORCE_232=y
-CONFIG_JOYSTICK_WARRIOR=m
-CONFIG_JOYSTICK_MAGELLAN=m
-CONFIG_JOYSTICK_SPACEORB=m
-CONFIG_JOYSTICK_SPACEBALL=m
-CONFIG_JOYSTICK_STINGER=m
-CONFIG_JOYSTICK_JOYDUMP=m
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_GUNZE=m
-CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=m
-CONFIG_SERIO_SERPORT=m
-CONFIG_SERIO_RAW=m
-CONFIG_GAMEPORT_NS558=m
-CONFIG_GAMEPORT_L4=m
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_EXTENDED=y
-CONFIG_SERIAL_8250_MANY_PORTS=y
-CONFIG_SERIAL_8250_SHARE_IRQ=y
-CONFIG_SERIAL_8250_RSA=y
-CONFIG_HW_RANDOM=y
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_SPI=y
-CONFIG_SPI_BITBANG=y
-# CONFIG_HWMON is not set
-CONFIG_WATCHDOG=y
-CONFIG_SOFT_WATCHDOG=m
-CONFIG_USBPCWATCHDOG=m
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_SEQUENCER=m
-CONFIG_SND_SEQ_DUMMY=m
-CONFIG_SND_MIXER_OSS=m
-CONFIG_SND_PCM_OSS=m
-CONFIG_SND_SEQUENCER_OSS=y
-CONFIG_SND_DUMMY=m
-CONFIG_SND_VIRMIDI=m
-CONFIG_SND_MTPAV=m
-CONFIG_SND_SERIAL_U16550=m
-CONFIG_SND_MPU401=m
-CONFIG_SND_USB_AUDIO=m
-CONFIG_SOUND_PRIME=m
-CONFIG_USB_HID=m
-CONFIG_USB_HIDDEV=y
-CONFIG_USB_KBD=m
-CONFIG_USB_MOUSE=m
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_MON=y
-CONFIG_USB_SL811_HCD=m
-CONFIG_USB_ACM=m
-CONFIG_USB_PRINTER=m
-CONFIG_USB_STORAGE=m
-CONFIG_USB_STORAGE_DATAFAB=m
-CONFIG_USB_STORAGE_FREECOM=m
-CONFIG_USB_STORAGE_USBAT=m
-CONFIG_USB_STORAGE_SDDR09=m
-CONFIG_USB_STORAGE_SDDR55=m
-CONFIG_USB_STORAGE_JUMPSHOT=m
-CONFIG_USB_MDC800=m
-CONFIG_USB_MICROTEK=m
-CONFIG_USB_SERIAL=m
-CONFIG_USB_SERIAL_GENERIC=y
-CONFIG_USB_SERIAL_BELKIN=m
-CONFIG_USB_SERIAL_WHITEHEAT=m
-CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
-CONFIG_USB_SERIAL_CYPRESS_M8=m
-CONFIG_USB_SERIAL_EMPEG=m
-CONFIG_USB_SERIAL_FTDI_SIO=m
-CONFIG_USB_SERIAL_VISOR=m
-CONFIG_USB_SERIAL_IPAQ=m
-CONFIG_USB_SERIAL_IR=m
-CONFIG_USB_SERIAL_EDGEPORT=m
-CONFIG_USB_SERIAL_EDGEPORT_TI=m
-CONFIG_USB_SERIAL_IPW=m
-CONFIG_USB_SERIAL_KEYSPAN_PDA=m
-CONFIG_USB_SERIAL_KEYSPAN=m
-CONFIG_USB_SERIAL_KLSI=m
-CONFIG_USB_SERIAL_KOBIL_SCT=m
-CONFIG_USB_SERIAL_MCT_U232=m
-CONFIG_USB_SERIAL_PL2303=m
-CONFIG_USB_SERIAL_SAFE=m
-CONFIG_USB_SERIAL_CYBERJACK=m
-CONFIG_USB_SERIAL_XIRCOM=m
-CONFIG_USB_SERIAL_OMNINET=m
-CONFIG_USB_RIO500=m
-CONFIG_USB_LEGOTOWER=m
-CONFIG_USB_LCD=m
-CONFIG_USB_LED=m
-CONFIG_USB_CYTHERM=m
-CONFIG_USB_TEST=m
-CONFIG_USB_ATM=m
-CONFIG_USB_SPEEDTOUCH=m
-CONFIG_USB_GADGET=m
-CONFIG_USB_GADGET_DUMMY_HCD=y
-CONFIG_USB_ZERO=m
-CONFIG_USB_ETH=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_FILE_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_MMC=m
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_POSIX_ACL=y
-CONFIG_EXT2_FS_SECURITY=y
-CONFIG_EXT3_FS=m
-CONFIG_EXT3_FS_POSIX_ACL=y
-CONFIG_EXT3_FS_SECURITY=y
-CONFIG_REISERFS_FS=m
-CONFIG_REISERFS_FS_XATTR=y
-CONFIG_REISERFS_FS_POSIX_ACL=y
-CONFIG_REISERFS_FS_SECURITY=y
-CONFIG_JFS_FS=m
-CONFIG_JFS_POSIX_ACL=y
-CONFIG_JFS_STATISTICS=y
-CONFIG_XFS_FS=m
-CONFIG_XFS_QUOTA=y
-CONFIG_XFS_POSIX_ACL=y
-CONFIG_XFS_RT=y
-CONFIG_INOTIFY=y
-CONFIG_QUOTA=y
-CONFIG_QFMT_V1=m
-CONFIG_QFMT_V2=m
-CONFIG_AUTOFS_FS=m
-CONFIG_AUTOFS4_FS=m
-CONFIG_ISO9660_FS=m
-CONFIG_JOLIET=y
-CONFIG_ZISOFS=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_NTFS_FS=m
-CONFIG_TMPFS=y
-CONFIG_ADFS_FS=m
-CONFIG_AFFS_FS=m
-CONFIG_HFS_FS=m
-CONFIG_HFSPLUS_FS=m
-CONFIG_BEFS_FS=m
-CONFIG_BFS_FS=m
-CONFIG_EFS_FS=m
-CONFIG_JFFS2_FS=m
-CONFIG_CRAMFS=y
-CONFIG_VXFS_FS=m
-CONFIG_MINIX_FS=m
-CONFIG_HPFS_FS=m
-CONFIG_QNX4FS_FS=m
-CONFIG_ROMFS_FS=m
-CONFIG_SYSV_FS=m
-CONFIG_UFS_FS=m
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_NFS_V4=y
-CONFIG_ROOT_NFS=y
-CONFIG_NFSD=m
-CONFIG_NFSD_V4=y
-CONFIG_RPCSEC_GSS_SPKM3=m
-CONFIG_SMB_FS=m
-CONFIG_CIFS=m
-CONFIG_NCP_FS=m
-CONFIG_NCPFS_PACKET_SIGNING=y
-CONFIG_NCPFS_IOCTL_LOCKING=y
-CONFIG_NCPFS_STRONG=y
-CONFIG_NCPFS_NFS_NS=y
-CONFIG_NCPFS_OS2_NS=y
-CONFIG_NCPFS_NLS=y
-CONFIG_NCPFS_EXTRAS=y
-CONFIG_CODA_FS=m
-CONFIG_AFS_FS=m
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_ACORN_PARTITION=y
-CONFIG_ACORN_PARTITION_ICS=y
-CONFIG_ACORN_PARTITION_RISCIX=y
-CONFIG_OSF_PARTITION=y
-CONFIG_AMIGA_PARTITION=y
-CONFIG_ATARI_PARTITION=y
-CONFIG_MAC_PARTITION=y
-CONFIG_BSD_DISKLABEL=y
-CONFIG_MINIX_SUBPARTITION=y
-CONFIG_SOLARIS_X86_PARTITION=y
-CONFIG_UNIXWARE_DISKLABEL=y
-CONFIG_LDM_PARTITION=y
-CONFIG_SGI_PARTITION=y
-CONFIG_ULTRIX_PARTITION=y
-CONFIG_SUN_PARTITION=y
-CONFIG_NLS_DEFAULT="cp437"
-CONFIG_NLS_CODEPAGE_437=m
-CONFIG_NLS_CODEPAGE_737=m
-CONFIG_NLS_CODEPAGE_775=m
-CONFIG_NLS_CODEPAGE_850=m
-CONFIG_NLS_CODEPAGE_852=m
-CONFIG_NLS_CODEPAGE_855=m
-CONFIG_NLS_CODEPAGE_857=m
-CONFIG_NLS_CODEPAGE_860=m
-CONFIG_NLS_CODEPAGE_861=m
-CONFIG_NLS_CODEPAGE_862=m
-CONFIG_NLS_CODEPAGE_863=m
-CONFIG_NLS_CODEPAGE_864=m
-CONFIG_NLS_CODEPAGE_865=m
-CONFIG_NLS_CODEPAGE_866=m
-CONFIG_NLS_CODEPAGE_869=m
-CONFIG_NLS_CODEPAGE_936=m
-CONFIG_NLS_CODEPAGE_950=m
-CONFIG_NLS_CODEPAGE_932=m
-CONFIG_NLS_CODEPAGE_949=m
-CONFIG_NLS_CODEPAGE_874=m
-CONFIG_NLS_ISO8859_8=m
-CONFIG_NLS_CODEPAGE_1250=m
-CONFIG_NLS_CODEPAGE_1251=m
-CONFIG_NLS_ASCII=m
-CONFIG_NLS_ISO8859_1=m
-CONFIG_NLS_ISO8859_2=m
-CONFIG_NLS_ISO8859_3=m
-CONFIG_NLS_ISO8859_4=m
-CONFIG_NLS_ISO8859_5=m
-CONFIG_NLS_ISO8859_6=m
-CONFIG_NLS_ISO8859_7=m
-CONFIG_NLS_ISO8859_9=m
-CONFIG_NLS_ISO8859_13=m
-CONFIG_NLS_ISO8859_14=m
-CONFIG_NLS_ISO8859_15=m
-CONFIG_NLS_KOI8_R=m
-CONFIG_NLS_KOI8_U=m
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_MUTEXES=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_SECURITY=y
-CONFIG_CRYPTO_NULL=m
-CONFIG_CRYPTO_TEST=m
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_MD4=m
-CONFIG_CRYPTO_MICHAEL_MIC=m
-CONFIG_CRYPTO_SHA256=m
-CONFIG_CRYPTO_SHA512=m
-CONFIG_CRYPTO_WP512=m
-CONFIG_CRYPTO_ANUBIS=m
-CONFIG_CRYPTO_BLOWFISH=m
-CONFIG_CRYPTO_CAST6=m
-CONFIG_CRYPTO_KHAZAD=m
-CONFIG_CRYPTO_SERPENT=m
-CONFIG_CRYPTO_TEA=m
-CONFIG_CRYPTO_TWOFISH=m
-CONFIG_CRC16=m
diff --git a/arch/arm/configs/prima2_defconfig b/arch/arm/configs/prima2_defconfig
index c328ac6..807d4e2 100644
--- a/arch/arm/configs/prima2_defconfig
+++ b/arch/arm/configs/prima2_defconfig
@@ -1,4 +1,6 @@
CONFIG_EXPERIMENTAL=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
CONFIG_RELAY=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_KALLSYMS_ALL=y
@@ -8,9 +10,7 @@
CONFIG_PARTITION_ADVANCED=y
CONFIG_BSD_DISKLABEL=y
CONFIG_SOLARIS_X86_PARTITION=y
-CONFIG_ARCH_PRIMA2=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
+CONFIG_ARCH_SIRF=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_KEXEC=y
@@ -36,7 +36,6 @@
CONFIG_SPI_SIRF=y
CONFIG_SPI_SPIDEV=y
# CONFIG_HWMON is not set
-# CONFIG_HID_SUPPORT is not set
CONFIG_USB_GADGET=y
CONFIG_USB_FILE_STORAGE=m
CONFIG_USB_MASS_STORAGE=m
diff --git a/arch/arm/include/asm/hardware/iop3xx.h b/arch/arm/include/asm/hardware/iop3xx.h
index 2ff2c75..02fe2fb 100644
--- a/arch/arm/include/asm/hardware/iop3xx.h
+++ b/arch/arm/include/asm/hardware/iop3xx.h
@@ -217,18 +217,8 @@
#define IOP3XX_PCI_LOWER_MEM_PA 0x80000000
#define IOP3XX_PCI_MEM_WINDOW_SIZE 0x08000000
-#define IOP3XX_PCI_IO_WINDOW_SIZE 0x00010000
#define IOP3XX_PCI_LOWER_IO_PA 0x90000000
-#define IOP3XX_PCI_LOWER_IO_VA 0xfe000000
-#define IOP3XX_PCI_LOWER_IO_BA 0x90000000
-#define IOP3XX_PCI_UPPER_IO_PA (IOP3XX_PCI_LOWER_IO_PA +\
- IOP3XX_PCI_IO_WINDOW_SIZE - 1)
-#define IOP3XX_PCI_UPPER_IO_VA (IOP3XX_PCI_LOWER_IO_VA +\
- IOP3XX_PCI_IO_WINDOW_SIZE - 1)
-#define IOP3XX_PCI_IO_PHYS_TO_VIRT(addr) (((u32) (addr) -\
- IOP3XX_PCI_LOWER_IO_PA) +\
- IOP3XX_PCI_LOWER_IO_VA)
-
+#define IOP3XX_PCI_LOWER_IO_BA 0x00000000
#ifndef __ASSEMBLY__
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 815c669..8f4db67 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -113,11 +113,19 @@
#define __iowmb() do { } while (0)
#endif
+/* PCI fixed i/o mapping */
+#define PCI_IO_VIRT_BASE 0xfee00000
+
+extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr);
+
/*
* Now, pick up the machine-defined IO definitions
*/
#ifdef CONFIG_NEED_MACH_IO_H
#include <mach/io.h>
+#elif defined(CONFIG_PCI)
+#define IO_SPACE_LIMIT ((resource_size_t)0xfffff)
+#define __io(a) __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT))
#else
#define __io(a) __typesafe_io((a) & IO_SPACE_LIMIT)
#endif
diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h
index a6efcdd..195ac2f 100644
--- a/arch/arm/include/asm/mach/map.h
+++ b/arch/arm/include/asm/mach/map.h
@@ -9,6 +9,9 @@
*
* Page table mapping constructs and function prototypes
*/
+#ifndef __ASM_MACH_MAP_H
+#define __ASM_MACH_MAP_H
+
#include <asm/io.h>
struct map_desc {
@@ -34,6 +37,8 @@
#ifdef CONFIG_MMU
extern void iotable_init(struct map_desc *, int);
+extern void vm_reserve_area_early(unsigned long addr, unsigned long size,
+ void *caller);
struct mem_type;
extern const struct mem_type *get_mem_type(unsigned int type);
@@ -44,4 +49,7 @@
const struct mem_type *mtype);
#else
#define iotable_init(map,num) do { } while (0)
+#define vm_reserve_area_early(a,s,c) do { } while (0)
+#endif
+
#endif
diff --git a/arch/arm/include/asm/mach/pci.h b/arch/arm/include/asm/mach/pci.h
index 26c511fd..db9fedb 100644
--- a/arch/arm/include/asm/mach/pci.h
+++ b/arch/arm/include/asm/mach/pci.h
@@ -11,6 +11,8 @@
#ifndef __ASM_MACH_PCI_H
#define __ASM_MACH_PCI_H
+#include <linux/ioport.h>
+
struct pci_sys_data;
struct pci_ops;
struct pci_bus;
@@ -42,6 +44,8 @@
unsigned long io_offset; /* bus->cpu IO mapping offset */
struct pci_bus *bus; /* PCI bus */
struct list_head resources; /* root bus resources (apertures) */
+ struct resource io_res;
+ char io_res_name[12];
/* Bridge swizzling */
u8 (*swizzle)(struct pci_dev *, u8 *);
/* IRQ mapping */
@@ -55,6 +59,15 @@
void pci_common_init(struct hw_pci *);
/*
+ * Setup early fixed I/O mapping.
+ */
+#if defined(CONFIG_PCI)
+extern void pci_map_io_early(unsigned long pfn);
+#else
+static inline void pci_map_io_early(unsigned long pfn) {}
+#endif
+
+/*
* PCI controllers
*/
extern struct pci_ops iop3xx_ops;
diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h
index e074948..625cd62 100644
--- a/arch/arm/include/asm/perf_event.h
+++ b/arch/arm/include/asm/perf_event.h
@@ -12,6 +12,13 @@
#ifndef __ARM_PERF_EVENT_H__
#define __ARM_PERF_EVENT_H__
-/* Nothing to see here... */
+/*
+ * The ARMv7 CPU PMU supports up to 32 event counters.
+ */
+#define ARMPMU_MAX_HWEVENTS 32
+
+#define HW_OP_UNSUPPORTED 0xFFFF
+#define C(_x) PERF_COUNT_HW_CACHE_##_x
+#define CACHE_OP_UNSUPPORTED 0xFFFF
#endif /* __ARM_PERF_EVENT_H__ */
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index 4432305..a26170d 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -16,69 +16,30 @@
#include <linux/perf_event.h>
/*
- * Types of PMUs that can be accessed directly and require mutual
- * exclusion between profiling tools.
- */
-enum arm_pmu_type {
- ARM_PMU_DEVICE_CPU = 0,
- ARM_NUM_PMU_DEVICES,
-};
-
-/*
* struct arm_pmu_platdata - ARM PMU platform data
*
* @handle_irq: an optional handler which will be called from the
* interrupt and passed the address of the low level handler,
* and can be used to implement any platform specific handling
* before or after calling it.
- * @enable_irq: an optional handler which will be called after
- * request_irq and be used to handle some platform specific
- * irq enablement
- * @disable_irq: an optional handler which will be called before
- * free_irq and be used to handle some platform specific
- * irq disablement
+ * @runtime_resume: an optional handler which will be called by the
+ * runtime PM framework following a call to pm_runtime_get().
+ * Note that if pm_runtime_get() is called more than once in
+ * succession this handler will only be called once.
+ * @runtime_suspend: an optional handler which will be called by the
+ * runtime PM framework following a call to pm_runtime_put().
+ * Note that if pm_runtime_get() is called more than once in
+ * succession this handler will only be called following the
+ * final call to pm_runtime_put() that actually disables the
+ * hardware.
*/
struct arm_pmu_platdata {
irqreturn_t (*handle_irq)(int irq, void *dev,
irq_handler_t pmu_handler);
- void (*enable_irq)(int irq);
- void (*disable_irq)(int irq);
+ int (*runtime_resume)(struct device *dev);
+ int (*runtime_suspend)(struct device *dev);
};
-#ifdef CONFIG_CPU_HAS_PMU
-
-/**
- * reserve_pmu() - reserve the hardware performance counters
- *
- * Reserve the hardware performance counters in the system for exclusive use.
- * Returns 0 on success or -EBUSY if the lock is already held.
- */
-extern int
-reserve_pmu(enum arm_pmu_type type);
-
-/**
- * release_pmu() - Relinquish control of the performance counters
- *
- * Release the performance counters and allow someone else to use them.
- */
-extern void
-release_pmu(enum arm_pmu_type type);
-
-#else /* CONFIG_CPU_HAS_PMU */
-
-#include <linux/err.h>
-
-static inline int
-reserve_pmu(enum arm_pmu_type type)
-{
- return -ENODEV;
-}
-
-static inline void
-release_pmu(enum arm_pmu_type type) { }
-
-#endif /* CONFIG_CPU_HAS_PMU */
-
#ifdef CONFIG_HW_PERF_EVENTS
/* The events for a given PMU register set. */
@@ -103,7 +64,6 @@
struct arm_pmu {
struct pmu pmu;
- enum arm_pmu_type type;
cpumask_t active_irqs;
char *name;
irqreturn_t (*handle_irq)(int irq_num, void *dev);
@@ -118,6 +78,8 @@
void (*start)(void);
void (*stop)(void);
void (*reset)(void *);
+ int (*request_irq)(irq_handler_t handler);
+ void (*free_irq)(void);
int (*map_event)(struct perf_event *event);
int num_events;
atomic_t active_events;
@@ -129,7 +91,9 @@
#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
-int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type);
+extern const struct dev_pm_ops armpmu_dev_pm_ops;
+
+int armpmu_register(struct arm_pmu *armpmu, char *name, int type);
u64 armpmu_event_update(struct perf_event *event,
struct hw_perf_event *hwc,
@@ -139,6 +103,13 @@
struct hw_perf_event *hwc,
int idx);
+int armpmu_map_event(struct perf_event *event,
+ const unsigned (*event_map)[PERF_COUNT_HW_MAX],
+ const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
+ [PERF_COUNT_HW_CACHE_OP_MAX]
+ [PERF_COUNT_HW_CACHE_RESULT_MAX],
+ u32 raw_event_mask);
+
#endif /* CONFIG_HW_PERF_EVENTS */
#endif /* __ARM_PMU_H__ */
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 7ad2d5c..1c43214 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -69,8 +69,7 @@
obj-$(CONFIG_CPU_MOHAWK) += xscale-cp0.o
obj-$(CONFIG_CPU_PJ4) += pj4-cp0.o
obj-$(CONFIG_IWMMXT) += iwmmxt.o
-obj-$(CONFIG_CPU_HAS_PMU) += pmu.o
-obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o
+obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o perf_event_cpu.o
AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt
obj-$(CONFIG_ARM_CPU_TOPOLOGY) += topology.o
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index 2b2f25e..b244696 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -13,6 +13,7 @@
#include <linux/io.h>
#include <asm/mach-types.h>
+#include <asm/mach/map.h>
#include <asm/mach/pci.h>
static int debug_pci;
@@ -423,6 +424,38 @@
return irq;
}
+static int __init pcibios_init_resources(int busnr, struct pci_sys_data *sys)
+{
+ int ret;
+ struct pci_host_bridge_window *window;
+
+ if (list_empty(&sys->resources)) {
+ pci_add_resource_offset(&sys->resources,
+ &iomem_resource, sys->mem_offset);
+ }
+
+ list_for_each_entry(window, &sys->resources, list) {
+ if (resource_type(window->res) == IORESOURCE_IO)
+ return 0;
+ }
+
+ sys->io_res.start = (busnr * SZ_64K) ? : pcibios_min_io;
+ sys->io_res.end = (busnr + 1) * SZ_64K - 1;
+ sys->io_res.flags = IORESOURCE_IO;
+ sys->io_res.name = sys->io_res_name;
+ sprintf(sys->io_res_name, "PCI%d I/O", busnr);
+
+ ret = request_resource(&ioport_resource, &sys->io_res);
+ if (ret) {
+ pr_err("PCI: unable to allocate I/O port region (%d)\n", ret);
+ return ret;
+ }
+ pci_add_resource_offset(&sys->resources, &sys->io_res,
+ sys->io_offset);
+
+ return 0;
+}
+
static void __init pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
{
struct pci_sys_data *sys = NULL;
@@ -445,11 +478,10 @@
ret = hw->setup(nr, sys);
if (ret > 0) {
- if (list_empty(&sys->resources)) {
- pci_add_resource_offset(&sys->resources,
- &ioport_resource, sys->io_offset);
- pci_add_resource_offset(&sys->resources,
- &iomem_resource, sys->mem_offset);
+ ret = pcibios_init_resources(nr, sys);
+ if (ret) {
+ kfree(sys);
+ break;
}
if (hw->scan)
@@ -627,3 +659,15 @@
return 0;
}
+
+void __init pci_map_io_early(unsigned long pfn)
+{
+ struct map_desc pci_io_desc = {
+ .virtual = PCI_IO_VIRT_BASE,
+ .type = MT_DEVICE,
+ .length = SZ_64K,
+ };
+
+ pci_io_desc.pfn = pfn;
+ iotable_init(&pci_io_desc, 1);
+}
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index ab243b8..93971b1 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -12,68 +12,15 @@
*/
#define pr_fmt(fmt) "hw perfevents: " fmt
-#include <linux/bitmap.h>
-#include <linux/interrupt.h>
#include <linux/kernel.h>
-#include <linux/export.h>
-#include <linux/perf_event.h>
#include <linux/platform_device.h>
-#include <linux/spinlock.h>
+#include <linux/pm_runtime.h>
#include <linux/uaccess.h>
-#include <asm/cputype.h>
-#include <asm/irq.h>
#include <asm/irq_regs.h>
#include <asm/pmu.h>
#include <asm/stacktrace.h>
-/*
- * ARMv6 supports a maximum of 3 events, starting from index 0. If we add
- * another platform that supports more, we need to increase this to be the
- * largest of all platforms.
- *
- * ARMv7 supports up to 32 events:
- * cycle counter CCNT + 31 events counters CNT0..30.
- * Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters.
- */
-#define ARMPMU_MAX_HWEVENTS 32
-
-static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
-static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
-static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
-
-#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
-
-/* Set at runtime when we know what CPU type we are. */
-static struct arm_pmu *cpu_pmu;
-
-const char *perf_pmu_name(void)
-{
- if (!cpu_pmu)
- return NULL;
-
- return cpu_pmu->pmu.name;
-}
-EXPORT_SYMBOL_GPL(perf_pmu_name);
-
-int perf_num_counters(void)
-{
- int max_events = 0;
-
- if (cpu_pmu != NULL)
- max_events = cpu_pmu->num_events;
-
- return max_events;
-}
-EXPORT_SYMBOL_GPL(perf_num_counters);
-
-#define HW_OP_UNSUPPORTED 0xFFFF
-
-#define C(_x) \
- PERF_COUNT_HW_CACHE_##_x
-
-#define CACHE_OP_UNSUPPORTED 0xFFFF
-
static int
armpmu_map_cache_event(const unsigned (*cache_map)
[PERF_COUNT_HW_CACHE_MAX]
@@ -104,7 +51,7 @@
}
static int
-armpmu_map_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
+armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
{
int mapping = (*event_map)[config];
return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
@@ -116,19 +63,20 @@
return (int)(config & raw_event_mask);
}
-static int map_cpu_event(struct perf_event *event,
- const unsigned (*event_map)[PERF_COUNT_HW_MAX],
- const unsigned (*cache_map)
- [PERF_COUNT_HW_CACHE_MAX]
- [PERF_COUNT_HW_CACHE_OP_MAX]
- [PERF_COUNT_HW_CACHE_RESULT_MAX],
- u32 raw_event_mask)
+int
+armpmu_map_event(struct perf_event *event,
+ const unsigned (*event_map)[PERF_COUNT_HW_MAX],
+ const unsigned (*cache_map)
+ [PERF_COUNT_HW_CACHE_MAX]
+ [PERF_COUNT_HW_CACHE_OP_MAX]
+ [PERF_COUNT_HW_CACHE_RESULT_MAX],
+ u32 raw_event_mask)
{
u64 config = event->attr.config;
switch (event->attr.type) {
case PERF_TYPE_HARDWARE:
- return armpmu_map_event(event_map, config);
+ return armpmu_map_hw_event(event_map, config);
case PERF_TYPE_HW_CACHE:
return armpmu_map_cache_event(cache_map, config);
case PERF_TYPE_RAW:
@@ -222,7 +170,6 @@
*/
if (!(hwc->state & PERF_HES_STOPPED)) {
armpmu->disable(hwc, hwc->idx);
- barrier(); /* why? */
armpmu_event_update(event, hwc, hwc->idx);
hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
}
@@ -350,99 +297,41 @@
return 0;
}
-static irqreturn_t armpmu_platform_irq(int irq, void *dev)
+static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
{
struct arm_pmu *armpmu = (struct arm_pmu *) dev;
struct platform_device *plat_device = armpmu->plat_device;
struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev);
- return plat->handle_irq(irq, dev, armpmu->handle_irq);
+ if (plat && plat->handle_irq)
+ return plat->handle_irq(irq, dev, armpmu->handle_irq);
+ else
+ return armpmu->handle_irq(irq, dev);
}
static void
armpmu_release_hardware(struct arm_pmu *armpmu)
{
- int i, irq, irqs;
- struct platform_device *pmu_device = armpmu->plat_device;
- struct arm_pmu_platdata *plat =
- dev_get_platdata(&pmu_device->dev);
-
- irqs = min(pmu_device->num_resources, num_possible_cpus());
-
- for (i = 0; i < irqs; ++i) {
- if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
- continue;
- irq = platform_get_irq(pmu_device, i);
- if (irq >= 0) {
- if (plat && plat->disable_irq)
- plat->disable_irq(irq);
- free_irq(irq, armpmu);
- }
- }
-
- release_pmu(armpmu->type);
+ armpmu->free_irq();
+ pm_runtime_put_sync(&armpmu->plat_device->dev);
}
static int
armpmu_reserve_hardware(struct arm_pmu *armpmu)
{
- struct arm_pmu_platdata *plat;
- irq_handler_t handle_irq;
- int i, err, irq, irqs;
+ int err;
struct platform_device *pmu_device = armpmu->plat_device;
if (!pmu_device)
return -ENODEV;
- err = reserve_pmu(armpmu->type);
+ pm_runtime_get_sync(&pmu_device->dev);
+ err = armpmu->request_irq(armpmu_dispatch_irq);
if (err) {
- pr_warning("unable to reserve pmu\n");
+ armpmu_release_hardware(armpmu);
return err;
}
- plat = dev_get_platdata(&pmu_device->dev);
- if (plat && plat->handle_irq)
- handle_irq = armpmu_platform_irq;
- else
- handle_irq = armpmu->handle_irq;
-
- irqs = min(pmu_device->num_resources, num_possible_cpus());
- if (irqs < 1) {
- pr_err("no irqs for PMUs defined\n");
- return -ENODEV;
- }
-
- for (i = 0; i < irqs; ++i) {
- err = 0;
- irq = platform_get_irq(pmu_device, i);
- if (irq < 0)
- continue;
-
- /*
- * If we have a single PMU interrupt that we can't shift,
- * assume that we're running on a uniprocessor machine and
- * continue. Otherwise, continue without this interrupt.
- */
- if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
- pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
- irq, i);
- continue;
- }
-
- err = request_irq(irq, handle_irq,
- IRQF_DISABLED | IRQF_NOBALANCING,
- "arm-pmu", armpmu);
- if (err) {
- pr_err("unable to request IRQ%d for ARM PMU counters\n",
- irq);
- armpmu_release_hardware(armpmu);
- return err;
- } else if (plat && plat->enable_irq)
- plat->enable_irq(irq);
-
- cpumask_set_cpu(i, &armpmu->active_irqs);
- }
-
return 0;
}
@@ -581,6 +470,32 @@
armpmu->stop();
}
+#ifdef CONFIG_PM_RUNTIME
+static int armpmu_runtime_resume(struct device *dev)
+{
+ struct arm_pmu_platdata *plat = dev_get_platdata(dev);
+
+ if (plat && plat->runtime_resume)
+ return plat->runtime_resume(dev);
+
+ return 0;
+}
+
+static int armpmu_runtime_suspend(struct device *dev)
+{
+ struct arm_pmu_platdata *plat = dev_get_platdata(dev);
+
+ if (plat && plat->runtime_suspend)
+ return plat->runtime_suspend(dev);
+
+ return 0;
+}
+#endif
+
+const struct dev_pm_ops armpmu_dev_pm_ops = {
+ SET_RUNTIME_PM_OPS(armpmu_runtime_suspend, armpmu_runtime_resume, NULL)
+};
+
static void __init armpmu_init(struct arm_pmu *armpmu)
{
atomic_set(&armpmu->active_events, 0);
@@ -598,174 +513,14 @@
};
}
-int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type)
+int armpmu_register(struct arm_pmu *armpmu, char *name, int type)
{
armpmu_init(armpmu);
+ pr_info("enabled with %s PMU driver, %d counters available\n",
+ armpmu->name, armpmu->num_events);
return perf_pmu_register(&armpmu->pmu, name, type);
}
-/* Include the PMU-specific implementations. */
-#include "perf_event_xscale.c"
-#include "perf_event_v6.c"
-#include "perf_event_v7.c"
-
-/*
- * Ensure the PMU has sane values out of reset.
- * This requires SMP to be available, so exists as a separate initcall.
- */
-static int __init
-cpu_pmu_reset(void)
-{
- if (cpu_pmu && cpu_pmu->reset)
- return on_each_cpu(cpu_pmu->reset, NULL, 1);
- return 0;
-}
-arch_initcall(cpu_pmu_reset);
-
-/*
- * PMU platform driver and devicetree bindings.
- */
-static struct of_device_id armpmu_of_device_ids[] = {
- {.compatible = "arm,cortex-a9-pmu"},
- {.compatible = "arm,cortex-a8-pmu"},
- {.compatible = "arm,arm1136-pmu"},
- {.compatible = "arm,arm1176-pmu"},
- {},
-};
-
-static struct platform_device_id armpmu_plat_device_ids[] = {
- {.name = "arm-pmu"},
- {},
-};
-
-static int __devinit armpmu_device_probe(struct platform_device *pdev)
-{
- if (!cpu_pmu)
- return -ENODEV;
-
- cpu_pmu->plat_device = pdev;
- return 0;
-}
-
-static struct platform_driver armpmu_driver = {
- .driver = {
- .name = "arm-pmu",
- .of_match_table = armpmu_of_device_ids,
- },
- .probe = armpmu_device_probe,
- .id_table = armpmu_plat_device_ids,
-};
-
-static int __init register_pmu_driver(void)
-{
- return platform_driver_register(&armpmu_driver);
-}
-device_initcall(register_pmu_driver);
-
-static struct pmu_hw_events *armpmu_get_cpu_events(void)
-{
- return &__get_cpu_var(cpu_hw_events);
-}
-
-static void __init cpu_pmu_init(struct arm_pmu *armpmu)
-{
- int cpu;
- for_each_possible_cpu(cpu) {
- struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
- events->events = per_cpu(hw_events, cpu);
- events->used_mask = per_cpu(used_mask, cpu);
- raw_spin_lock_init(&events->pmu_lock);
- }
- armpmu->get_hw_events = armpmu_get_cpu_events;
- armpmu->type = ARM_PMU_DEVICE_CPU;
-}
-
-/*
- * PMU hardware loses all context when a CPU goes offline.
- * When a CPU is hotplugged back in, since some hardware registers are
- * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
- * junk values out of them.
- */
-static int __cpuinit pmu_cpu_notify(struct notifier_block *b,
- unsigned long action, void *hcpu)
-{
- if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
- return NOTIFY_DONE;
-
- if (cpu_pmu && cpu_pmu->reset)
- cpu_pmu->reset(NULL);
-
- return NOTIFY_OK;
-}
-
-static struct notifier_block __cpuinitdata pmu_cpu_notifier = {
- .notifier_call = pmu_cpu_notify,
-};
-
-/*
- * CPU PMU identification and registration.
- */
-static int __init
-init_hw_perf_events(void)
-{
- unsigned long cpuid = read_cpuid_id();
- unsigned long implementor = (cpuid & 0xFF000000) >> 24;
- unsigned long part_number = (cpuid & 0xFFF0);
-
- /* ARM Ltd CPUs. */
- if (0x41 == implementor) {
- switch (part_number) {
- case 0xB360: /* ARM1136 */
- case 0xB560: /* ARM1156 */
- case 0xB760: /* ARM1176 */
- cpu_pmu = armv6pmu_init();
- break;
- case 0xB020: /* ARM11mpcore */
- cpu_pmu = armv6mpcore_pmu_init();
- break;
- case 0xC080: /* Cortex-A8 */
- cpu_pmu = armv7_a8_pmu_init();
- break;
- case 0xC090: /* Cortex-A9 */
- cpu_pmu = armv7_a9_pmu_init();
- break;
- case 0xC050: /* Cortex-A5 */
- cpu_pmu = armv7_a5_pmu_init();
- break;
- case 0xC0F0: /* Cortex-A15 */
- cpu_pmu = armv7_a15_pmu_init();
- break;
- case 0xC070: /* Cortex-A7 */
- cpu_pmu = armv7_a7_pmu_init();
- break;
- }
- /* Intel CPUs [xscale]. */
- } else if (0x69 == implementor) {
- part_number = (cpuid >> 13) & 0x7;
- switch (part_number) {
- case 1:
- cpu_pmu = xscale1pmu_init();
- break;
- case 2:
- cpu_pmu = xscale2pmu_init();
- break;
- }
- }
-
- if (cpu_pmu) {
- pr_info("enabled with %s PMU driver, %d counters available\n",
- cpu_pmu->name, cpu_pmu->num_events);
- cpu_pmu_init(cpu_pmu);
- register_cpu_notifier(&pmu_cpu_notifier);
- armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW);
- } else {
- pr_info("no hardware support available\n");
- }
-
- return 0;
-}
-early_initcall(init_hw_perf_events);
-
/*
* Callchain handling code.
*/
diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c
new file mode 100644
index 0000000..8d7d8d4
--- /dev/null
+++ b/arch/arm/kernel/perf_event_cpu.c
@@ -0,0 +1,295 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (C) 2012 ARM Limited
+ *
+ * Author: Will Deacon <will.deacon@arm.com>
+ */
+#define pr_fmt(fmt) "CPU PMU: " fmt
+
+#include <linux/bitmap.h>
+#include <linux/export.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+
+#include <asm/cputype.h>
+#include <asm/irq_regs.h>
+#include <asm/pmu.h>
+
+/* Set at runtime when we know what CPU type we are. */
+static struct arm_pmu *cpu_pmu;
+
+static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
+static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
+static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
+
+/*
+ * Despite the names, these two functions are CPU-specific and are used
+ * by the OProfile/perf code.
+ */
+const char *perf_pmu_name(void)
+{
+ if (!cpu_pmu)
+ return NULL;
+
+ return cpu_pmu->pmu.name;
+}
+EXPORT_SYMBOL_GPL(perf_pmu_name);
+
+int perf_num_counters(void)
+{
+ int max_events = 0;
+
+ if (cpu_pmu != NULL)
+ max_events = cpu_pmu->num_events;
+
+ return max_events;
+}
+EXPORT_SYMBOL_GPL(perf_num_counters);
+
+/* Include the PMU-specific implementations. */
+#include "perf_event_xscale.c"
+#include "perf_event_v6.c"
+#include "perf_event_v7.c"
+
+static struct pmu_hw_events *cpu_pmu_get_cpu_events(void)
+{
+ return &__get_cpu_var(cpu_hw_events);
+}
+
+static void cpu_pmu_free_irq(void)
+{
+ int i, irq, irqs;
+ struct platform_device *pmu_device = cpu_pmu->plat_device;
+
+ irqs = min(pmu_device->num_resources, num_possible_cpus());
+
+ for (i = 0; i < irqs; ++i) {
+ if (!cpumask_test_and_clear_cpu(i, &cpu_pmu->active_irqs))
+ continue;
+ irq = platform_get_irq(pmu_device, i);
+ if (irq >= 0)
+ free_irq(irq, cpu_pmu);
+ }
+}
+
+static int cpu_pmu_request_irq(irq_handler_t handler)
+{
+ int i, err, irq, irqs;
+ struct platform_device *pmu_device = cpu_pmu->plat_device;
+
+ if (!pmu_device)
+ return -ENODEV;
+
+ irqs = min(pmu_device->num_resources, num_possible_cpus());
+ if (irqs < 1) {
+ pr_err("no irqs for PMUs defined\n");
+ return -ENODEV;
+ }
+
+ for (i = 0; i < irqs; ++i) {
+ err = 0;
+ irq = platform_get_irq(pmu_device, i);
+ if (irq < 0)
+ continue;
+
+ /*
+ * If we have a single PMU interrupt that we can't shift,
+ * assume that we're running on a uniprocessor machine and
+ * continue. Otherwise, continue without this interrupt.
+ */
+ if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
+ pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
+ irq, i);
+ continue;
+ }
+
+ err = request_irq(irq, handler, IRQF_NOBALANCING, "arm-pmu",
+ cpu_pmu);
+ if (err) {
+ pr_err("unable to request IRQ%d for ARM PMU counters\n",
+ irq);
+ return err;
+ }
+
+ cpumask_set_cpu(i, &cpu_pmu->active_irqs);
+ }
+
+ return 0;
+}
+
+static void __devinit cpu_pmu_init(struct arm_pmu *cpu_pmu)
+{
+ int cpu;
+ for_each_possible_cpu(cpu) {
+ struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
+ events->events = per_cpu(hw_events, cpu);
+ events->used_mask = per_cpu(used_mask, cpu);
+ raw_spin_lock_init(&events->pmu_lock);
+ }
+
+ cpu_pmu->get_hw_events = cpu_pmu_get_cpu_events;
+ cpu_pmu->request_irq = cpu_pmu_request_irq;
+ cpu_pmu->free_irq = cpu_pmu_free_irq;
+
+ /* Ensure the PMU has sane values out of reset. */
+ if (cpu_pmu && cpu_pmu->reset)
+ on_each_cpu(cpu_pmu->reset, NULL, 1);
+}
+
+/*
+ * PMU hardware loses all context when a CPU goes offline.
+ * When a CPU is hotplugged back in, since some hardware registers are
+ * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
+ * junk values out of them.
+ */
+static int __cpuinit cpu_pmu_notify(struct notifier_block *b,
+ unsigned long action, void *hcpu)
+{
+ if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
+ return NOTIFY_DONE;
+
+ if (cpu_pmu && cpu_pmu->reset)
+ cpu_pmu->reset(NULL);
+
+ return NOTIFY_OK;
+}
+
+static struct notifier_block __cpuinitdata cpu_pmu_hotplug_notifier = {
+ .notifier_call = cpu_pmu_notify,
+};
+
+/*
+ * PMU platform driver and devicetree bindings.
+ */
+static struct of_device_id __devinitdata cpu_pmu_of_device_ids[] = {
+ {.compatible = "arm,cortex-a15-pmu", .data = armv7_a15_pmu_init},
+ {.compatible = "arm,cortex-a9-pmu", .data = armv7_a9_pmu_init},
+ {.compatible = "arm,cortex-a8-pmu", .data = armv7_a8_pmu_init},
+ {.compatible = "arm,cortex-a7-pmu", .data = armv7_a7_pmu_init},
+ {.compatible = "arm,cortex-a5-pmu", .data = armv7_a5_pmu_init},
+ {.compatible = "arm,arm11mpcore-pmu", .data = armv6mpcore_pmu_init},
+ {.compatible = "arm,arm1176-pmu", .data = armv6pmu_init},
+ {.compatible = "arm,arm1136-pmu", .data = armv6pmu_init},
+ {},
+};
+
+static struct platform_device_id __devinitdata cpu_pmu_plat_device_ids[] = {
+ {.name = "arm-pmu"},
+ {},
+};
+
+/*
+ * CPU PMU identification and probing.
+ */
+static struct arm_pmu *__devinit probe_current_pmu(void)
+{
+ struct arm_pmu *pmu = NULL;
+ int cpu = get_cpu();
+ unsigned long cpuid = read_cpuid_id();
+ unsigned long implementor = (cpuid & 0xFF000000) >> 24;
+ unsigned long part_number = (cpuid & 0xFFF0);
+
+ pr_info("probing PMU on CPU %d\n", cpu);
+
+ /* ARM Ltd CPUs. */
+ if (0x41 == implementor) {
+ switch (part_number) {
+ case 0xB360: /* ARM1136 */
+ case 0xB560: /* ARM1156 */
+ case 0xB760: /* ARM1176 */
+ pmu = armv6pmu_init();
+ break;
+ case 0xB020: /* ARM11mpcore */
+ pmu = armv6mpcore_pmu_init();
+ break;
+ case 0xC080: /* Cortex-A8 */
+ pmu = armv7_a8_pmu_init();
+ break;
+ case 0xC090: /* Cortex-A9 */
+ pmu = armv7_a9_pmu_init();
+ break;
+ case 0xC050: /* Cortex-A5 */
+ pmu = armv7_a5_pmu_init();
+ break;
+ case 0xC0F0: /* Cortex-A15 */
+ pmu = armv7_a15_pmu_init();
+ break;
+ case 0xC070: /* Cortex-A7 */
+ pmu = armv7_a7_pmu_init();
+ break;
+ }
+ /* Intel CPUs [xscale]. */
+ } else if (0x69 == implementor) {
+ part_number = (cpuid >> 13) & 0x7;
+ switch (part_number) {
+ case 1:
+ pmu = xscale1pmu_init();
+ break;
+ case 2:
+ pmu = xscale2pmu_init();
+ break;
+ }
+ }
+
+ put_cpu();
+ return pmu;
+}
+
+static int __devinit cpu_pmu_device_probe(struct platform_device *pdev)
+{
+ const struct of_device_id *of_id;
+ struct arm_pmu *(*init_fn)(void);
+ struct device_node *node = pdev->dev.of_node;
+
+ if (cpu_pmu) {
+ pr_info("attempt to register multiple PMU devices!");
+ return -ENOSPC;
+ }
+
+ if (node && (of_id = of_match_node(cpu_pmu_of_device_ids, pdev->dev.of_node))) {
+ init_fn = of_id->data;
+ cpu_pmu = init_fn();
+ } else {
+ cpu_pmu = probe_current_pmu();
+ }
+
+ if (!cpu_pmu)
+ return -ENODEV;
+
+ cpu_pmu->plat_device = pdev;
+ cpu_pmu_init(cpu_pmu);
+ register_cpu_notifier(&cpu_pmu_hotplug_notifier);
+ armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW);
+
+ return 0;
+}
+
+static struct platform_driver cpu_pmu_driver = {
+ .driver = {
+ .name = "arm-pmu",
+ .pm = &armpmu_dev_pm_ops,
+ .of_match_table = cpu_pmu_of_device_ids,
+ },
+ .probe = cpu_pmu_device_probe,
+ .id_table = cpu_pmu_plat_device_ids,
+};
+
+static int __init register_pmu_driver(void)
+{
+ return platform_driver_register(&cpu_pmu_driver);
+}
+device_initcall(register_pmu_driver);
diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c
index c90fcb2..6ccc079 100644
--- a/arch/arm/kernel/perf_event_v6.c
+++ b/arch/arm/kernel/perf_event_v6.c
@@ -645,7 +645,7 @@
static int armv6_map_event(struct perf_event *event)
{
- return map_cpu_event(event, &armv6_perf_map,
+ return armpmu_map_event(event, &armv6_perf_map,
&armv6_perf_cache_map, 0xFF);
}
@@ -664,7 +664,7 @@
.max_period = (1LLU << 32) - 1,
};
-static struct arm_pmu *__init armv6pmu_init(void)
+static struct arm_pmu *__devinit armv6pmu_init(void)
{
return &armv6pmu;
}
@@ -679,7 +679,7 @@
static int armv6mpcore_map_event(struct perf_event *event)
{
- return map_cpu_event(event, &armv6mpcore_perf_map,
+ return armpmu_map_event(event, &armv6mpcore_perf_map,
&armv6mpcore_perf_cache_map, 0xFF);
}
@@ -698,17 +698,17 @@
.max_period = (1LLU << 32) - 1,
};
-static struct arm_pmu *__init armv6mpcore_pmu_init(void)
+static struct arm_pmu *__devinit armv6mpcore_pmu_init(void)
{
return &armv6mpcore_pmu;
}
#else
-static struct arm_pmu *__init armv6pmu_init(void)
+static struct arm_pmu *__devinit armv6pmu_init(void)
{
return NULL;
}
-static struct arm_pmu *__init armv6mpcore_pmu_init(void)
+static struct arm_pmu *__devinit armv6mpcore_pmu_init(void)
{
return NULL;
}
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index f04070b..bd4b090 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -1204,31 +1204,31 @@
static int armv7_a8_map_event(struct perf_event *event)
{
- return map_cpu_event(event, &armv7_a8_perf_map,
+ return armpmu_map_event(event, &armv7_a8_perf_map,
&armv7_a8_perf_cache_map, 0xFF);
}
static int armv7_a9_map_event(struct perf_event *event)
{
- return map_cpu_event(event, &armv7_a9_perf_map,
+ return armpmu_map_event(event, &armv7_a9_perf_map,
&armv7_a9_perf_cache_map, 0xFF);
}
static int armv7_a5_map_event(struct perf_event *event)
{
- return map_cpu_event(event, &armv7_a5_perf_map,
+ return armpmu_map_event(event, &armv7_a5_perf_map,
&armv7_a5_perf_cache_map, 0xFF);
}
static int armv7_a15_map_event(struct perf_event *event)
{
- return map_cpu_event(event, &armv7_a15_perf_map,
+ return armpmu_map_event(event, &armv7_a15_perf_map,
&armv7_a15_perf_cache_map, 0xFF);
}
static int armv7_a7_map_event(struct perf_event *event)
{
- return map_cpu_event(event, &armv7_a7_perf_map,
+ return armpmu_map_event(event, &armv7_a7_perf_map,
&armv7_a7_perf_cache_map, 0xFF);
}
@@ -1245,7 +1245,7 @@
.max_period = (1LLU << 32) - 1,
};
-static u32 __init armv7_read_num_pmnc_events(void)
+static u32 __devinit armv7_read_num_pmnc_events(void)
{
u32 nb_cnt;
@@ -1256,7 +1256,7 @@
return nb_cnt + 1;
}
-static struct arm_pmu *__init armv7_a8_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a8_pmu_init(void)
{
armv7pmu.name = "ARMv7 Cortex-A8";
armv7pmu.map_event = armv7_a8_map_event;
@@ -1264,7 +1264,7 @@
return &armv7pmu;
}
-static struct arm_pmu *__init armv7_a9_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a9_pmu_init(void)
{
armv7pmu.name = "ARMv7 Cortex-A9";
armv7pmu.map_event = armv7_a9_map_event;
@@ -1272,7 +1272,7 @@
return &armv7pmu;
}
-static struct arm_pmu *__init armv7_a5_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a5_pmu_init(void)
{
armv7pmu.name = "ARMv7 Cortex-A5";
armv7pmu.map_event = armv7_a5_map_event;
@@ -1280,7 +1280,7 @@
return &armv7pmu;
}
-static struct arm_pmu *__init armv7_a15_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a15_pmu_init(void)
{
armv7pmu.name = "ARMv7 Cortex-A15";
armv7pmu.map_event = armv7_a15_map_event;
@@ -1289,7 +1289,7 @@
return &armv7pmu;
}
-static struct arm_pmu *__init armv7_a7_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a7_pmu_init(void)
{
armv7pmu.name = "ARMv7 Cortex-A7";
armv7pmu.map_event = armv7_a7_map_event;
@@ -1298,27 +1298,27 @@
return &armv7pmu;
}
#else
-static struct arm_pmu *__init armv7_a8_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a8_pmu_init(void)
{
return NULL;
}
-static struct arm_pmu *__init armv7_a9_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a9_pmu_init(void)
{
return NULL;
}
-static struct arm_pmu *__init armv7_a5_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a5_pmu_init(void)
{
return NULL;
}
-static struct arm_pmu *__init armv7_a15_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a15_pmu_init(void)
{
return NULL;
}
-static struct arm_pmu *__init armv7_a7_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a7_pmu_init(void)
{
return NULL;
}
diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c
index f759fe0..426e19f 100644
--- a/arch/arm/kernel/perf_event_xscale.c
+++ b/arch/arm/kernel/perf_event_xscale.c
@@ -430,7 +430,7 @@
static int xscale_map_event(struct perf_event *event)
{
- return map_cpu_event(event, &xscale_perf_map,
+ return armpmu_map_event(event, &xscale_perf_map,
&xscale_perf_cache_map, 0xFF);
}
@@ -449,7 +449,7 @@
.max_period = (1LLU << 32) - 1,
};
-static struct arm_pmu *__init xscale1pmu_init(void)
+static struct arm_pmu *__devinit xscale1pmu_init(void)
{
return &xscale1pmu;
}
@@ -816,17 +816,17 @@
.max_period = (1LLU << 32) - 1,
};
-static struct arm_pmu *__init xscale2pmu_init(void)
+static struct arm_pmu *__devinit xscale2pmu_init(void)
{
return &xscale2pmu;
}
#else
-static struct arm_pmu *__init xscale1pmu_init(void)
+static struct arm_pmu *__devinit xscale1pmu_init(void)
{
return NULL;
}
-static struct arm_pmu *__init xscale2pmu_init(void)
+static struct arm_pmu *__devinit xscale2pmu_init(void)
{
return NULL;
}
diff --git a/arch/arm/kernel/pmu.c b/arch/arm/kernel/pmu.c
deleted file mode 100644
index 2334bf8..0000000
--- a/arch/arm/kernel/pmu.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * linux/arch/arm/kernel/pmu.c
- *
- * Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
- * Copyright (C) 2010 ARM Ltd, Will Deacon
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/err.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-
-#include <asm/pmu.h>
-
-/*
- * PMU locking to ensure mutual exclusion between different subsystems.
- */
-static unsigned long pmu_lock[BITS_TO_LONGS(ARM_NUM_PMU_DEVICES)];
-
-int
-reserve_pmu(enum arm_pmu_type type)
-{
- return test_and_set_bit_lock(type, pmu_lock) ? -EBUSY : 0;
-}
-EXPORT_SYMBOL_GPL(reserve_pmu);
-
-void
-release_pmu(enum arm_pmu_type type)
-{
- clear_bit_unlock(type, pmu_lock);
-}
-EXPORT_SYMBOL_GPL(release_pmu);
diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c
index 45c97b1..c18a504 100644
--- a/arch/arm/mach-bcmring/arch.c
+++ b/arch/arm/mach-bcmring/arch.c
@@ -29,7 +29,6 @@
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/time.h>
-#include <asm/pmu.h>
#include <asm/mach/arch.h>
#include <mach/dma.h>
@@ -38,7 +37,7 @@
#include <mach/csp/chipcHw_def.h>
#include <mach/csp/chipcHw_inline.h>
-#include <cfg_global.h>
+#include <mach/cfg_global.h>
#include "core.h"
@@ -116,7 +115,7 @@
static struct platform_device pmu_device = {
.name = "arm-pmu",
- .id = ARM_PMU_DEVICE_CPU,
+ .id = -1,
.resource = &pmu_resource,
.num_resources = 1,
};
diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c
index adbfb19..4b50228 100644
--- a/arch/arm/mach-bcmring/core.c
+++ b/arch/arm/mach-bcmring/core.c
@@ -43,11 +43,10 @@
#include <asm/mach/time.h>
#include <asm/mach/map.h>
-#include <cfg_global.h>
+#include <mach/cfg_global.h>
#include "clock.h"
-#include <csp/secHw.h>
#include <mach/csp/secHw_def.h>
#include <mach/csp/chipcHw_inline.h>
#include <mach/csp/tmrHw_reg.h>
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
index 96273ff..5050833 100644
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
@@ -26,15 +26,15 @@
/* ---- Include Files ---------------------------------------------------- */
-#include <csp/errno.h>
-#include <csp/stdint.h>
-#include <csp/module.h>
+#include <linux/errno.h>
+#include <linux/types.h>
+#include <linux/export.h>
#include <mach/csp/chipcHw_def.h>
#include <mach/csp/chipcHw_inline.h>
-#include <csp/reg.h>
-#include <csp/delay.h>
+#include <mach/csp/reg.h>
+#include <linux/delay.h>
/* ---- Private Constants and Types --------------------------------------- */
@@ -61,21 +61,21 @@
/****************************************************************************/
chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock /* [ IN ] Configurable clock */
) {
- volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
- volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
- volatile uint32_t *pDependentClock = (uint32_t *) 0x0;
+ uint32_t __iomem *pPLLReg = NULL;
+ uint32_t __iomem *pClockCtrl = NULL;
+ uint32_t __iomem *pDependentClock = NULL;
uint32_t vcoFreqPll1Hz = 0; /* Effective VCO frequency for PLL1 in Hz */
uint32_t vcoFreqPll2Hz = 0; /* Effective VCO frequency for PLL2 in Hz */
uint32_t dependentClockType = 0;
uint32_t vcoHz = 0;
/* Get VCO frequencies */
- if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
+ if ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
uint64_t adjustFreq = 0;
vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
- ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+ ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
/* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
@@ -86,13 +86,13 @@
} else {
vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
- ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+ ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
}
vcoFreqPll2Hz =
chipcHw_XTAL_FREQ_Hz *
chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
- ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+ ((readl(&pChipcHw->PLLPreDivider2) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
switch (clock) {
@@ -187,51 +187,51 @@
if (pPLLReg) {
/* Obtain PLL clock frequency */
- if (*pPLLReg & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
+ if (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
/* Return crystal clock frequency when bypassed */
return chipcHw_XTAL_FREQ_Hz;
} else if (clock == chipcHw_CLOCK_DDR) {
/* DDR frequency is configured in PLLDivider register */
- return chipcHw_divide (vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256));
+ return chipcHw_divide (vcoHz, (((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) ? ((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) : 256));
} else {
/* From chip revision number B0, LCD clock is internally divided by 2 */
if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
vcoHz >>= 1;
}
/* Obtain PLL clock frequency using VCO dividers */
- return chipcHw_divide(vcoHz, ((*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
+ return chipcHw_divide(vcoHz, ((readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
}
} else if (pClockCtrl) {
/* Obtain divider clock frequency */
uint32_t div;
uint32_t freq = 0;
- if (*pClockCtrl & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
+ if (readl(pClockCtrl) & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
/* Return crystal clock frequency when bypassed */
return chipcHw_XTAL_FREQ_Hz;
} else if (pDependentClock) {
/* Identify the dependent clock frequency */
switch (dependentClockType) {
case PLL_CLOCK:
- if (*pDependentClock & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
+ if (readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
/* Use crystal clock frequency when dependent PLL clock is bypassed */
freq = chipcHw_XTAL_FREQ_Hz;
} else {
/* Obtain PLL clock frequency using VCO dividers */
- div = *pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK;
+ div = readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_MDIV_MASK;
freq = div ? chipcHw_divide(vcoHz, div) : 0;
}
break;
case NON_PLL_CLOCK:
- if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) {
+ if (pDependentClock == &pChipcHw->ACLKClock) {
freq = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS);
} else {
- if (*pDependentClock & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
+ if (readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
/* Use crystal clock frequency when dependent divider clock is bypassed */
freq = chipcHw_XTAL_FREQ_Hz;
} else {
/* Obtain divider clock frequency using XTAL dividers */
- div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK;
+ div = readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_DIV_MASK;
freq = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, (div ? div : 256));
}
}
@@ -242,7 +242,7 @@
freq = chipcHw_XTAL_FREQ_Hz;
}
- div = *pClockCtrl & chipcHw_REG_DIV_CLOCK_DIV_MASK;
+ div = readl(pClockCtrl) & chipcHw_REG_DIV_CLOCK_DIV_MASK;
return chipcHw_divide(freq, (div ? div : 256));
}
return 0;
@@ -261,9 +261,9 @@
chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock, /* [ IN ] Configurable clock */
uint32_t freq /* [ IN ] Clock frequency in Hz */
) {
- volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
- volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
- volatile uint32_t *pDependentClock = (uint32_t *) 0x0;
+ uint32_t __iomem *pPLLReg = NULL;
+ uint32_t __iomem *pClockCtrl = NULL;
+ uint32_t __iomem *pDependentClock = NULL;
uint32_t vcoFreqPll1Hz = 0; /* Effective VCO frequency for PLL1 in Hz */
uint32_t desVcoFreqPll1Hz = 0; /* Desired VCO frequency for PLL1 in Hz */
uint32_t vcoFreqPll2Hz = 0; /* Effective VCO frequency for PLL2 in Hz */
@@ -272,12 +272,12 @@
uint32_t desVcoHz = 0;
/* Get VCO frequencies */
- if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
+ if ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
uint64_t adjustFreq = 0;
vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
- ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+ ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
/* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
@@ -289,16 +289,16 @@
/* Desired VCO frequency */
desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
- (((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+ (((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) + 1);
} else {
vcoFreqPll1Hz = desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
- ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+ ((readl(&pChipcHw->PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
}
vcoFreqPll2Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
- ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+ ((readl(&pChipcHw->PLLPreDivider2) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
switch (clock) {
@@ -307,8 +307,7 @@
{
REG_LOCAL_IRQ_SAVE;
/* Dvide DDR_phy by two to obtain DDR_ctrl clock */
- pChipcHw->DDRClock = (pChipcHw->DDRClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1)
- << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT);
+ writel((readl(&pChipcHw->DDRClock) & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT), &pChipcHw->DDRClock);
REG_LOCAL_IRQ_RESTORE;
}
pPLLReg = &pChipcHw->DDRClock;
@@ -329,8 +328,7 @@
/* Configure the VPM:BUS ratio settings */
{
REG_LOCAL_IRQ_SAVE;
- pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1)
- << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT);
+ writel((readl(&pChipcHw->VPMClock) & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1) << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT), &pChipcHw->VPMClock);
REG_LOCAL_IRQ_RESTORE;
}
pPLLReg = &pChipcHw->VPMClock;
@@ -428,9 +426,9 @@
/* For DDR settings use only the PLL divider clock */
if (pPLLReg == &pChipcHw->DDRClock) {
/* Set M1DIV for PLL1, which controls the DDR clock */
- reg32_write(&pChipcHw->PLLDivider, (pChipcHw->PLLDivider & 0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24));
+ reg32_write(&pChipcHw->PLLDivider, (readl(&pChipcHw->PLLDivider) & 0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24));
/* Calculate expected frequency */
- freq = chipcHw_divide(vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256));
+ freq = chipcHw_divide(vcoHz, (((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) ? ((readl(&pChipcHw->PLLDivider) & 0xFF000000) >> 24) : 256));
} else {
/* From chip revision number B0, LCD clock is internally divided by 2 */
if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
@@ -441,7 +439,7 @@
reg32_modify_and(pPLLReg, ~(chipcHw_REG_PLL_CLOCK_MDIV_MASK));
reg32_modify_or(pPLLReg, chipcHw_REG_PLL_DIVIDER_MDIV(desVcoHz, freq));
/* Calculate expected frequency */
- freq = chipcHw_divide(vcoHz, ((*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
+ freq = chipcHw_divide(vcoHz, ((readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (readl(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
}
/* Wait for for atleast 200ns as per the protocol to change frequency */
udelay(1);
@@ -460,16 +458,16 @@
if (pDependentClock) {
switch (dependentClockType) {
case PLL_CLOCK:
- divider = chipcHw_divide(chipcHw_divide (desVcoHz, (*pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq);
+ divider = chipcHw_divide(chipcHw_divide (desVcoHz, (readl(pDependentClock) & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq);
break;
case NON_PLL_CLOCK:
{
uint32_t sourceClock = 0;
- if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) {
+ if (pDependentClock == &pChipcHw->ACLKClock) {
sourceClock = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS);
} else {
- uint32_t div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK;
+ uint32_t div = readl(pDependentClock) & chipcHw_REG_DIV_CLOCK_DIV_MASK;
sourceClock = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, ((div) ? div : 256));
}
divider = chipcHw_divide(sourceClock, freq);
@@ -483,7 +481,7 @@
if (divider) {
REG_LOCAL_IRQ_SAVE;
/* Set the divider to obtain the required frequency */
- *pClockCtrl = (*pClockCtrl & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | (((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & chipcHw_REG_DIV_CLOCK_DIV_MASK);
+ writel((readl(pClockCtrl) & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | (((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & chipcHw_REG_DIV_CLOCK_DIV_MASK), pClockCtrl);
REG_LOCAL_IRQ_RESTORE;
return freq;
}
@@ -515,25 +513,26 @@
int count = 0;
for (iter = 0; (iter < MAX_PHASE_ALIGN_ATTEMPTS) && (adjustCount < MAX_PHASE_ADJUST_COUNT); iter++) {
- phaseControl = (pChipcHw->VPMClock & chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT;
+ phaseControl = (readl(&pChipcHw->VPMClock) & chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT;
phaseValue = 0;
prevPhaseComp = 0;
/* Step 1: Look for falling PH_COMP transition */
/* Read the contents of VPM Clock resgister */
- phaseValue = pChipcHw->VPMClock;
+ phaseValue = readl(&pChipcHw->VPMClock);
do {
/* Store previous value of phase comparator */
prevPhaseComp = phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP;
/* Change the value of PH_CTRL. */
- reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+ reg32_write(&pChipcHw->VPMClock,
+ (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
/* Wait atleast 20 ns */
udelay(1);
/* Toggle the LOAD_CH after phase control is written. */
- pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+ writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
/* Read the contents of VPM Clock resgister. */
- phaseValue = pChipcHw->VPMClock;
+ phaseValue = readl(&pChipcHw->VPMClock);
if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) {
phaseControl = (0x3F & (phaseControl - 1));
@@ -557,12 +556,13 @@
for (count = 0; (count < 5) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) {
phaseControl = (0x3F & (phaseControl + 1));
- reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+ reg32_write(&pChipcHw->VPMClock,
+ (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
/* Wait atleast 20 ns */
udelay(1);
/* Toggle the LOAD_CH after phase control is written. */
- pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
- phaseValue = pChipcHw->VPMClock;
+ writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
+ phaseValue = readl(&pChipcHw->VPMClock);
/* Count number of adjustment made */
adjustCount++;
}
@@ -581,12 +581,13 @@
for (count = 0; (count < 3) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) {
phaseControl = (0x3F & (phaseControl - 1));
- reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+ reg32_write(&pChipcHw->VPMClock,
+ (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
/* Wait atleast 20 ns */
udelay(1);
/* Toggle the LOAD_CH after phase control is written. */
- pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
- phaseValue = pChipcHw->VPMClock;
+ writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
+ phaseValue = readl(&pChipcHw->VPMClock);
/* Count number of adjustment made */
adjustCount++;
}
@@ -605,12 +606,13 @@
for (count = 0; (count < 5); count++) {
phaseControl = (0x3F & (phaseControl - 1));
- reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+ reg32_write(&pChipcHw->VPMClock,
+ (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
/* Wait atleast 20 ns */
udelay(1);
/* Toggle the LOAD_CH after phase control is written. */
- pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
- phaseValue = pChipcHw->VPMClock;
+ writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
+ phaseValue = readl(&pChipcHw->VPMClock);
/* Count number of adjustment made */
adjustCount++;
}
@@ -631,14 +633,14 @@
/* Store previous value of phase comparator */
prevPhaseComp = phaseValue;
/* Change the value of PH_CTRL. */
- reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+ reg32_write(&pChipcHw->VPMClock,
+ (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
/* Wait atleast 20 ns */
udelay(1);
/* Toggle the LOAD_CH after phase control is written. */
- pChipcHw->VPMClock ^=
- chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+ writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
/* Read the contents of VPM Clock resgister. */
- phaseValue = pChipcHw->VPMClock;
+ phaseValue = readl(&pChipcHw->VPMClock);
if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) {
phaseControl = (0x3F & (phaseControl - 1));
@@ -661,13 +663,13 @@
}
/* For VPM Phase should be perfectly aligned. */
- phaseControl = (((pChipcHw->VPMClock >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F);
+ phaseControl = (((readl(&pChipcHw->VPMClock) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F);
{
REG_LOCAL_IRQ_SAVE;
- pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT);
+ writel((readl(&pChipcHw->VPMClock) & ~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT), &pChipcHw->VPMClock);
/* Load new phase value */
- pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+ writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
REG_LOCAL_IRQ_RESTORE;
}
@@ -697,7 +699,7 @@
int adjustCount = 0;
/* Disable VPM access */
- pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
+ writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1);
/* Disable HW VPM phase alignment */
chipcHw_vpmHwPhaseAlignDisable();
/* Enable SW VPM phase alignment */
@@ -715,23 +717,24 @@
phaseControl--;
} else {
/* Enable VPM access */
- pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
+ writel(readl(&pChipcHw->Spare1) | chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1);
/* Return adjust count */
return adjustCount;
}
/* Change the value of PH_CTRL. */
- reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+ reg32_write(&pChipcHw->VPMClock,
+ (readl(&pChipcHw->VPMClock) & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
/* Wait atleast 20 ns */
udelay(1);
/* Toggle the LOAD_CH after phase control is written. */
- pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+ writel(readl(&pChipcHw->VPMClock) ^ chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE, &pChipcHw->VPMClock);
/* Count adjustment */
adjustCount++;
}
}
/* Disable VPM access */
- pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
+ writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE, &pChipcHw->Spare1);
return -1;
}
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
index 367df75..8377d80 100644
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
@@ -26,15 +26,15 @@
/* ---- Include Files ---------------------------------------------------- */
-#include <csp/errno.h>
-#include <csp/stdint.h>
-#include <csp/module.h>
+#include <linux/errno.h>
+#include <linux/types.h>
+#include <linux/export.h>
#include <mach/csp/chipcHw_def.h>
#include <mach/csp/chipcHw_inline.h>
-#include <csp/reg.h>
-#include <csp/delay.h>
+#include <mach/csp/reg.h>
+#include <linux/delay.h>
/* ---- Private Constants and Types --------------------------------------- */
/*
@@ -73,9 +73,9 @@
{
REG_LOCAL_IRQ_SAVE;
- pChipcHw->PLLConfig2 =
- chipcHw_REG_PLL_CONFIG_D_RESET |
- chipcHw_REG_PLL_CONFIG_A_RESET;
+ writel(chipcHw_REG_PLL_CONFIG_D_RESET |
+ chipcHw_REG_PLL_CONFIG_A_RESET,
+ &pChipcHw->PLLConfig2);
pllPreDivider2 = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
@@ -87,28 +87,30 @@
chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
/* Enable CHIPC registers to control the PLL */
- pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
+ writel(readl(&pChipcHw->PLLStatus) | chipcHw_REG_PLL_STATUS_CONTROL_ENABLE, &pChipcHw->PLLStatus);
/* Set pre divider to get desired VCO frequency */
- pChipcHw->PLLPreDivider2 = pllPreDivider2;
+ writel(pllPreDivider2, &pChipcHw->PLLPreDivider2);
/* Set NDIV Frac */
- pChipcHw->PLLDivider2 = chipcHw_REG_PLL_DIVIDER_NDIV_f;
+ writel(chipcHw_REG_PLL_DIVIDER_NDIV_f, &pChipcHw->PLLDivider2);
/* This has to be removed once the default values are fixed for PLL2. */
- pChipcHw->PLLControl12 = 0x38000700;
- pChipcHw->PLLControl22 = 0x00000015;
+ writel(0x38000700, &pChipcHw->PLLControl12);
+ writel(0x00000015, &pChipcHw->PLLControl22);
/* Reset PLL2 */
if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
- pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
+ writel(chipcHw_REG_PLL_CONFIG_D_RESET |
chipcHw_REG_PLL_CONFIG_A_RESET |
chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
- chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+ chipcHw_REG_PLL_CONFIG_POWER_DOWN,
+ &pChipcHw->PLLConfig2);
} else {
- pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
+ writel(chipcHw_REG_PLL_CONFIG_D_RESET |
chipcHw_REG_PLL_CONFIG_A_RESET |
chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
- chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+ chipcHw_REG_PLL_CONFIG_POWER_DOWN,
+ &pChipcHw->PLLConfig2);
}
REG_LOCAL_IRQ_RESTORE;
}
@@ -119,22 +121,25 @@
{
REG_LOCAL_IRQ_SAVE;
/* Remove analog reset and Power on the PLL */
- pChipcHw->PLLConfig2 &=
+ writel(readl(&pChipcHw->PLLConfig2) &
~(chipcHw_REG_PLL_CONFIG_A_RESET |
- chipcHw_REG_PLL_CONFIG_POWER_DOWN);
+ chipcHw_REG_PLL_CONFIG_POWER_DOWN),
+ &pChipcHw->PLLConfig2);
REG_LOCAL_IRQ_RESTORE;
}
/* Wait until PLL is locked */
- while (!(pChipcHw->PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
+ while (!(readl(&pChipcHw->PLLStatus2) & chipcHw_REG_PLL_STATUS_LOCKED))
;
{
REG_LOCAL_IRQ_SAVE;
/* Remove digital reset */
- pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
+ writel(readl(&pChipcHw->PLLConfig2) &
+ ~chipcHw_REG_PLL_CONFIG_D_RESET,
+ &pChipcHw->PLLConfig2);
REG_LOCAL_IRQ_RESTORE;
}
@@ -157,9 +162,9 @@
{
REG_LOCAL_IRQ_SAVE;
- pChipcHw->PLLConfig =
- chipcHw_REG_PLL_CONFIG_D_RESET |
- chipcHw_REG_PLL_CONFIG_A_RESET;
+ writel(chipcHw_REG_PLL_CONFIG_D_RESET |
+ chipcHw_REG_PLL_CONFIG_A_RESET,
+ &pChipcHw->PLLConfig);
/* Setting VCO frequency */
if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
pllPreDivider =
@@ -182,30 +187,22 @@
}
/* Enable CHIPC registers to control the PLL */
- pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
+ writel(readl(&pChipcHw->PLLStatus) | chipcHw_REG_PLL_STATUS_CONTROL_ENABLE, &pChipcHw->PLLStatus);
/* Set pre divider to get desired VCO frequency */
- pChipcHw->PLLPreDivider = pllPreDivider;
+ writel(pllPreDivider, &pChipcHw->PLLPreDivider);
/* Set NDIV Frac */
if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
- pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
- chipcHw_REG_PLL_DIVIDER_NDIV_f_SS;
+ writel(chipcHw_REG_PLL_DIVIDER_M1DIV | chipcHw_REG_PLL_DIVIDER_NDIV_f_SS, &pChipcHw->PLLDivider);
} else {
- pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
- chipcHw_REG_PLL_DIVIDER_NDIV_f;
+ writel(chipcHw_REG_PLL_DIVIDER_M1DIV | chipcHw_REG_PLL_DIVIDER_NDIV_f, &pChipcHw->PLLDivider);
}
/* Reset PLL1 */
if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
- pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
- chipcHw_REG_PLL_CONFIG_A_RESET |
- chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
- chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+ writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_1601_3200 | chipcHw_REG_PLL_CONFIG_POWER_DOWN, &pChipcHw->PLLConfig);
} else {
- pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
- chipcHw_REG_PLL_CONFIG_A_RESET |
- chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
- chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+ writel(chipcHw_REG_PLL_CONFIG_D_RESET | chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_VCO_800_1600 | chipcHw_REG_PLL_CONFIG_POWER_DOWN, &pChipcHw->PLLConfig);
}
REG_LOCAL_IRQ_RESTORE;
@@ -216,22 +213,19 @@
{
REG_LOCAL_IRQ_SAVE;
/* Remove analog reset and Power on the PLL */
- pChipcHw->PLLConfig &=
- ~(chipcHw_REG_PLL_CONFIG_A_RESET |
- chipcHw_REG_PLL_CONFIG_POWER_DOWN);
+ writel(readl(&pChipcHw->PLLConfig) & ~(chipcHw_REG_PLL_CONFIG_A_RESET | chipcHw_REG_PLL_CONFIG_POWER_DOWN), &pChipcHw->PLLConfig);
REG_LOCAL_IRQ_RESTORE;
}
/* Wait until PLL is locked */
- while (!(pChipcHw->PLLStatus & chipcHw_REG_PLL_STATUS_LOCKED)
- || !(pChipcHw->
- PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
+ while (!(readl(&pChipcHw->PLLStatus) & chipcHw_REG_PLL_STATUS_LOCKED)
+ || !(readl(&pChipcHw->PLLStatus2) & chipcHw_REG_PLL_STATUS_LOCKED))
;
/* Remove digital reset */
{
REG_LOCAL_IRQ_SAVE;
- pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
+ writel(readl(&pChipcHw->PLLConfig) & ~chipcHw_REG_PLL_CONFIG_D_RESET, &pChipcHw->PLLConfig);
REG_LOCAL_IRQ_RESTORE;
}
}
@@ -267,11 +261,7 @@
chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_SOFT_RESET);
/* Before configuring the ARM clock, atleast we need to make sure BUS clock maintains the proper ratio with ARM clock */
- pChipcHw->ACLKClock =
- (pChipcHw->
- ACLKClock & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam->
- armBusRatio &
- chipcHw_REG_ACLKClock_CLK_DIV_MASK);
+ writel((readl(&pChipcHw->ACLKClock) & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam-> armBusRatio & chipcHw_REG_ACLKClock_CLK_DIV_MASK), &pChipcHw->ACLKClock);
/* Set various core component frequencies. The order in which this is done is important for some. */
/* The RTBUS (DDR PHY) is derived from the BUS, and the BUS from the ARM, and VPM needs to know BUS */
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
index 2671d88..f95ce91 100644
--- a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
@@ -13,11 +13,11 @@
*****************************************************************************/
/* ---- Include Files ---------------------------------------------------- */
-#include <csp/stdint.h>
+#include <linux/types.h>
#include <mach/csp/chipcHw_def.h>
#include <mach/csp/chipcHw_inline.h>
-#include <csp/intcHw.h>
-#include <csp/cache.h>
+#include <mach/csp/intcHw_reg.h>
+#include <asm/cacheflush.h>
/* ---- Private Constants and Types --------------------------------------- */
/* ---- Private Variables ------------------------------------------------- */
@@ -50,17 +50,18 @@
chipcHw_softReset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
}
/* Bypass the PLL clocks before reboot */
- pChipcHw->UARTClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;
- pChipcHw->SPIClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;
+ writel(readl(&pChipcHw->UARTClock) | chipcHw_REG_PLL_CLOCK_BYPASS_SELECT,
+ &pChipcHw->UARTClock);
+ writel(readl(&pChipcHw->SPIClock) | chipcHw_REG_PLL_CLOCK_BYPASS_SELECT,
+ &pChipcHw->SPIClock);
/* Copy the chipcHw_warmReset_run_from_aram function into ARAM */
do {
- ((uint32_t *) MM_IO_BASE_ARAM)[i] =
- ((uint32_t *) &chipcHw_reset_run_from_aram)[i];
+ writel(((uint32_t *) &chipcHw_reset_run_from_aram)[i], ((uint32_t __iomem *) MM_IO_BASE_ARAM) + i);
i++;
- } while (((uint32_t *) MM_IO_BASE_ARAM)[i - 1] != 0xe1a0f00f); /* 0xe1a0f00f == asm ("mov r15, r15"); */
+ } while (readl(((uint32_t __iomem*) MM_IO_BASE_ARAM) + i - 1) != 0xe1a0f00f); /* 0xe1a0f00f == asm ("mov r15, r15"); */
- CSP_CACHE_FLUSH_ALL;
+ flush_cache_all();
/* run the function from ARAM */
runFunc();
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
index 6b9be2e..547f746 100644
--- a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
+++ b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
@@ -25,11 +25,11 @@
/****************************************************************************/
/* ---- Include Files ---------------------------------------------------- */
-#include <csp/stdint.h>
-#include <csp/string.h>
-#include <stddef.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/stddef.h>
-#include <csp/dmacHw.h>
+#include <mach/csp/dmacHw.h>
#include <mach/csp/dmacHw_reg.h>
#include <mach/csp/dmacHw_priv.h>
#include <mach/csp/chipcHw_inline.h>
@@ -55,33 +55,32 @@
) {
uint32_t val = 0;
dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
- dmacHw_MISC_t *pMiscReg =
- (dmacHw_MISC_t *) dmacHw_REG_MISC_BASE(pCblk->module);
+ dmacHw_MISC_t __iomem *pMiscReg = (void __iomem *)dmacHw_REG_MISC_BASE(pCblk->module);
switch (pCblk->channel) {
case 0:
- val = (pMiscReg->CompParm2.lo & 0x70000000) >> 28;
+ val = (readl(&pMiscReg->CompParm2.lo) & 0x70000000) >> 28;
break;
case 1:
- val = (pMiscReg->CompParm3.hi & 0x70000000) >> 28;
+ val = (readl(&pMiscReg->CompParm3.hi) & 0x70000000) >> 28;
break;
case 2:
- val = (pMiscReg->CompParm3.lo & 0x70000000) >> 28;
+ val = (readl(&pMiscReg->CompParm3.lo) & 0x70000000) >> 28;
break;
case 3:
- val = (pMiscReg->CompParm4.hi & 0x70000000) >> 28;
+ val = (readl(&pMiscReg->CompParm4.hi) & 0x70000000) >> 28;
break;
case 4:
- val = (pMiscReg->CompParm4.lo & 0x70000000) >> 28;
+ val = (readl(&pMiscReg->CompParm4.lo) & 0x70000000) >> 28;
break;
case 5:
- val = (pMiscReg->CompParm5.hi & 0x70000000) >> 28;
+ val = (readl(&pMiscReg->CompParm5.hi) & 0x70000000) >> 28;
break;
case 6:
- val = (pMiscReg->CompParm5.lo & 0x70000000) >> 28;
+ val = (readl(&pMiscReg->CompParm5.lo) & 0x70000000) >> 28;
break;
case 7:
- val = (pMiscReg->CompParm6.hi & 0x70000000) >> 28;
+ val = (readl(&pMiscReg->CompParm6.hi) & 0x70000000) >> 28;
break;
}
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
index a1f3283..fe43869 100644
--- a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
+++ b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
@@ -26,10 +26,10 @@
/* ---- Include Files ---------------------------------------------------- */
-#include <csp/stdint.h>
-#include <stddef.h>
+#include <linux/types.h>
+#include <linux/stddef.h>
-#include <csp/dmacHw.h>
+#include <mach/csp/dmacHw.h>
#include <mach/csp/dmacHw_reg.h>
#include <mach/csp/dmacHw_priv.h>
diff --git a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c b/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
index 16225e4..dc4137f 100644
--- a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
+++ b/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
@@ -26,10 +26,10 @@
/* ---- Include Files ---------------------------------------------------- */
-#include <csp/errno.h>
-#include <csp/stdint.h>
+#include <linux/errno.h>
+#include <linux/types.h>
-#include <csp/tmrHw.h>
+#include <mach/csp/tmrHw.h>
#include <mach/csp/tmrHw_reg.h>
#define tmrHw_ASSERT(a) if (!(a)) *(char *)0 = 0
diff --git a/arch/arm/mach-bcmring/include/cfg_global.h b/arch/arm/mach-bcmring/include/cfg_global.h
deleted file mode 100644
index f01da87..0000000
--- a/arch/arm/mach-bcmring/include/cfg_global.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _CFG_GLOBAL_H_
-#define _CFG_GLOBAL_H_
-
-#include <cfg_global_defines.h>
-
-#define CFG_GLOBAL_CHIP BCM11107
-#define CFG_GLOBAL_CHIP_FAMILY CFG_GLOBAL_CHIP_FAMILY_BCMRING
-#define CFG_GLOBAL_CHIP_REV 0xB0
-#define CFG_GLOBAL_RAM_SIZE 0x10000000
-#define CFG_GLOBAL_RAM_BASE 0x00000000
-#define CFG_GLOBAL_RAM_RESERVED_SIZE 0x000000
-
-#endif /* _CFG_GLOBAL_H_ */
diff --git a/arch/arm/mach-bcmring/include/csp/cache.h b/arch/arm/mach-bcmring/include/csp/cache.h
deleted file mode 100644
index caa20e5..0000000
--- a/arch/arm/mach-bcmring/include/csp/cache.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CSP_CACHE_H
-#define CSP_CACHE_H
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#include <csp/stdint.h>
-
-/* ---- Public Constants and Types --------------------------------------- */
-
-#if defined(__KERNEL__) && !defined(STANDALONE)
-#include <asm/cacheflush.h>
-
-#define CSP_CACHE_FLUSH_ALL flush_cache_all()
-
-#else
-
-#define CSP_CACHE_FLUSH_ALL
-
-#endif
-
-#endif /* CSP_CACHE_H */
diff --git a/arch/arm/mach-bcmring/include/csp/delay.h b/arch/arm/mach-bcmring/include/csp/delay.h
deleted file mode 100644
index 8b3d803..0000000
--- a/arch/arm/mach-bcmring/include/csp/delay.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-
-#ifndef CSP_DELAY_H
-#define CSP_DELAY_H
-
-/* ---- Include Files ---------------------------------------------------- */
-
-/* Some CSP routines require use of the following delay routines. Use the OS */
-/* version if available, otherwise use a CSP specific definition. */
-/* void udelay(unsigned long usecs); */
-/* void mdelay(unsigned long msecs); */
-
-#if defined(__KERNEL__) && !defined(STANDALONE)
- #include <linux/delay.h>
-#else
- #include <mach/csp/delay.h>
-#endif
-
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-#endif /* CSP_DELAY_H */
diff --git a/arch/arm/mach-bcmring/include/csp/errno.h b/arch/arm/mach-bcmring/include/csp/errno.h
deleted file mode 100644
index 51357dd..0000000
--- a/arch/arm/mach-bcmring/include/csp/errno.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CSP_ERRNO_H
-#define CSP_ERRNO_H
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#if defined(__KERNEL__)
-#include <linux/errno.h>
-#elif defined(CSP_SIMULATION)
-#include <asm-generic/errno.h>
-#else
-#include <errno.h>
-#endif
-
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-#endif /* CSP_ERRNO_H */
diff --git a/arch/arm/mach-bcmring/include/csp/intcHw.h b/arch/arm/mach-bcmring/include/csp/intcHw.h
deleted file mode 100644
index 1c639c8..0000000
--- a/arch/arm/mach-bcmring/include/csp/intcHw.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-
-/****************************************************************************/
-/**
-* @file intcHw.h
-*
-* @brief generic interrupt controller API
-*
-* @note
-* None
-*/
-/****************************************************************************/
-
-#ifndef _INTCHW_H
-#define _INTCHW_H
-
-/* ---- Include Files ---------------------------------------------------- */
-#include <mach/csp/intcHw_reg.h>
-
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-static inline void intcHw_irq_disable(void *basep, uint32_t mask);
-static inline void intcHw_irq_enable(void *basep, uint32_t mask);
-
-#endif /* _INTCHW_H */
-
diff --git a/arch/arm/mach-bcmring/include/csp/module.h b/arch/arm/mach-bcmring/include/csp/module.h
deleted file mode 100644
index c30d2a5..0000000
--- a/arch/arm/mach-bcmring/include/csp/module.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-
-#ifndef CSP_MODULE_H
-#define CSP_MODULE_H
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#ifdef __KERNEL__
- #include <linux/module.h>
-#else
- #define EXPORT_SYMBOL(symbol)
-#endif
-
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-
-#endif /* CSP_MODULE_H */
diff --git a/arch/arm/mach-bcmring/include/csp/secHw.h b/arch/arm/mach-bcmring/include/csp/secHw.h
deleted file mode 100644
index b9d7e07..0000000
--- a/arch/arm/mach-bcmring/include/csp/secHw.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*****************************************************************************
-* Copyright 2004 - 2008 Broadcom Corporation. All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-/****************************************************************************/
-/**
-* @file secHw.h
-*
-* @brief Definitions for accessing low level security features
-*
-*/
-/****************************************************************************/
-#ifndef SECHW_H
-#define SECHW_H
-
-typedef void (*secHw_FUNC_t) (void);
-
-typedef enum {
- secHw_MODE_SECURE = 0x0, /* Switches processor into secure mode */
- secHw_MODE_NONSECURE = 0x1 /* Switches processor into non-secure mode */
-} secHw_MODE;
-
-/****************************************************************************/
-/**
-* @brief Requesting to execute the function in secure mode
-*
-* This function requests the given function to run in secure mode
-*
-*/
-/****************************************************************************/
-void secHw_RunSecure(secHw_FUNC_t /* Function to run in secure mode */
- );
-
-/****************************************************************************/
-/**
-* @brief Sets the mode
-*
-* his function sets the processor mode (secure/non-secure)
-*
-*/
-/****************************************************************************/
-void secHw_SetMode(secHw_MODE /* Processor mode */
- );
-
-/****************************************************************************/
-/**
-* @brief Get the current mode
-*
-* This function retieves the processor mode (secure/non-secure)
-*
-*/
-/****************************************************************************/
-void secHw_GetMode(secHw_MODE *);
-
-#endif /* SECHW_H */
diff --git a/arch/arm/mach-bcmring/include/csp/stdint.h b/arch/arm/mach-bcmring/include/csp/stdint.h
deleted file mode 100644
index 3a8718b..0000000
--- a/arch/arm/mach-bcmring/include/csp/stdint.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-#ifndef CSP_STDINT_H
-#define CSP_STDINT_H
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#ifdef __KERNEL__
-#include <linux/types.h>
-#else
-#include <stdint.h>
-#endif
-
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-#endif /* CSP_STDINT_H */
diff --git a/arch/arm/mach-bcmring/include/csp/string.h b/arch/arm/mach-bcmring/include/csp/string.h
deleted file mode 100644
index ad9e400..0000000
--- a/arch/arm/mach-bcmring/include/csp/string.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*****************************************************************************
-* Copyright 2003 - 2008 Broadcom Corporation. All rights reserved.
-*
-* Unless you and Broadcom execute a separate written software license
-* agreement governing use of this software, this software is licensed to you
-* under the terms of the GNU General Public License version 2, available at
-* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
-*
-* Notwithstanding the above, under no circumstances may you combine this
-* software in any way with any other Broadcom software provided under a
-* license other than the GPL, without Broadcom's express prior written
-* consent.
-*****************************************************************************/
-
-
-
-#ifndef CSP_STRING_H
-#define CSP_STRING_H
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#ifdef __KERNEL__
- #include <linux/string.h>
-#else
- #include <string.h>
-#endif
-
-/* ---- Public Constants and Types --------------------------------------- */
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-
-#endif /* CSP_STRING_H */
-
diff --git a/arch/arm/mach-bcmring/include/cfg_global_defines.h b/arch/arm/mach-bcmring/include/mach/cfg_global.h
similarity index 74%
rename from arch/arm/mach-bcmring/include/cfg_global_defines.h
rename to arch/arm/mach-bcmring/include/mach/cfg_global.h
index b5beb0b3..449133e 100644
--- a/arch/arm/mach-bcmring/include/cfg_global_defines.h
+++ b/arch/arm/mach-bcmring/include/mach/cfg_global.h
@@ -38,3 +38,14 @@
#define IMAGE_HEADER_SIZE_CHECKSUM 4
#endif
+#ifndef _CFG_GLOBAL_H_
+#define _CFG_GLOBAL_H_
+
+#define CFG_GLOBAL_CHIP BCM11107
+#define CFG_GLOBAL_CHIP_FAMILY CFG_GLOBAL_CHIP_FAMILY_BCMRING
+#define CFG_GLOBAL_CHIP_REV 0xB0
+#define CFG_GLOBAL_RAM_SIZE 0x10000000
+#define CFG_GLOBAL_RAM_BASE 0x00000000
+#define CFG_GLOBAL_RAM_RESERVED_SIZE 0x000000
+
+#endif /* _CFG_GLOBAL_H_ */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h b/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
index 933ce68..0a89e0c 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
@@ -17,7 +17,7 @@
/* ---- Include Files ---------------------------------------------------- */
#include <mach/csp/cap.h>
-#include <cfg_global.h>
+#include <mach/cfg_global.h>
/* ---- Public Constants and Types --------------------------------------- */
#define CAP_CONFIG0_VPM_DIS 0x00000001
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
index 1619733..39f09cb 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
@@ -17,9 +17,9 @@
/* ---- Include Files ----------------------------------------------------- */
-#include <csp/stdint.h>
-#include <csp/errno.h>
-#include <csp/reg.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <mach/csp/reg.h>
#include <mach/csp/chipcHw_reg.h>
/* ---- Public Constants and Types ---------------------------------------- */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
index 03238c2..a66f3f7 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
@@ -17,8 +17,8 @@
/* ---- Include Files ----------------------------------------------------- */
-#include <csp/errno.h>
-#include <csp/reg.h>
+#include <linux/errno.h>
+#include <mach/csp/reg.h>
#include <mach/csp/chipcHw_reg.h>
#include <mach/csp/chipcHw_def.h>
@@ -47,7 +47,7 @@
/****************************************************************************/
static inline uint32_t chipcHw_getChipId(void)
{
- return pChipcHw->ChipId;
+ return readl(&pChipcHw->ChipId);
}
/****************************************************************************/
@@ -59,15 +59,16 @@
/****************************************************************************/
static inline void chipcHw_enableSpreadSpectrum(void)
{
- if ((pChipcHw->
- PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) !=
+ if ((readl(&pChipcHw->
+ PLLPreDivider) & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) !=
chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
- ddrcReg_PHY_ADDR_CTL_REGP->ssCfg =
- (0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) |
+ writel((0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) |
(ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK <<
- ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT);
- ddrcReg_PHY_ADDR_CTL_REGP->ssCtl |=
- ddrcReg_PHY_ADDR_SS_CTRL_ENABLE;
+ ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT),
+ &ddrcReg_PHY_ADDR_CTL_REGP->ssCfg);
+ writel(readl(&ddrcReg_PHY_ADDR_CTL_REGP->ssCtl) |
+ ddrcReg_PHY_ADDR_SS_CTRL_ENABLE,
+ &ddrcReg_PHY_ADDR_CTL_REGP->ssCtl);
}
}
@@ -93,8 +94,8 @@
/****************************************************************************/
static inline uint32_t chipcHw_getChipProductId(void)
{
- return (pChipcHw->
- ChipId & chipcHw_REG_CHIPID_BASE_MASK) >>
+ return (readl(&pChipcHw->
+ ChipId) & chipcHw_REG_CHIPID_BASE_MASK) >>
chipcHw_REG_CHIPID_BASE_SHIFT;
}
@@ -109,7 +110,7 @@
/****************************************************************************/
static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void)
{
- return pChipcHw->ChipId & chipcHw_REG_CHIPID_REV_MASK;
+ return readl(&pChipcHw->ChipId) & chipcHw_REG_CHIPID_REV_MASK;
}
/****************************************************************************/
@@ -156,7 +157,7 @@
/****************************************************************************/
static inline uint32_t chipcHw_getBusInterfaceClockStatus(void)
{
- return pChipcHw->BusIntfClock;
+ return readl(&pChipcHw->BusIntfClock);
}
/****************************************************************************/
@@ -215,8 +216,9 @@
/* Deassert module soft reset */
REG_LOCAL_IRQ_SAVE;
- pChipcHw->SoftReset1 ^= ctrl1;
- pChipcHw->SoftReset2 ^= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK));
+ writel(readl(&pChipcHw->SoftReset1) ^ ctrl1, &pChipcHw->SoftReset1);
+ writel(readl(&pChipcHw->SoftReset2) ^ (ctrl2 &
+ (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)), &pChipcHw->SoftReset2);
REG_LOCAL_IRQ_RESTORE;
}
@@ -227,9 +229,10 @@
uint32_t unhold = 0;
REG_LOCAL_IRQ_SAVE;
- pChipcHw->SoftReset1 |= ctrl1;
+ writel(readl(&pChipcHw->SoftReset1) | ctrl1, &pChipcHw->SoftReset1);
/* Mask out unhold request bits */
- pChipcHw->SoftReset2 |= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK));
+ writel(readl(&pChipcHw->SoftReset2) | (ctrl2 &
+ (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK)), &pChipcHw->SoftReset2);
/* Process unhold requests */
if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD) {
@@ -246,7 +249,7 @@
if (unhold) {
/* Make sure unhold request is effective */
- pChipcHw->SoftReset1 &= ~unhold;
+ writel(readl(&pChipcHw->SoftReset1) & ~unhold, &pChipcHw->SoftReset1);
}
REG_LOCAL_IRQ_RESTORE;
}
@@ -307,7 +310,7 @@
/****************************************************************************/
static inline uint32_t chipcHw_getStickyBits(void)
{
- return pChipcHw->Sticky;
+ return readl(&pChipcHw->Sticky);
}
/****************************************************************************/
@@ -328,7 +331,7 @@
bits |= chipcHw_REG_STICKY_POR_BROM;
} else {
uint32_t sticky;
- sticky = pChipcHw->Sticky;
+ sticky = readl(pChipcHw->Sticky);
if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
&& (sticky & chipcHw_REG_STICKY_BOOT_DONE) == 0) {
@@ -355,7 +358,7 @@
bits |= chipcHw_REG_STICKY_GENERAL_5;
}
}
- pChipcHw->Sticky = bits;
+ writel(bits, pChipcHw->Sticky);
REG_LOCAL_IRQ_RESTORE;
}
@@ -377,7 +380,7 @@
(chipcHw_REG_STICKY_BOOT_DONE | chipcHw_REG_STICKY_GENERAL_1 |
chipcHw_REG_STICKY_GENERAL_2 | chipcHw_REG_STICKY_GENERAL_3 |
chipcHw_REG_STICKY_GENERAL_4 | chipcHw_REG_STICKY_GENERAL_5)) {
- uint32_t sticky = pChipcHw->Sticky;
+ uint32_t sticky = readl(&pChipcHw->Sticky);
if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
&& (sticky & chipcHw_REG_STICKY_BOOT_DONE)) {
@@ -410,7 +413,7 @@
mask &= ~chipcHw_REG_STICKY_GENERAL_5;
}
}
- pChipcHw->Sticky = bits | mask;
+ writel(bits | mask, &pChipcHw->Sticky);
REG_LOCAL_IRQ_RESTORE;
}
@@ -426,7 +429,7 @@
/****************************************************************************/
static inline uint32_t chipcHw_getSoftStraps(void)
{
- return pChipcHw->SoftStraps;
+ return readl(&pChipcHw->SoftStraps);
}
/****************************************************************************/
@@ -456,7 +459,7 @@
/****************************************************************************/
static inline uint32_t chipcHw_getPinStraps(void)
{
- return pChipcHw->PinStraps;
+ return readl(&pChipcHw->PinStraps);
}
/****************************************************************************/
@@ -671,9 +674,9 @@
/****************************************************************************/
static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin)
{
- return (*((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) &
+ return (readl(chipcHw_REG_GPIO_MUX(pin))) &
(chipcHw_REG_GPIO_MUX_MASK <<
- chipcHw_REG_GPIO_MUX_POSITION(pin))) >>
+ chipcHw_REG_GPIO_MUX_POSITION(pin)) >>
chipcHw_REG_GPIO_MUX_POSITION(pin);
}
@@ -841,8 +844,8 @@
static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
chipcHw_OPTYPE_e type, int mode)
{
- volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
- volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
+ uint32_t __iomem *pPLLReg = NULL;
+ uint32_t __iomem *pClockCtrl = NULL;
switch (clock) {
case chipcHw_CLOCK_DDR:
@@ -1071,7 +1074,7 @@
/****************************************************************************/
static inline int chipcHw_isSoftwareStrapsEnable(void)
{
- return pChipcHw->SoftStraps & 0x00000001;
+ return readl(&pChipcHw->SoftStraps) & 0x00000001;
}
/****************************************************************************/
@@ -1138,7 +1141,7 @@
/****************************************************************************/
static inline int chipcHw_isPllTestEnable(void)
{
- return pChipcHw->PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
+ return readl(&pChipcHw->PLLConfig) & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
}
/****************************************************************************/
@@ -1147,7 +1150,7 @@
/****************************************************************************/
static inline int chipcHw_isPll2TestEnable(void)
{
- return pChipcHw->PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
+ return readl(&pChipcHw->PLLConfig2) & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
}
/****************************************************************************/
@@ -1183,8 +1186,8 @@
/****************************************************************************/
static inline uint8_t chipcHw_getPllTestSelected(void)
{
- return (uint8_t) ((pChipcHw->
- PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
+ return (uint8_t) ((readl(&pChipcHw->
+ PLLConfig) & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
>> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
}
@@ -1194,8 +1197,8 @@
/****************************************************************************/
static inline uint8_t chipcHw_getPll2TestSelected(void)
{
- return (uint8_t) ((pChipcHw->
- PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
+ return (uint8_t) ((readl(&pChipcHw->
+ PLLConfig2) & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
>> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
}
@@ -1208,7 +1211,8 @@
static inline void chipcHw_pll1Disable(void)
{
REG_LOCAL_IRQ_SAVE;
- pChipcHw->PLLConfig |= chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+ writel(readl(&pChipcHw->PLLConfig) | chipcHw_REG_PLL_CONFIG_POWER_DOWN,
+ &pChipcHw->PLLConfig);
REG_LOCAL_IRQ_RESTORE;
}
@@ -1221,7 +1225,8 @@
static inline void chipcHw_pll2Disable(void)
{
REG_LOCAL_IRQ_SAVE;
- pChipcHw->PLLConfig2 |= chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+ writel(readl(&pChipcHw->PLLConfig2) | chipcHw_REG_PLL_CONFIG_POWER_DOWN,
+ &pChipcHw->PLLConfig2);
REG_LOCAL_IRQ_RESTORE;
}
@@ -1233,7 +1238,8 @@
static inline void chipcHw_ddrPhaseAlignInterruptEnable(void)
{
REG_LOCAL_IRQ_SAVE;
- pChipcHw->Spare1 |= chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE;
+ writel(readl(&pChipcHw->Spare1) | chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE,
+ &pChipcHw->Spare1);
REG_LOCAL_IRQ_RESTORE;
}
@@ -1245,7 +1251,8 @@
static inline void chipcHw_ddrPhaseAlignInterruptDisable(void)
{
REG_LOCAL_IRQ_SAVE;
- pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE;
+ writel(readl(&pChipcHw->Spare1) & ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE,
+ &pChipcHw->Spare1);
REG_LOCAL_IRQ_RESTORE;
}
@@ -1333,7 +1340,8 @@
static inline void chipcHw_vpmSwPhaseAlignEnable(void)
{
REG_LOCAL_IRQ_SAVE;
- pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE;
+ writel(readl(&pChipcHw->VPMPhaseCtrl1) | chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE,
+ &pChipcHw->VPMPhaseCtrl1);
REG_LOCAL_IRQ_RESTORE;
}
@@ -1372,7 +1380,8 @@
static inline void chipcHw_vpmHwPhaseAlignDisable(void)
{
REG_LOCAL_IRQ_SAVE;
- pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE;
+ writel(readl(&pChipcHw->VPMPhaseCtrl1) & ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE,
+ &pChipcHw->VPMPhaseCtrl1);
REG_LOCAL_IRQ_RESTORE;
}
@@ -1474,8 +1483,8 @@
/****************************************************************************/
static inline uint32_t chipcHw_isDdrHwPhaseAligned(void)
{
- return (pChipcHw->
- PhaseAlignStatus & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0;
+ return (readl(&pChipcHw->
+ PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0;
}
/****************************************************************************/
@@ -1488,8 +1497,8 @@
/****************************************************************************/
static inline uint32_t chipcHw_isVpmHwPhaseAligned(void)
{
- return (pChipcHw->
- PhaseAlignStatus & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0;
+ return (readl(&pChipcHw->
+ PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0;
}
/****************************************************************************/
@@ -1500,8 +1509,8 @@
/****************************************************************************/
static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void)
{
- return (pChipcHw->
- PhaseAlignStatus & chipcHw_REG_DDR_PHASE_STATUS_MASK) >>
+ return (readl(&pChipcHw->
+ PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_STATUS_MASK) >>
chipcHw_REG_DDR_PHASE_STATUS_SHIFT;
}
@@ -1513,8 +1522,8 @@
/****************************************************************************/
static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void)
{
- return (pChipcHw->
- PhaseAlignStatus & chipcHw_REG_VPM_PHASE_STATUS_MASK) >>
+ return (readl(&pChipcHw->
+ PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_STATUS_MASK) >>
chipcHw_REG_VPM_PHASE_STATUS_SHIFT;
}
@@ -1526,8 +1535,8 @@
/****************************************************************************/
static inline uint32_t chipcHw_getDdrPhaseControl(void)
{
- return (pChipcHw->
- PhaseAlignStatus & chipcHw_REG_DDR_PHASE_CTRL_MASK) >>
+ return (readl(&pChipcHw->
+ PhaseAlignStatus) & chipcHw_REG_DDR_PHASE_CTRL_MASK) >>
chipcHw_REG_DDR_PHASE_CTRL_SHIFT;
}
@@ -1539,8 +1548,8 @@
/****************************************************************************/
static inline uint32_t chipcHw_getVpmPhaseControl(void)
{
- return (pChipcHw->
- PhaseAlignStatus & chipcHw_REG_VPM_PHASE_CTRL_MASK) >>
+ return (readl(&pChipcHw->
+ PhaseAlignStatus) & chipcHw_REG_VPM_PHASE_CTRL_MASK) >>
chipcHw_REG_VPM_PHASE_CTRL_SHIFT;
}
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
index b162448..26f5d0e 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
@@ -24,7 +24,7 @@
#define CHIPCHW_REG_H
#include <mach/csp/mm_io.h>
-#include <csp/reg.h>
+#include <mach/csp/reg.h>
#include <mach/csp/ddrcReg.h>
#define chipcHw_BASE_ADDRESS MM_IO_BASE_CHIPC
@@ -131,8 +131,8 @@
uint32_t MiscInput_0_15; /* Input type for MISC 0 - 16 */
} chipcHw_REG_t;
-#define pChipcHw ((volatile chipcHw_REG_t *) chipcHw_BASE_ADDRESS)
-#define pChipcPhysical ((volatile chipcHw_REG_t *) MM_ADDR_IO_CHIPC)
+#define pChipcHw ((chipcHw_REG_t __iomem *) chipcHw_BASE_ADDRESS)
+#define pChipcPhysical (MM_ADDR_IO_CHIPC)
#define chipcHw_REG_CHIPID_BASE_MASK 0xFFFFF000
#define chipcHw_REG_CHIPID_BASE_SHIFT 12
diff --git a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h b/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
index f1b68e2..39da2c1 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
@@ -30,8 +30,8 @@
/* ---- Include Files ---------------------------------------------------- */
-#include <csp/reg.h>
-#include <csp/stdint.h>
+#include <mach/csp/reg.h>
+#include <linux/types.h>
#include <mach/csp/mm_io.h>
@@ -416,7 +416,7 @@
} ddrcReg_PHY_ADDR_CTL_REG_t;
#define ddrcReg_PHY_ADDR_CTL_REG_OFFSET 0x0400
-#define ddrcReg_PHY_ADDR_CTL_REGP ((volatile ddrcReg_PHY_ADDR_CTL_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET))
+#define ddrcReg_PHY_ADDR_CTL_REGP ((volatile ddrcReg_PHY_ADDR_CTL_REG_t __iomem*) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET))
/* @todo These SS definitions are duplicates of ones below */
diff --git a/arch/arm/mach-bcmring/include/csp/dmacHw.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw.h
similarity index 99%
rename from arch/arm/mach-bcmring/include/csp/dmacHw.h
rename to arch/arm/mach-bcmring/include/mach/csp/dmacHw.h
index e6a1dc4..9dc90f46 100644
--- a/arch/arm/mach-bcmring/include/csp/dmacHw.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/dmacHw.h
@@ -23,9 +23,9 @@
#ifndef _DMACHW_H
#define _DMACHW_H
-#include <stddef.h>
+#include <linux/stddef.h>
-#include <csp/stdint.h>
+#include <linux/types.h>
#include <mach/csp/dmacHw_reg.h>
/* Define DMA Channel ID using DMA controller number (m) and channel number (c).
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
index d67e2f8..9d9455e 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
@@ -24,7 +24,7 @@
#ifndef _DMACHW_PRIV_H
#define _DMACHW_PRIV_H
-#include <csp/stdint.h>
+#include <linux/types.h>
/* Data type for DMA Link List Item */
typedef struct {
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
index f1ecf96..7cd0aaf 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
@@ -24,7 +24,7 @@
#ifndef _DMACHW_REG_H
#define _DMACHW_REG_H
-#include <csp/stdint.h>
+#include <linux/types.h>
#include <mach/csp/mm_io.h>
/* Data type for 64 bit little endian register */
@@ -121,75 +121,75 @@
} dmacHw_MISC_t;
/* Base registers */
-#define dmacHw_0_MODULE_BASE_ADDR (char *) MM_IO_BASE_DMA0 /* DMAC 0 module's base address */
-#define dmacHw_1_MODULE_BASE_ADDR (char *) MM_IO_BASE_DMA1 /* DMAC 1 module's base address */
+#define dmacHw_0_MODULE_BASE_ADDR (char __iomem*) MM_IO_BASE_DMA0 /* DMAC 0 module's base address */
+#define dmacHw_1_MODULE_BASE_ADDR (char __iomem*) MM_IO_BASE_DMA1 /* DMAC 1 module's base address */
extern uint32_t dmaChannelCount_0;
extern uint32_t dmaChannelCount_1;
/* Define channel specific registers */
-#define dmacHw_CHAN_BASE(module, chan) ((dmacHw_CH_REG_t *) ((char *)((module) ? dmacHw_1_MODULE_BASE_ADDR : dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t))))
+#define dmacHw_CHAN_BASE(module, chan) ((dmacHw_CH_REG_t __iomem*) ((char __iomem*)((module) ? dmacHw_1_MODULE_BASE_ADDR : dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t))))
/* Raw interrupt status registers */
-#define dmacHw_REG_INT_RAW_BASE(module) ((char *)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : dmaChannelCount_0)))
-#define dmacHw_REG_INT_RAW_TRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo)
-#define dmacHw_REG_INT_RAW_BLOCK(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo)
-#define dmacHw_REG_INT_RAW_STRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo)
-#define dmacHw_REG_INT_RAW_DTRAN(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo)
-#define dmacHw_REG_INT_RAW_ERROR(module) (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo)
+#define dmacHw_REG_INT_RAW_BASE(module) ((char __iomem *)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : dmaChannelCount_0)))
+#define dmacHw_REG_INT_RAW_TRAN(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo)
+#define dmacHw_REG_INT_RAW_BLOCK(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo)
+#define dmacHw_REG_INT_RAW_STRAN(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo)
+#define dmacHw_REG_INT_RAW_DTRAN(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo)
+#define dmacHw_REG_INT_RAW_ERROR(module) (((dmacHw_INT_RAW_t __iomem *) dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo)
/* Interrupt status registers */
-#define dmacHw_REG_INT_STAT_BASE(module) ((char *)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t)))
-#define dmacHw_REG_INT_STAT_TRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo)
-#define dmacHw_REG_INT_STAT_BLOCK(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo)
-#define dmacHw_REG_INT_STAT_STRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo)
-#define dmacHw_REG_INT_STAT_DTRAN(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo)
-#define dmacHw_REG_INT_STAT_ERROR(module) (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo)
+#define dmacHw_REG_INT_STAT_BASE(module) ((char __iomem*)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t)))
+#define dmacHw_REG_INT_STAT_TRAN(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo)
+#define dmacHw_REG_INT_STAT_BLOCK(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo)
+#define dmacHw_REG_INT_STAT_STRAN(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo)
+#define dmacHw_REG_INT_STAT_DTRAN(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo)
+#define dmacHw_REG_INT_STAT_ERROR(module) (((dmacHw_INT_STATUS_t __iomem *) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo)
/* Interrupt status registers */
-#define dmacHw_REG_INT_MASK_BASE(module) ((char *)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t)))
-#define dmacHw_REG_INT_MASK_TRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo)
-#define dmacHw_REG_INT_MASK_BLOCK(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo)
-#define dmacHw_REG_INT_MASK_STRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo)
-#define dmacHw_REG_INT_MASK_DTRAN(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo)
-#define dmacHw_REG_INT_MASK_ERROR(module) (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo)
+#define dmacHw_REG_INT_MASK_BASE(module) ((char __iomem*)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t)))
+#define dmacHw_REG_INT_MASK_TRAN(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo)
+#define dmacHw_REG_INT_MASK_BLOCK(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo)
+#define dmacHw_REG_INT_MASK_STRAN(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo)
+#define dmacHw_REG_INT_MASK_DTRAN(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo)
+#define dmacHw_REG_INT_MASK_ERROR(module) (((dmacHw_INT_MASK_t __iomem *) dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo)
/* Interrupt clear registers */
-#define dmacHw_REG_INT_CLEAR_BASE(module) ((char *)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t)))
-#define dmacHw_REG_INT_CLEAR_TRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo)
-#define dmacHw_REG_INT_CLEAR_BLOCK(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo)
-#define dmacHw_REG_INT_CLEAR_STRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo)
-#define dmacHw_REG_INT_CLEAR_DTRAN(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo)
-#define dmacHw_REG_INT_CLEAR_ERROR(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo)
-#define dmacHw_REG_INT_STATUS(module) (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo)
+#define dmacHw_REG_INT_CLEAR_BASE(module) ((char __iomem*)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t)))
+#define dmacHw_REG_INT_CLEAR_TRAN(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo)
+#define dmacHw_REG_INT_CLEAR_BLOCK(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo)
+#define dmacHw_REG_INT_CLEAR_STRAN(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo)
+#define dmacHw_REG_INT_CLEAR_DTRAN(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo)
+#define dmacHw_REG_INT_CLEAR_ERROR(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo)
+#define dmacHw_REG_INT_STATUS(module) (((dmacHw_INT_CLEAR_t __iomem *) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo)
/* Software handshaking registers */
-#define dmacHw_REG_SW_HS_BASE(module) ((char *)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t)))
-#define dmacHw_REG_SW_HS_SRC_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo)
-#define dmacHw_REG_SW_HS_DST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo)
-#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo)
-#define dmacHw_REG_SW_HS_DST_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo)
-#define dmacHw_REG_SW_HS_SRC_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo)
-#define dmacHw_REG_SW_HS_DST_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo)
+#define dmacHw_REG_SW_HS_BASE(module) ((char __iomem*)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t)))
+#define dmacHw_REG_SW_HS_SRC_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo)
+#define dmacHw_REG_SW_HS_DST_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo)
+#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo)
+#define dmacHw_REG_SW_HS_DST_SGL_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo)
+#define dmacHw_REG_SW_HS_SRC_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo)
+#define dmacHw_REG_SW_HS_DST_LST_REQ(module) (((dmacHw_SW_HANDSHAKE_t __iomem *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo)
/* Miscellaneous registers */
-#define dmacHw_REG_MISC_BASE(module) ((char *)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t)))
-#define dmacHw_REG_MISC_CFG(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo)
-#define dmacHw_REG_MISC_CH_ENABLE(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo)
-#define dmacHw_REG_MISC_ID(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo)
-#define dmacHw_REG_MISC_TEST(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo)
-#define dmacHw_REG_MISC_COMP_PARAM1_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.lo)
-#define dmacHw_REG_MISC_COMP_PARAM1_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.hi)
-#define dmacHw_REG_MISC_COMP_PARAM2_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.lo)
-#define dmacHw_REG_MISC_COMP_PARAM2_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.hi)
-#define dmacHw_REG_MISC_COMP_PARAM3_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.lo)
-#define dmacHw_REG_MISC_COMP_PARAM3_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.hi)
-#define dmacHw_REG_MISC_COMP_PARAM4_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.lo)
-#define dmacHw_REG_MISC_COMP_PARAM4_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.hi)
-#define dmacHw_REG_MISC_COMP_PARAM5_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.lo)
-#define dmacHw_REG_MISC_COMP_PARAM5_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.hi)
-#define dmacHw_REG_MISC_COMP_PARAM6_LO(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.lo)
-#define dmacHw_REG_MISC_COMP_PARAM6_HI(module) (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.hi)
+#define dmacHw_REG_MISC_BASE(module) ((char __iomem*)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t)))
+#define dmacHw_REG_MISC_CFG(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo)
+#define dmacHw_REG_MISC_CH_ENABLE(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo)
+#define dmacHw_REG_MISC_ID(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo)
+#define dmacHw_REG_MISC_TEST(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo)
+#define dmacHw_REG_MISC_COMP_PARAM1_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm1.lo)
+#define dmacHw_REG_MISC_COMP_PARAM1_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm1.hi)
+#define dmacHw_REG_MISC_COMP_PARAM2_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm2.lo)
+#define dmacHw_REG_MISC_COMP_PARAM2_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm2.hi)
+#define dmacHw_REG_MISC_COMP_PARAM3_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm3.lo)
+#define dmacHw_REG_MISC_COMP_PARAM3_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm3.hi)
+#define dmacHw_REG_MISC_COMP_PARAM4_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm4.lo)
+#define dmacHw_REG_MISC_COMP_PARAM4_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm4.hi)
+#define dmacHw_REG_MISC_COMP_PARAM5_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm5.lo)
+#define dmacHw_REG_MISC_COMP_PARAM5_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm5.hi)
+#define dmacHw_REG_MISC_COMP_PARAM6_LO(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm6.lo)
+#define dmacHw_REG_MISC_COMP_PARAM6_HI(module) (((dmacHw_MISC_t __iomem*) dmacHw_REG_MISC_BASE((module)))->CompParm6.hi)
/* Channel control registers */
#define dmacHw_REG_SAR(module, chan) (dmacHw_CHAN_BASE((module), (chan))->ChannelSar.lo)
diff --git a/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h b/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
index cfa91be..27f59dd 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
@@ -18,7 +18,7 @@
/* ---- Include Files ---------------------------------------------------- */
-#include <cfg_global.h>
+#include <mach/cfg_global.h>
#include <mach/csp/cap_inline.h>
#if defined(__KERNEL__)
diff --git a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
index 0aeb6a6..f59db25 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
@@ -27,8 +27,8 @@
#define _INTCHW_REG_H
/* ---- Include Files ---------------------------------------------------- */
-#include <csp/stdint.h>
-#include <csp/reg.h>
+#include <linux/types.h>
+#include <mach/csp/reg.h>
#include <mach/csp/mm_io.h>
/* ---- Public Constants and Types --------------------------------------- */
@@ -37,9 +37,9 @@
#define INTCHW_NUM_INTC 3
/* Defines for interrupt controllers. This simplifies and cleans up the function calls. */
-#define INTCHW_INTC0 ((void *)MM_IO_BASE_INTC0)
-#define INTCHW_INTC1 ((void *)MM_IO_BASE_INTC1)
-#define INTCHW_SINTC ((void *)MM_IO_BASE_SINTC)
+#define INTCHW_INTC0 (MM_IO_BASE_INTC0)
+#define INTCHW_INTC1 (MM_IO_BASE_INTC1)
+#define INTCHW_SINTC (MM_IO_BASE_SINTC)
/* INTC0 - interrupt controller 0 */
#define INTCHW_INTC0_PIF_BITNUM 31 /* Peripheral interface interrupt */
@@ -232,15 +232,15 @@
/* ---- Public Variable Externs ------------------------------------------ */
/* ---- Public Function Prototypes --------------------------------------- */
/* Clear one or more IRQ interrupts. */
-static inline void intcHw_irq_disable(void *basep, uint32_t mask)
+static inline void intcHw_irq_disable(void __iomem *basep, uint32_t mask)
{
- __REG32(basep + INTCHW_INTENCLEAR) = mask;
+ writel(mask, basep + INTCHW_INTENCLEAR);
}
/* Enables one or more IRQ interrupts. */
-static inline void intcHw_irq_enable(void *basep, uint32_t mask)
+static inline void intcHw_irq_enable(void __iomem *basep, uint32_t mask)
{
- __REG32(basep + INTCHW_INTENABLE) = mask;
+ writel(mask, basep + INTCHW_INTENABLE);
}
#endif /* _INTCHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h b/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
index ad58cf8..d571962 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
@@ -29,7 +29,7 @@
/* ---- Include Files ---------------------------------------------------- */
#if !defined(CSP_SIMULATION)
-#include <cfg_global.h>
+#include <mach/cfg_global.h>
#endif
/* ---- Public Constants and Types --------------------------------------- */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h b/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
index de92ec6..47450c2 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
@@ -30,7 +30,7 @@
#include <mach/csp/mm_addr.h>
#if !defined(CSP_SIMULATION)
-#include <cfg_global.h>
+#include <mach/cfg_global.h>
#endif
/* ---- Public Constants and Types --------------------------------------- */
@@ -49,7 +49,7 @@
#ifdef __ASSEMBLY__
#define MM_IO_PHYS_TO_VIRT(phys) (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF))
#else
-#define MM_IO_PHYS_TO_VIRT(phys) (((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \
+#define MM_IO_PHYS_TO_VIRT(phys) (void __iomem *)(((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \
(0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF)))
#endif
#endif
@@ -60,8 +60,8 @@
#ifdef __ASSEMBLY__
#define MM_IO_VIRT_TO_PHYS(virt) ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF))
#else
-#define MM_IO_VIRT_TO_PHYS(virt) (((virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \
- ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF)))
+#define MM_IO_VIRT_TO_PHYS(virt) (((unsigned long)(virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \
+ ((((unsigned long)(virt) & 0x0F000000) << 4) | ((unsigned long)(virt) & 0xFFFFFF)))
#endif
#endif
diff --git a/arch/arm/mach-bcmring/include/csp/reg.h b/arch/arm/mach-bcmring/include/mach/csp/reg.h
similarity index 81%
rename from arch/arm/mach-bcmring/include/csp/reg.h
rename to arch/arm/mach-bcmring/include/mach/csp/reg.h
index 56654d2..d9cbdca 100644
--- a/arch/arm/mach-bcmring/include/csp/reg.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/reg.h
@@ -25,13 +25,14 @@
/* ---- Include Files ---------------------------------------------------- */
-#include <csp/stdint.h>
+#include <linux/types.h>
+#include <linux/io.h>
/* ---- Public Constants and Types --------------------------------------- */
-#define __REG32(x) (*((volatile uint32_t *)(x)))
-#define __REG16(x) (*((volatile uint16_t *)(x)))
-#define __REG8(x) (*((volatile uint8_t *) (x)))
+#define __REG32(x) (*((volatile uint32_t __iomem *)(x)))
+#define __REG16(x) (*((volatile uint16_t __iomem *)(x)))
+#define __REG8(x) (*((volatile uint8_t __iomem *) (x)))
/* Macros used to define a sequence of reserved registers. The start / end */
/* are byte offsets in the particular register definition, with the "end" */
@@ -84,31 +85,31 @@
#endif
-static inline void reg32_modify_and(volatile uint32_t *reg, uint32_t value)
+static inline void reg32_modify_and(volatile uint32_t __iomem *reg, uint32_t value)
{
REG_LOCAL_IRQ_SAVE;
- *reg &= value;
+ __raw_writel(__raw_readl(reg) & value, reg);
REG_LOCAL_IRQ_RESTORE;
}
-static inline void reg32_modify_or(volatile uint32_t *reg, uint32_t value)
+static inline void reg32_modify_or(volatile uint32_t __iomem *reg, uint32_t value)
{
REG_LOCAL_IRQ_SAVE;
- *reg |= value;
+ __raw_writel(__raw_readl(reg) | value, reg);
REG_LOCAL_IRQ_RESTORE;
}
-static inline void reg32_modify_mask(volatile uint32_t *reg, uint32_t mask,
+static inline void reg32_modify_mask(volatile uint32_t __iomem *reg, uint32_t mask,
uint32_t value)
{
REG_LOCAL_IRQ_SAVE;
- *reg = (*reg & mask) | value;
+ __raw_writel((__raw_readl(reg) & mask) | value, reg);
REG_LOCAL_IRQ_RESTORE;
}
-static inline void reg32_write(volatile uint32_t *reg, uint32_t value)
+static inline void reg32_write(volatile uint32_t __iomem *reg, uint32_t value)
{
- *reg = value;
+ __raw_writel(value, reg);
}
#endif /* CSP_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
index 9cd6a03..55d3cd4 100644
--- a/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
@@ -34,7 +34,7 @@
/****************************************************************************/
static inline void secHw_setSecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */
) {
- secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
+ secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC;
if (mask & 0x0000FFFF) {
regp->reg[secHw_IDX_LS].setSecure = mask & 0x0000FFFF;
@@ -53,13 +53,13 @@
/****************************************************************************/
static inline void secHw_setUnsecure(uint32_t mask /* mask of type secHw_BLK_MASK_XXXXXX */
) {
- secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
+ secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC;
if (mask & 0x0000FFFF) {
- regp->reg[secHw_IDX_LS].setUnsecure = mask & 0x0000FFFF;
+ writel(mask & 0x0000FFFF, ®p->reg[secHw_IDX_LS].setUnsecure);
}
if (mask & 0xFFFF0000) {
- regp->reg[secHw_IDX_MS].setUnsecure = mask >> 16;
+ writel(mask >> 16, ®p->reg[secHw_IDX_MS].setUnsecure);
}
}
@@ -71,7 +71,7 @@
/****************************************************************************/
static inline uint32_t secHw_getStatus(void)
{
- secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
+ secHw_REGS_t __iomem *regp = MM_IO_BASE_TZPC;
return (regp->reg[1].status << 16) + regp->reg[0].status;
}
diff --git a/arch/arm/mach-bcmring/include/csp/tmrHw.h b/arch/arm/mach-bcmring/include/mach/csp/tmrHw.h
similarity index 99%
rename from arch/arm/mach-bcmring/include/csp/tmrHw.h
rename to arch/arm/mach-bcmring/include/mach/csp/tmrHw.h
index 2cbb530..1cc882a 100644
--- a/arch/arm/mach-bcmring/include/csp/tmrHw.h
+++ b/arch/arm/mach-bcmring/include/mach/csp/tmrHw.h
@@ -23,7 +23,7 @@
#ifndef _TMRHW_H
#define _TMRHW_H
-#include <csp/stdint.h>
+#include <linux/types.h>
typedef uint32_t tmrHw_ID_t; /* Timer ID */
typedef uint32_t tmrHw_COUNT_t; /* Timer count */
diff --git a/arch/arm/mach-bcmring/include/mach/dma.h b/arch/arm/mach-bcmring/include/mach/dma.h
index 7254378..13e0138 100644
--- a/arch/arm/mach-bcmring/include/mach/dma.h
+++ b/arch/arm/mach-bcmring/include/mach/dma.h
@@ -27,7 +27,7 @@
#include <linux/kernel.h>
#include <linux/semaphore.h>
-#include <csp/dmacHw.h>
+#include <mach/csp/dmacHw.h>
#include <mach/timer.h>
/* ---- Constants and Types ---------------------------------------------- */
diff --git a/arch/arm/mach-bcmring/include/mach/hardware.h b/arch/arm/mach-bcmring/include/mach/hardware.h
index 6ae20a6..a0c92b4 100644
--- a/arch/arm/mach-bcmring/include/mach/hardware.h
+++ b/arch/arm/mach-bcmring/include/mach/hardware.h
@@ -22,7 +22,7 @@
#define __ASM_ARCH_HARDWARE_H
#include <asm/sizes.h>
-#include <cfg_global.h>
+#include <mach/cfg_global.h>
#include <mach/csp/mm_io.h>
/* Hardware addresses of major areas.
diff --git a/arch/arm/mach-bcmring/include/mach/reg_nand.h b/arch/arm/mach-bcmring/include/mach/reg_nand.h
index 387376f..f8d51a8 100644
--- a/arch/arm/mach-bcmring/include/mach/reg_nand.h
+++ b/arch/arm/mach-bcmring/include/mach/reg_nand.h
@@ -30,7 +30,7 @@
#define __ASM_ARCH_REG_NAND_H
/* ---- Include Files ---------------------------------------------------- */
-#include <csp/reg.h>
+#include <mach/csp/reg.h>
#include <mach/reg_umi.h>
/* ---- Constants and Types ---------------------------------------------- */
diff --git a/arch/arm/mach-bcmring/include/mach/reg_umi.h b/arch/arm/mach-bcmring/include/mach/reg_umi.h
index 0992842..56dd9de 100644
--- a/arch/arm/mach-bcmring/include/mach/reg_umi.h
+++ b/arch/arm/mach-bcmring/include/mach/reg_umi.h
@@ -30,7 +30,7 @@
#define __ASM_ARCH_REG_UMI_H
/* ---- Include Files ---------------------------------------------------- */
-#include <csp/reg.h>
+#include <mach/csp/reg.h>
#include <mach/csp/mm_io.h>
/* ---- Constants and Types ---------------------------------------------- */
@@ -233,5 +233,5 @@
#define REG_UMI_BCH_ERR_LOC_WORD 0x00000018
/* location within a page (512 byte) */
#define REG_UMI_BCH_ERR_LOC_PAGE 0x00001FE0
-#define REG_UMI_BCH_ERR_LOC_ADDR(index) (__REG32(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16))
+#define REG_UMI_BCH_ERR_LOC_ADDR(index) (readl(HW_UMI_BASE + 0x64 + (index / 2)*4) >> ((index % 2) * 16))
#endif
diff --git a/arch/arm/mach-bcmring/mm.c b/arch/arm/mach-bcmring/mm.c
index 1adec78e..33824a8 100644
--- a/arch/arm/mach-bcmring/mm.c
+++ b/arch/arm/mach-bcmring/mm.c
@@ -20,12 +20,12 @@
#include <mach/hardware.h>
#include <mach/csp/mm_io.h>
-#define IO_DESC(va, sz) { .virtual = va, \
+#define IO_DESC(va, sz) { .virtual = (unsigned long)va, \
.pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
.length = sz, \
.type = MT_DEVICE }
-#define MEM_DESC(va, sz) { .virtual = va, \
+#define MEM_DESC(va, sz) { .virtual = (unsigned long)va, \
.pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
.length = sz, \
.type = MT_MEMORY }
diff --git a/arch/arm/mach-bcmring/timer.c b/arch/arm/mach-bcmring/timer.c
index af9c3d7..5941290 100644
--- a/arch/arm/mach-bcmring/timer.c
+++ b/arch/arm/mach-bcmring/timer.c
@@ -14,7 +14,7 @@
#include <linux/types.h>
#include <linux/module.h>
-#include <csp/tmrHw.h>
+#include <mach/csp/tmrHw.h>
#include <mach/timer.h>
/* The core.c file initializes timers 1 and 3 as a linux clocksource. */
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 6321567..cc4c6a5 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -49,16 +49,6 @@
.pfn = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
.length = DOVE_NB_REGS_SIZE,
.type = MT_DEVICE,
- }, {
- .virtual = DOVE_PCIE0_IO_VIRT_BASE,
- .pfn = __phys_to_pfn(DOVE_PCIE0_IO_PHYS_BASE),
- .length = DOVE_PCIE0_IO_SIZE,
- .type = MT_DEVICE,
- }, {
- .virtual = DOVE_PCIE1_IO_VIRT_BASE,
- .pfn = __phys_to_pfn(DOVE_PCIE1_IO_PHYS_BASE),
- .length = DOVE_PCIE1_IO_SIZE,
- .type = MT_DEVICE,
},
};
diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h
index d52b0ef..c91e300 100644
--- a/arch/arm/mach-dove/include/mach/dove.h
+++ b/arch/arm/mach-dove/include/mach/dove.h
@@ -50,14 +50,12 @@
#define DOVE_NB_REGS_SIZE SZ_8M
#define DOVE_PCIE0_IO_PHYS_BASE 0xf2000000
-#define DOVE_PCIE0_IO_VIRT_BASE 0xfee00000
#define DOVE_PCIE0_IO_BUS_BASE 0x00000000
-#define DOVE_PCIE0_IO_SIZE SZ_1M
+#define DOVE_PCIE0_IO_SIZE SZ_64K
#define DOVE_PCIE1_IO_PHYS_BASE 0xf2100000
-#define DOVE_PCIE1_IO_VIRT_BASE 0xfef00000
-#define DOVE_PCIE1_IO_BUS_BASE 0x00100000
-#define DOVE_PCIE1_IO_SIZE SZ_1M
+#define DOVE_PCIE1_IO_BUS_BASE 0x00010000
+#define DOVE_PCIE1_IO_SIZE SZ_64K
/*
* Dove Core Registers Map
diff --git a/arch/arm/mach-dove/include/mach/io.h b/arch/arm/mach-dove/include/mach/io.h
deleted file mode 100644
index 29c8b85..0000000
--- a/arch/arm/mach-dove/include/mach/io.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-dove/include/mach/io.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-
-#include "dove.h"
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-#define __io(a) ((void __iomem *)(((a) - DOVE_PCIE0_IO_BUS_BASE) + \
- DOVE_PCIE0_IO_VIRT_BASE))
-
-#endif
diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c
index 47921b0..355332d 100644
--- a/arch/arm/mach-dove/pcie.c
+++ b/arch/arm/mach-dove/pcie.c
@@ -26,9 +26,8 @@
u8 root_bus_nr;
void __iomem *base;
spinlock_t conf_lock;
- char io_space_name[16];
char mem_space_name[16];
- struct resource res[2];
+ struct resource res;
};
static struct pcie_port pcie_port[2];
@@ -53,24 +52,10 @@
orion_pcie_setup(pp->base);
- /*
- * IORESOURCE_IO
- */
- snprintf(pp->io_space_name, sizeof(pp->io_space_name),
- "PCIe %d I/O", pp->index);
- pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
- pp->res[0].name = pp->io_space_name;
- if (pp->index == 0) {
- pp->res[0].start = DOVE_PCIE0_IO_PHYS_BASE;
- pp->res[0].end = pp->res[0].start + DOVE_PCIE0_IO_SIZE - 1;
- } else {
- pp->res[0].start = DOVE_PCIE1_IO_PHYS_BASE;
- pp->res[0].end = pp->res[0].start + DOVE_PCIE1_IO_SIZE - 1;
- }
- pp->res[0].flags = IORESOURCE_IO;
- if (request_resource(&ioport_resource, &pp->res[0]))
- panic("Request PCIe IO resource failed\n");
- pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
+ if (pp->index == 0)
+ pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE0_IO_PHYS_BASE);
+ else
+ pci_ioremap_io(sys->busnr * SZ_64K, DOVE_PCIE1_IO_PHYS_BASE);
/*
* IORESOURCE_MEM
@@ -78,18 +63,18 @@
snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
"PCIe %d MEM", pp->index);
pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
- pp->res[1].name = pp->mem_space_name;
+ pp->res.name = pp->mem_space_name;
if (pp->index == 0) {
- pp->res[1].start = DOVE_PCIE0_MEM_PHYS_BASE;
- pp->res[1].end = pp->res[1].start + DOVE_PCIE0_MEM_SIZE - 1;
+ pp->res.start = DOVE_PCIE0_MEM_PHYS_BASE;
+ pp->res.end = pp->res.start + DOVE_PCIE0_MEM_SIZE - 1;
} else {
- pp->res[1].start = DOVE_PCIE1_MEM_PHYS_BASE;
- pp->res[1].end = pp->res[1].start + DOVE_PCIE1_MEM_SIZE - 1;
+ pp->res.start = DOVE_PCIE1_MEM_PHYS_BASE;
+ pp->res.end = pp->res.start + DOVE_PCIE1_MEM_SIZE - 1;
}
- pp->res[1].flags = IORESOURCE_MEM;
- if (request_resource(&iomem_resource, &pp->res[1]))
+ pp->res.flags = IORESOURCE_MEM;
+ if (request_resource(&iomem_resource, &pp->res))
panic("Request PCIe Memory resource failed\n");
- pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
+ pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
return 1;
}
@@ -210,7 +195,7 @@
pp->root_bus_nr = -1;
pp->base = (void __iomem *)base;
spin_lock_init(&pp->conf_lock);
- memset(pp->res, 0, sizeof(pp->res));
+ memset(&pp->res, 0, sizeof(pp->res));
} else {
printk(KERN_INFO "link down, ignoring\n");
}
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index 3e6aaa6..a42b369 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -15,7 +15,7 @@
#include <linux/init.h>
#include <linux/io.h>
#include <linux/spinlock.h>
-
+
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/irq.h>
@@ -26,6 +26,7 @@
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
+#include <asm/mach/pci.h>
#include "common.h"
@@ -175,11 +176,6 @@
.pfn = __phys_to_pfn(DC21285_PCI_IACK),
.length = PCIIACK_SIZE,
.type = MT_DEVICE,
- }, {
- .virtual = PCIO_BASE,
- .pfn = __phys_to_pfn(DC21285_PCI_IO),
- .length = PCIO_SIZE,
- .type = MT_DEVICE,
},
#endif
};
@@ -196,8 +192,10 @@
* Now, work out what we've got to map in addition on this
* platform.
*/
- if (footbridge_cfn_mode())
+ if (footbridge_cfn_mode()) {
iotable_init(ebsa285_host_io_desc, ARRAY_SIZE(ebsa285_host_io_desc));
+ pci_map_io_early(__phys_to_pfn(DC21285_PCI_IO));
+ }
}
void footbridge_restart(char mode, const char *cmd)
diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c
index 9d62e33..a7cd2cf 100644
--- a/arch/arm/mach-footbridge/dc21285.c
+++ b/arch/arm/mach-footbridge/dc21285.c
@@ -276,8 +276,8 @@
sys->mem_offset = DC21285_PCI_MEM;
- pci_add_resource_offset(&sys->resources,
- &ioport_resource, sys->io_offset);
+ pci_ioremap_io(0, DC21285_PCI_IO);
+
pci_add_resource_offset(&sys->resources, &res[0], sys->mem_offset);
pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
@@ -298,7 +298,7 @@
mem_size = (unsigned int)high_memory - PAGE_OFFSET;
for (mem_mask = 0x00100000; mem_mask < 0x10000000; mem_mask <<= 1)
if (mem_mask >= mem_size)
- break;
+ break;
/*
* These registers need to be set up whether we're the
@@ -350,14 +350,6 @@
"PCI data parity", NULL);
if (cfn_mode) {
- static struct resource csrio;
-
- csrio.flags = IORESOURCE_IO;
- csrio.name = "Footbridge";
-
- allocate_resource(&ioport_resource, &csrio, 128,
- 0xff00, 0xffff, 128, NULL, NULL);
-
/*
* Map our SDRAM at a known address in PCI space, just in case
* the firmware had other ideas. Using a nonzero base is
@@ -365,7 +357,7 @@
* in the range 0x000a0000 to 0x000c0000. (eg, S3 cards).
*/
*CSR_PCICSRBASE = 0xf4000000;
- *CSR_PCICSRIOBASE = csrio.start;
+ *CSR_PCICSRIOBASE = 0;
*CSR_PCISDRAMBASE = __virt_to_bus(PAGE_OFFSET);
*CSR_PCIROMBASE = 0;
*CSR_PCICMD = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
diff --git a/arch/arm/mach-footbridge/include/mach/debug-macro.S b/arch/arm/mach-footbridge/include/mach/debug-macro.S
index e5acde2..c169f0c 100644
--- a/arch/arm/mach-footbridge/include/mach/debug-macro.S
+++ b/arch/arm/mach-footbridge/include/mach/debug-macro.S
@@ -17,7 +17,8 @@
/* For NetWinder debugging */
.macro addruart, rp, rv, tmp
mov \rp, #0x000003f8
- orr \rv, \rp, #0xff000000 @ virtual
+ orr \rv, \rp, #0xfe000000 @ virtual
+ orr \rv, \rv, #0x00e00000 @ virtual
orr \rp, \rp, #0x7c000000 @ physical
.endm
diff --git a/arch/arm/mach-footbridge/include/mach/io.h b/arch/arm/mach-footbridge/include/mach/io.h
index aba531ee..aba4638 100644
--- a/arch/arm/mach-footbridge/include/mach/io.h
+++ b/arch/arm/mach-footbridge/include/mach/io.h
@@ -14,18 +14,10 @@
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
-#ifdef CONFIG_MMU
-#define MMU_IO(a, b) (a)
-#else
-#define MMU_IO(a, b) (b)
-#endif
-
-#define PCIO_SIZE 0x00100000
-#define PCIO_BASE MMU_IO(0xff000000, 0x7c000000)
-
/*
- * Translation of various region addresses to virtual addresses
+ * Translation of various i/o addresses to host addresses for !CONFIG_MMU
*/
+#define PCIO_BASE 0x7c000000
#define __io(a) ((void __iomem *)(PCIO_BASE + (a)))
#endif
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index d004d37..d120419 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -13,7 +13,7 @@
obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y) cpu_op-mx51.o
obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
- clk-pfd.o clk-busy.o
+ clk-pfd.o clk-busy.o clk.o
# Support for CMOS sensor interface
obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c
index ea13e61..cf65148 100644
--- a/arch/arm/mach-imx/clk-imx21.c
+++ b/arch/arm/mach-imx/clk-imx21.c
@@ -23,7 +23,6 @@
#include <linux/clk-provider.h>
#include <linux/io.h>
#include <linux/module.h>
-#include <linux/clkdev.h>
#include <linux/err.h>
#include <mach/hardware.h>
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 4bdcaa9..f89c440 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -39,10 +39,10 @@
static const char *emi_slow_sel[] = { "main_bus", "ahb", };
static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", };
static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", };
-static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0", };
+static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0_gate", };
static const char *mx53_ldb_di0_sel[] = { "pll3_sw", "pll4_sw", };
static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", };
-static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1", };
+static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1_gate", };
static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", };
static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", };
static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", };
diff --git a/arch/arm/mach-imx/clk-pllv1.c b/arch/arm/mach-imx/clk-pllv1.c
index 2d856f9c..02be731 100644
--- a/arch/arm/mach-imx/clk-pllv1.c
+++ b/arch/arm/mach-imx/clk-pllv1.c
@@ -6,7 +6,7 @@
#include <linux/err.h>
#include <mach/common.h>
#include <mach/hardware.h>
-#include <mach/clock.h>
+
#include "clk.h"
/**
@@ -29,8 +29,53 @@
unsigned long parent_rate)
{
struct clk_pllv1 *pll = to_clk_pllv1(hw);
+ long long ll;
+ int mfn_abs;
+ unsigned int mfi, mfn, mfd, pd;
+ u32 reg;
+ unsigned long rate;
- return mxc_decode_pll(readl(pll->base), parent_rate);
+ reg = readl(pll->base);
+
+ /*
+ * Get the resulting clock rate from a PLL register value and the input
+ * frequency. PLLs with this register layout can be found on i.MX1,
+ * i.MX21, i.MX27 and i,MX31
+ *
+ * mfi + mfn / (mfd + 1)
+ * f = 2 * f_ref * --------------------
+ * pd + 1
+ */
+
+ mfi = (reg >> 10) & 0xf;
+ mfn = reg & 0x3ff;
+ mfd = (reg >> 16) & 0x3ff;
+ pd = (reg >> 26) & 0xf;
+
+ mfi = mfi <= 5 ? 5 : mfi;
+
+ mfn_abs = mfn;
+
+ /*
+ * On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
+ * 2's complements number
+ */
+ if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
+ mfn_abs = 0x400 - mfn;
+
+ rate = parent_rate * 2;
+ rate /= pd + 1;
+
+ ll = (unsigned long long)rate * mfn_abs;
+
+ do_div(ll, mfd + 1);
+
+ if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
+ ll = -ll;
+
+ ll = (rate * mfi) + ll;
+
+ return ll;
}
struct clk_ops clk_pllv1_ops = {
diff --git a/arch/arm/mach-imx/clk.c b/arch/arm/mach-imx/clk.c
new file mode 100644
index 0000000..f5e8be8
--- /dev/null
+++ b/arch/arm/mach-imx/clk.c
@@ -0,0 +1,3 @@
+#include <linux/spinlock.h>
+
+DEFINE_SPINLOCK(imx_ccm_lock);
diff --git a/arch/arm/mach-imx/clk.h b/arch/arm/mach-imx/clk.h
index 1bf64fe..5f2d8ac 100644
--- a/arch/arm/mach-imx/clk.h
+++ b/arch/arm/mach-imx/clk.h
@@ -3,7 +3,8 @@
#include <linux/spinlock.h>
#include <linux/clk-provider.h>
-#include <mach/clock.h>
+
+extern spinlock_t imx_ccm_lock;
struct clk *imx_clk_pllv1(const char *name, const char *parent,
void __iomem *base);
diff --git a/arch/arm/mach-imx/mach-kzm_arm11_01.c b/arch/arm/mach-imx/mach-kzm_arm11_01.c
index 5d08533..8dc9d3e 100644
--- a/arch/arm/mach-imx/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-imx/mach-kzm_arm11_01.c
@@ -36,7 +36,6 @@
#include <asm/mach/map.h>
#include <asm/mach/time.h>
-#include <mach/clock.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx3.h>
diff --git a/arch/arm/mach-integrator/include/mach/io.h b/arch/arm/mach-integrator/include/mach/io.h
deleted file mode 100644
index 8de70de..0000000
--- a/arch/arm/mach-integrator/include/mach/io.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * arch/arm/mach-integrator/include/mach/io.h
- *
- * Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-/*
- * WARNING: this has to mirror definitions in platform.h
- */
-#define PCI_MEMORY_VADDR 0xe8000000
-#define PCI_CONFIG_VADDR 0xec000000
-#define PCI_V3_VADDR 0xed000000
-#define PCI_IO_VADDR 0xee000000
-
-#define __io(a) ((void __iomem *)(PCI_IO_VADDR + (a)))
-
-#endif
diff --git a/arch/arm/mach-integrator/include/mach/platform.h b/arch/arm/mach-integrator/include/mach/platform.h
index ec467ba..4c03475 100644
--- a/arch/arm/mach-integrator/include/mach/platform.h
+++ b/arch/arm/mach-integrator/include/mach/platform.h
@@ -324,6 +324,10 @@
*/
#define PHYS_PCI_V3_BASE 0x62000000
+#define PCI_MEMORY_VADDR 0xe8000000
+#define PCI_CONFIG_VADDR 0xec000000
+#define PCI_V3_VADDR 0xed000000
+
/* ------------------------------------------------------------------------
* Integrator Interrupt Controllers
* ------------------------------------------------------------------------
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index 3b22675..fd3ef28 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -50,6 +50,7 @@
#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
+#include <asm/mach/pci.h>
#include <asm/mach/time.h>
#include <plat/fpga-irq.h>
@@ -73,7 +74,7 @@
* e8000000 40000000 PCI memory PHYS_PCI_MEM_BASE (max 512M)
* ec000000 61000000 PCI config space PHYS_PCI_CONFIG_BASE (max 16M)
* ed000000 62000000 PCI V3 regs PHYS_PCI_V3_BASE (max 64k)
- * ee000000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M)
+ * fee00000 60000000 PCI IO PHYS_PCI_IO_BASE (max 16M)
* ef000000 Cache flush
* f1000000 10000000 Core module registers
* f1100000 11000000 System controller registers
@@ -147,11 +148,6 @@
.pfn = __phys_to_pfn(PHYS_PCI_V3_BASE),
.length = SZ_64K,
.type = MT_DEVICE
- }, {
- .virtual = PCI_IO_VADDR,
- .pfn = __phys_to_pfn(PHYS_PCI_IO_BASE),
- .length = SZ_64K,
- .type = MT_DEVICE
}
};
@@ -159,6 +155,7 @@
{
iotable_init(ap_io_desc, ARRAY_SIZE(ap_io_desc));
vga_base = PCI_MEMORY_VADDR;
+ pci_map_io_early(__phys_to_pfn(PHYS_PCI_IO_BASE));
}
#define INTEGRATOR_SC_VALID_INT 0x003fffff
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index b866880..495f181 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -41,61 +41,61 @@
/*
* The V3 PCI interface chip in Integrator provides several windows from
* local bus memory into the PCI memory areas. Unfortunately, there
- * are not really enough windows for our usage, therefore we reuse
+ * are not really enough windows for our usage, therefore we reuse
* one of the windows for access to PCI configuration space. The
* memory map is as follows:
- *
+ *
* Local Bus Memory Usage
- *
+ *
* 40000000 - 4FFFFFFF PCI memory. 256M non-prefetchable
* 50000000 - 5FFFFFFF PCI memory. 256M prefetchable
* 60000000 - 60FFFFFF PCI IO. 16M
* 61000000 - 61FFFFFF PCI Configuration. 16M
- *
+ *
* There are three V3 windows, each described by a pair of V3 registers.
* These are LB_BASE0/LB_MAP0, LB_BASE1/LB_MAP1 and LB_BASE2/LB_MAP2.
* Base0 and Base1 can be used for any type of PCI memory access. Base2
* can be used either for PCI I/O or for I20 accesses. By default, uHAL
* uses this only for PCI IO space.
- *
+ *
* Normally these spaces are mapped using the following base registers:
- *
+ *
* Usage Local Bus Memory Base/Map registers used
- *
+ *
* Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
* Mem 50000000 - 5FFFFFFF LB_BASE1/LB_MAP1
* IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
* Cfg 61000000 - 61FFFFFF
- *
+ *
* This means that I20 and PCI configuration space accesses will fail.
- * When PCI configuration accesses are needed (via the uHAL PCI
+ * When PCI configuration accesses are needed (via the uHAL PCI
* configuration space primitives) we must remap the spaces as follows:
- *
+ *
* Usage Local Bus Memory Base/Map registers used
- *
+ *
* Mem 40000000 - 4FFFFFFF LB_BASE0/LB_MAP0
* Mem 50000000 - 5FFFFFFF LB_BASE0/LB_MAP0
* IO 60000000 - 60FFFFFF LB_BASE2/LB_MAP2
* Cfg 61000000 - 61FFFFFF LB_BASE1/LB_MAP1
- *
+ *
* To make this work, the code depends on overlapping windows working.
- * The V3 chip translates an address by checking its range within
+ * The V3 chip translates an address by checking its range within
* each of the BASE/MAP pairs in turn (in ascending register number
* order). It will use the first matching pair. So, for example,
* if the same address is mapped by both LB_BASE0/LB_MAP0 and
- * LB_BASE1/LB_MAP1, the V3 will use the translation from
+ * LB_BASE1/LB_MAP1, the V3 will use the translation from
* LB_BASE0/LB_MAP0.
- *
+ *
* To allow PCI Configuration space access, the code enlarges the
* window mapped by LB_BASE0/LB_MAP0 from 256M to 512M. This occludes
* the windows currently mapped by LB_BASE1/LB_MAP1 so that it can
* be remapped for use by configuration cycles.
- *
- * At the end of the PCI Configuration space accesses,
+ *
+ * At the end of the PCI Configuration space accesses,
* LB_BASE1/LB_MAP1 is reset to map PCI Memory. Finally the window
* mapped by LB_BASE0/LB_MAP0 is reduced in size from 512M to 256M to
* reveal the now restored LB_BASE1/LB_MAP1 window.
- *
+ *
* NOTE: We do not set up I2O mapping. I suspect that this is only
* for an intelligent (target) device. Using I2O disables most of
* the mappings into PCI memory.
@@ -127,8 +127,8 @@
*
* returns: configuration address to play on the PCI bus
*
- * To generate the appropriate PCI configuration cycles in the PCI
- * configuration address space, you present the V3 with the following pattern
+ * To generate the appropriate PCI configuration cycles in the PCI
+ * configuration address space, you present the V3 with the following pattern
* (which is very nearly a type 1 (except that the lower two bits are 00 and
* not 01). In order for this mapping to work you need to set up one of
* the local to PCI aperatures to 16Mbytes in length translating to
@@ -138,7 +138,7 @@
*
* Type 0:
*
- * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
+ * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
* 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0|
@@ -150,7 +150,7 @@
*
* Type 1:
*
- * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
+ * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
* 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
* | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
@@ -161,7 +161,7 @@
* 15:11 Device number (5 bits)
* 10:8 function number
* 7:2 register number
- *
+ *
*/
static DEFINE_RAW_SPINLOCK(v3_lock);
@@ -374,12 +374,9 @@
}
/*
- * the IO resource for this bus
* the mem resource for this bus
* the prefetch mem resource for this bus
*/
- pci_add_resource_offset(&sys->resources,
- &ioport_resource, sys->io_offset);
pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset);
pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset);
@@ -498,7 +495,6 @@
unsigned int temp;
int ret;
- pcibios_min_io = 0x6000;
pcibios_min_mem = 0x00100000;
/*
diff --git a/arch/arm/mach-iop13xx/include/mach/io.h b/arch/arm/mach-iop13xx/include/mach/io.h
deleted file mode 100644
index f131885..0000000
--- a/arch/arm/mach-iop13xx/include/mach/io.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * iop13xx custom ioremap implementation
- * Copyright (c) 2005-2006, Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
- * Place - Suite 330, Boston, MA 02111-1307 USA.
- *
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-#define __io(a) __iop13xx_io(a)
-
-extern void __iomem * __iop13xx_io(unsigned long io_addr);
-
-#endif
diff --git a/arch/arm/mach-iop13xx/include/mach/iop13xx.h b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
index e190dcd..e10e101 100644
--- a/arch/arm/mach-iop13xx/include/mach/iop13xx.h
+++ b/arch/arm/mach-iop13xx/include/mach/iop13xx.h
@@ -69,21 +69,11 @@
* 0x8000.0000 + 928M 0x2.8000.0000 (ioremap) PCIE outbound memory window
*
* IO MAP
- * 0x1000 + 64K 0x0.fffb.1000 0xfec6.1000 PCIX outbound i/o window
- * 0x1000 + 64K 0x0.fffd.1000 0xfed7.1000 PCIE outbound i/o window
+ * 0x00000 + 64K 0x0.fffb.0000 0xfee0.0000 PCIX outbound i/o window
+ * 0x10000 + 64K 0x0.fffd.0000 0xfee1.0000 PCIE outbound i/o window
*/
-#define IOP13XX_PCIX_IO_WINDOW_SIZE 0x10000UL
#define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL
-#define IOP13XX_PCIX_LOWER_IO_VA 0xfec60000UL
#define IOP13XX_PCIX_LOWER_IO_BA 0x0UL /* OIOTVR */
-#define IOP13XX_PCIX_IO_BUS_OFFSET 0x1000UL
-#define IOP13XX_PCIX_UPPER_IO_PA (IOP13XX_PCIX_LOWER_IO_PA +\
- IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
-#define IOP13XX_PCIX_UPPER_IO_VA (IOP13XX_PCIX_LOWER_IO_VA +\
- IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
-#define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
- (IOP13XX_PCIX_LOWER_IO_PA\
- - IOP13XX_PCIX_LOWER_IO_VA))
#define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL
#define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL
@@ -103,20 +93,8 @@
IOP13XX_PCIX_LOWER_MEM_BA)
/* PCI-E ranges */
-#define IOP13XX_PCIE_IO_WINDOW_SIZE 0x10000UL
#define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL
-#define IOP13XX_PCIE_LOWER_IO_VA 0xfed70000UL
-#define IOP13XX_PCIE_LOWER_IO_BA 0x0UL /* OIOTVR */
-#define IOP13XX_PCIE_IO_BUS_OFFSET 0x1000UL
-#define IOP13XX_PCIE_UPPER_IO_PA (IOP13XX_PCIE_LOWER_IO_PA +\
- IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
-#define IOP13XX_PCIE_UPPER_IO_VA (IOP13XX_PCIE_LOWER_IO_VA +\
- IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
-#define IOP13XX_PCIE_UPPER_IO_BA (IOP13XX_PCIE_LOWER_IO_BA +\
- IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
-#define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
- (IOP13XX_PCIE_LOWER_IO_PA\
- - IOP13XX_PCIE_LOWER_IO_VA))
+#define IOP13XX_PCIE_LOWER_IO_BA 0x10000UL /* OIOTVR */
#define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL
#define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL
diff --git a/arch/arm/mach-iop13xx/io.c b/arch/arm/mach-iop13xx/io.c
index 3c36419..851dc8f 100644
--- a/arch/arm/mach-iop13xx/io.c
+++ b/arch/arm/mach-iop13xx/io.c
@@ -23,25 +23,6 @@
#include "pci.h"
-void * __iomem __iop13xx_io(unsigned long io_addr)
-{
- void __iomem * io_virt;
-
- switch (io_addr) {
- case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA:
- io_virt = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(io_addr);
- break;
- case IOP13XX_PCIX_LOWER_IO_PA ... IOP13XX_PCIX_UPPER_IO_PA:
- io_virt = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(io_addr);
- break;
- default:
- BUG();
- }
-
- return io_virt;
-}
-EXPORT_SYMBOL(__iop13xx_io);
-
static void __iomem *__iop13xx_ioremap_caller(unsigned long cookie,
size_t size, unsigned int mtype, void *caller)
{
@@ -67,12 +48,6 @@
(cookie - IOP13XX_PBI_LOWER_MEM_RA),
size, mtype, __builtin_return_address(0));
break;
- case IOP13XX_PCIE_LOWER_IO_PA ... IOP13XX_PCIE_UPPER_IO_PA:
- retval = (void *) IOP13XX_PCIE_IO_PHYS_TO_VIRT(cookie);
- break;
- case IOP13XX_PCIX_LOWER_IO_PA ... IOP13XX_PCIX_UPPER_IO_PA:
- retval = (void *) IOP13XX_PCIX_IO_PHYS_TO_VIRT(cookie);
- break;
case IOP13XX_PMMR_PHYS_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_PA:
retval = (void *) IOP13XX_PMMR_PHYS_TO_VIRT(cookie);
break;
@@ -99,8 +74,6 @@
goto skip;
switch ((u32) addr) {
- case IOP13XX_PCIE_LOWER_IO_VA ... IOP13XX_PCIE_UPPER_IO_VA:
- case IOP13XX_PCIX_LOWER_IO_VA ... IOP13XX_PCIX_UPPER_IO_VA:
case IOP13XX_PMMR_VIRT_MEM_BASE ... IOP13XX_PMMR_UPPER_MEM_VA:
goto skip;
}
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
index 861cb12..91f731a 100644
--- a/arch/arm/mach-iop13xx/pci.c
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -970,7 +970,6 @@
__raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR);
/* Setup the Min Address for PCI memory... */
- pcibios_min_io = 0;
pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA;
/* if Linux is given control of an ATU
@@ -1003,7 +1002,7 @@
if (nr > 1)
return 0;
- res = kcalloc(2, sizeof(struct resource), GFP_KERNEL);
+ res = kzalloc(sizeof(struct resource), GFP_KERNEL);
if (!res)
panic("PCI: unable to alloc resources");
@@ -1042,17 +1041,13 @@
<< IOP13XX_ATUX_PCIXSR_FUNC_NUM;
__raw_writel(pcixsr, IOP13XX_ATUX_PCIXSR);
- res[0].start = IOP13XX_PCIX_LOWER_IO_PA + IOP13XX_PCIX_IO_BUS_OFFSET;
- res[0].end = IOP13XX_PCIX_UPPER_IO_PA;
- res[0].name = "IQ81340 ATUX PCI I/O Space";
- res[0].flags = IORESOURCE_IO;
+ pci_ioremap_io(0, IOP13XX_PCIX_LOWER_IO_PA);
- res[1].start = IOP13XX_PCIX_LOWER_MEM_RA;
- res[1].end = IOP13XX_PCIX_UPPER_MEM_RA;
- res[1].name = "IQ81340 ATUX PCI Memory Space";
- res[1].flags = IORESOURCE_MEM;
+ res->start = IOP13XX_PCIX_LOWER_MEM_RA;
+ res->end = IOP13XX_PCIX_UPPER_MEM_RA;
+ res->name = "IQ81340 ATUX PCI Memory Space";
+ res->flags = IORESOURCE_MEM;
sys->mem_offset = IOP13XX_PCIX_MEM_OFFSET;
- sys->io_offset = IOP13XX_PCIX_LOWER_IO_PA;
break;
case IOP13XX_INIT_ATU_ATUE:
/* Note: the function number field in the PCSR is ro */
@@ -1063,17 +1058,13 @@
__raw_writel(pcsr, IOP13XX_ATUE_PCSR);
- res[0].start = IOP13XX_PCIE_LOWER_IO_PA + IOP13XX_PCIE_IO_BUS_OFFSET;
- res[0].end = IOP13XX_PCIE_UPPER_IO_PA;
- res[0].name = "IQ81340 ATUE PCI I/O Space";
- res[0].flags = IORESOURCE_IO;
+ pci_ioremap_io(SZ_64K, IOP13XX_PCIE_LOWER_IO_PA);
- res[1].start = IOP13XX_PCIE_LOWER_MEM_RA;
- res[1].end = IOP13XX_PCIE_UPPER_MEM_RA;
- res[1].name = "IQ81340 ATUE PCI Memory Space";
- res[1].flags = IORESOURCE_MEM;
+ res->start = IOP13XX_PCIE_LOWER_MEM_RA;
+ res->end = IOP13XX_PCIE_UPPER_MEM_RA;
+ res->name = "IQ81340 ATUE PCI Memory Space";
+ res->flags = IORESOURCE_MEM;
sys->mem_offset = IOP13XX_PCIE_MEM_OFFSET;
- sys->io_offset = IOP13XX_PCIE_LOWER_IO_PA;
sys->map_irq = iop13xx_pcie_map_irq;
break;
default:
@@ -1081,11 +1072,9 @@
return 0;
}
- request_resource(&ioport_resource, &res[0]);
- request_resource(&iomem_resource, &res[1]);
+ request_resource(&iomem_resource, res);
- pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
- pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
+ pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
return 1;
}
diff --git a/arch/arm/mach-iop13xx/setup.c b/arch/arm/mach-iop13xx/setup.c
index daabb1f..4a7f20d7 100644
--- a/arch/arm/mach-iop13xx/setup.c
+++ b/arch/arm/mach-iop13xx/setup.c
@@ -40,16 +40,6 @@
.pfn = __phys_to_pfn(IOP13XX_PMMR_PHYS_MEM_BASE),
.length = IOP13XX_PMMR_SIZE,
.type = MT_DEVICE,
- }, { /* PCIE IO space */
- .virtual = IOP13XX_PCIE_LOWER_IO_VA,
- .pfn = __phys_to_pfn(IOP13XX_PCIE_LOWER_IO_PA),
- .length = IOP13XX_PCIX_IO_WINDOW_SIZE,
- .type = MT_DEVICE,
- }, { /* PCIX IO space */
- .virtual = IOP13XX_PCIX_LOWER_IO_VA,
- .pfn = __phys_to_pfn(IOP13XX_PCIX_LOWER_IO_PA),
- .length = IOP13XX_PCIX_IO_WINDOW_SIZE,
- .type = MT_DEVICE,
},
};
diff --git a/arch/arm/mach-iop32x/include/mach/io.h b/arch/arm/mach-iop32x/include/mach/io.h
deleted file mode 100644
index e2ada26..0000000
--- a/arch/arm/mach-iop32x/include/mach/io.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-iop32x/include/mach/io.h
- *
- * Copyright (C) 2001 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __IO_H
-#define __IO_H
-
-#include <asm/hardware/iop3xx.h>
-
-#define IO_SPACE_LIMIT 0xffffffff
-#define __io(p) ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
-
-#endif
diff --git a/arch/arm/mach-iop33x/include/mach/io.h b/arch/arm/mach-iop33x/include/mach/io.h
deleted file mode 100644
index f7c1b65..0000000
--- a/arch/arm/mach-iop33x/include/mach/io.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-iop33x/include/mach/io.h
- *
- * Copyright (C) 2001 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __IO_H
-#define __IO_H
-
-#include <asm/hardware/iop3xx.h>
-
-#define IO_SPACE_LIMIT 0xffffffff
-#define __io(p) ((void __iomem *)IOP3XX_PCI_IO_PHYS_TO_VIRT(p))
-
-#endif
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 1201191..3f7b05f 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -42,16 +42,6 @@
****************************************************************************/
static struct map_desc kirkwood_io_desc[] __initdata = {
{
- .virtual = KIRKWOOD_PCIE_IO_VIRT_BASE,
- .pfn = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
- .length = KIRKWOOD_PCIE_IO_SIZE,
- .type = MT_DEVICE,
- }, {
- .virtual = KIRKWOOD_PCIE1_IO_VIRT_BASE,
- .pfn = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
- .length = KIRKWOOD_PCIE1_IO_SIZE,
- .type = MT_DEVICE,
- }, {
.virtual = KIRKWOOD_REGS_VIRT_BASE,
.pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
.length = KIRKWOOD_REGS_SIZE,
diff --git a/arch/arm/mach-kirkwood/include/mach/io.h b/arch/arm/mach-kirkwood/include/mach/io.h
deleted file mode 100644
index 5d0ab617..0000000
--- a/arch/arm/mach-kirkwood/include/mach/io.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * arch/arm/mach-kirkwood/include/mach/io.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-
-#include "kirkwood.h"
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-static inline void __iomem *__io(unsigned long addr)
-{
- return (void __iomem *)((addr - KIRKWOOD_PCIE_IO_BUS_BASE)
- + KIRKWOOD_PCIE_IO_VIRT_BASE);
-}
-
-#define __io(a) __io(a)
-
-#endif
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index c5b6851..af4f000 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -37,14 +37,12 @@
#define KIRKWOOD_NAND_MEM_SIZE SZ_1K
#define KIRKWOOD_PCIE1_IO_PHYS_BASE 0xf3000000
-#define KIRKWOOD_PCIE1_IO_VIRT_BASE 0xfef00000
-#define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00100000
-#define KIRKWOOD_PCIE1_IO_SIZE SZ_1M
+#define KIRKWOOD_PCIE1_IO_BUS_BASE 0x00010000
+#define KIRKWOOD_PCIE1_IO_SIZE SZ_64K
#define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000
-#define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfee00000
#define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000
-#define KIRKWOOD_PCIE_IO_SIZE SZ_1M
+#define KIRKWOOD_PCIE_IO_SIZE SZ_64K
#define KIRKWOOD_REGS_PHYS_BASE 0xf1000000
#define KIRKWOOD_REGS_VIRT_BASE 0xfed00000
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index 6e8b2ef..532d8ac 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -56,7 +56,7 @@
void __iomem *base;
spinlock_t conf_lock;
int irq;
- struct resource res[2];
+ struct resource res;
};
static int pcie_port_map[2];
@@ -137,20 +137,12 @@
pp->irq = IRQ_KIRKWOOD_PCIE;
/*
- * IORESOURCE_IO
- */
- pp->res[0].name = "PCIe 0 I/O Space";
- pp->res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE;
- pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
- pp->res[0].flags = IORESOURCE_IO;
-
- /*
* IORESOURCE_MEM
*/
- pp->res[1].name = "PCIe 0 MEM";
- pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
- pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
- pp->res[1].flags = IORESOURCE_MEM;
+ pp->res.name = "PCIe 0 MEM";
+ pp->res.start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
+ pp->res.end = pp->res.start + KIRKWOOD_PCIE_MEM_SIZE - 1;
+ pp->res.flags = IORESOURCE_MEM;
}
static void __init pcie1_ioresources_init(struct pcie_port *pp)
@@ -159,20 +151,12 @@
pp->irq = IRQ_KIRKWOOD_PCIE1;
/*
- * IORESOURCE_IO
- */
- pp->res[0].name = "PCIe 1 I/O Space";
- pp->res[0].start = KIRKWOOD_PCIE1_IO_BUS_BASE;
- pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
- pp->res[0].flags = IORESOURCE_IO;
-
- /*
* IORESOURCE_MEM
*/
- pp->res[1].name = "PCIe 1 MEM";
- pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
- pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
- pp->res[1].flags = IORESOURCE_MEM;
+ pp->res.name = "PCIe 1 MEM";
+ pp->res.start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
+ pp->res.end = pp->res.start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
+ pp->res.flags = IORESOURCE_MEM;
}
static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
@@ -197,23 +181,21 @@
case 0:
kirkwood_enable_pcie_clk("0");
pcie0_ioresources_init(pp);
+ pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE_IO_PHYS_BASE);
break;
case 1:
kirkwood_enable_pcie_clk("1");
pcie1_ioresources_init(pp);
+ pci_ioremap_io(SZ_64K * sys->busnr, KIRKWOOD_PCIE1_IO_PHYS_BASE);
break;
default:
panic("PCIe setup: invalid controller %d", index);
}
- if (request_resource(&ioport_resource, &pp->res[0]))
- panic("Request PCIe%d IO resource failed\n", index);
- if (request_resource(&iomem_resource, &pp->res[1]))
+ if (request_resource(&iomem_resource, &pp->res))
panic("Request PCIe%d Memory resource failed\n", index);
- sys->io_offset = 0;
- pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
- pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
+ pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
/*
* Generic PCIe unit setup.
diff --git a/arch/arm/mach-ks8695/include/mach/regs-timer.h b/arch/arm/mach-ks8695/include/mach/regs-timer.h
deleted file mode 100644
index e620cda..0000000
--- a/arch/arm/mach-ks8695/include/mach/regs-timer.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * arch/arm/mach-ks8695/include/mach/regs-timer.h
- *
- * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk>
- * Copyright (C) 2006 Simtec Electronics
- *
- * KS8695 - Timer registers and bit definitions.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef KS8695_TIMER_H
-#define KS8695_TIMER_H
-
-#define KS8695_TMR_OFFSET (0xF0000 + 0xE400)
-#define KS8695_TMR_VA (KS8695_IO_VA + KS8695_TMR_OFFSET)
-#define KS8695_TMR_PA (KS8695_IO_PA + KS8695_TMR_OFFSET)
-
-
-/*
- * Timer registers
- */
-#define KS8695_TMCON (0x00) /* Timer Control Register */
-#define KS8695_T1TC (0x04) /* Timer 1 Timeout Count Register */
-#define KS8695_T0TC (0x08) /* Timer 0 Timeout Count Register */
-#define KS8695_T1PD (0x0C) /* Timer 1 Pulse Count Register */
-#define KS8695_T0PD (0x10) /* Timer 0 Pulse Count Register */
-
-
-/* Timer Control Register */
-#define TMCON_T1EN (1 << 1) /* Timer 1 Enable */
-#define TMCON_T0EN (1 << 0) /* Timer 0 Enable */
-
-/* Timer0 Timeout Counter Register */
-#define T0TC_WATCHDOG (0xff) /* Enable watchdog mode */
-
-
-#endif
diff --git a/arch/arm/mach-ks8695/time.c b/arch/arm/mach-ks8695/time.c
index ec783a3..46c84bc 100644
--- a/arch/arm/mach-ks8695/time.c
+++ b/arch/arm/mach-ks8695/time.c
@@ -25,53 +25,98 @@
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/io.h>
+#include <linux/clockchips.h>
#include <asm/mach/time.h>
#include <asm/system_misc.h>
-#include <mach/regs-timer.h>
#include <mach/regs-irq.h>
#include "generic.h"
+#define KS8695_TMR_OFFSET (0xF0000 + 0xE400)
+#define KS8695_TMR_VA (KS8695_IO_VA + KS8695_TMR_OFFSET)
+#define KS8695_TMR_PA (KS8695_IO_PA + KS8695_TMR_OFFSET)
+
/*
- * Returns number of ms since last clock interrupt. Note that interrupts
- * will have been disabled by do_gettimeoffset()
+ * Timer registers
*/
-static unsigned long ks8695_gettimeoffset (void)
+#define KS8695_TMCON (0x00) /* Timer Control Register */
+#define KS8695_T1TC (0x04) /* Timer 1 Timeout Count Register */
+#define KS8695_T0TC (0x08) /* Timer 0 Timeout Count Register */
+#define KS8695_T1PD (0x0C) /* Timer 1 Pulse Count Register */
+#define KS8695_T0PD (0x10) /* Timer 0 Pulse Count Register */
+
+/* Timer Control Register */
+#define TMCON_T1EN (1 << 1) /* Timer 1 Enable */
+#define TMCON_T0EN (1 << 0) /* Timer 0 Enable */
+
+/* Timer0 Timeout Counter Register */
+#define T0TC_WATCHDOG (0xff) /* Enable watchdog mode */
+
+static void ks8695_set_mode(enum clock_event_mode mode,
+ struct clock_event_device *evt)
{
- unsigned long elapsed, tick2, intpending;
+ u32 tmcon;
- /*
- * Get the current number of ticks. Note that there is a race
- * condition between us reading the timer and checking for an
- * interrupt. We solve this by ensuring that the counter has not
- * reloaded between our two reads.
- */
- elapsed = __raw_readl(KS8695_TMR_VA + KS8695_T1TC) + __raw_readl(KS8695_TMR_VA + KS8695_T1PD);
- do {
- tick2 = elapsed;
- intpending = __raw_readl(KS8695_IRQ_VA + KS8695_INTST) & (1 << KS8695_IRQ_TIMER1);
- elapsed = __raw_readl(KS8695_TMR_VA + KS8695_T1TC) + __raw_readl(KS8695_TMR_VA + KS8695_T1PD);
- } while (elapsed > tick2);
+ if (mode == CLOCK_EVT_FEAT_PERIODIC) {
+ u32 rate = DIV_ROUND_CLOSEST(KS8695_CLOCK_RATE, HZ);
+ u32 half = DIV_ROUND_CLOSEST(rate, 2);
- /* Convert to number of ticks expired (not remaining) */
- elapsed = (CLOCK_TICK_RATE / HZ) - elapsed;
+ /* Disable timer 1 */
+ tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
+ tmcon &= ~TMCON_T1EN;
+ writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
- /* Is interrupt pending? If so, then timer has been reloaded already. */
- if (intpending)
- elapsed += (CLOCK_TICK_RATE / HZ);
+ /* Both registers need to count down */
+ writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC);
+ writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD);
- /* Convert ticks to usecs */
- return (unsigned long)(elapsed * (tick_nsec / 1000)) / LATCH;
+ /* Re-enable timer1 */
+ tmcon |= TMCON_T1EN;
+ writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
+ }
}
+static int ks8695_set_next_event(unsigned long cycles,
+ struct clock_event_device *evt)
+
+{
+ u32 half = DIV_ROUND_CLOSEST(cycles, 2);
+ u32 tmcon;
+
+ /* Disable timer 1 */
+ tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
+ tmcon &= ~TMCON_T1EN;
+ writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
+
+ /* Both registers need to count down */
+ writel_relaxed(half, KS8695_TMR_VA + KS8695_T1TC);
+ writel_relaxed(half, KS8695_TMR_VA + KS8695_T1PD);
+
+ /* Re-enable timer1 */
+ tmcon |= TMCON_T1EN;
+ writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
+
+ return 0;
+}
+
+static struct clock_event_device clockevent_ks8695 = {
+ .name = "ks8695_t1tc",
+ .rating = 300, /* Reasonably fast and accurate clock event */
+ .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
+ .set_next_event = ks8695_set_next_event,
+ .set_mode = ks8695_set_mode,
+};
+
/*
* IRQ handler for the timer.
*/
static irqreturn_t ks8695_timer_interrupt(int irq, void *dev_id)
{
- timer_tick();
+ struct clock_event_device *evt = &clockevent_ks8695;
+
+ evt->event_handler(evt);
return IRQ_HANDLED;
}
@@ -83,18 +128,22 @@
static void ks8695_timer_setup(void)
{
- unsigned long tmout = CLOCK_TICK_RATE / HZ;
unsigned long tmcon;
- /* disable timer1 */
- tmcon = __raw_readl(KS8695_TMR_VA + KS8695_TMCON);
- __raw_writel(tmcon & ~TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON);
+ /* Disable timer 0 and 1 */
+ tmcon = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
+ tmcon &= ~TMCON_T0EN;
+ tmcon &= ~TMCON_T1EN;
+ writel_relaxed(tmcon, KS8695_TMR_VA + KS8695_TMCON);
- __raw_writel(tmout / 2, KS8695_TMR_VA + KS8695_T1TC);
- __raw_writel(tmout / 2, KS8695_TMR_VA + KS8695_T1PD);
-
- /* re-enable timer1 */
- __raw_writel(tmcon | TMCON_T1EN, KS8695_TMR_VA + KS8695_TMCON);
+ /*
+ * Use timer 1 to fire IRQs on the timeline, minimum 2 cycles
+ * (one on each counter) maximum 2*2^32, but the API will only
+ * accept up to a 32bit full word (0xFFFFFFFFU).
+ */
+ clockevents_config_and_register(&clockevent_ks8695,
+ KS8695_CLOCK_RATE, 2,
+ 0xFFFFFFFFU);
}
static void __init ks8695_timer_init (void)
@@ -107,8 +156,6 @@
struct sys_timer ks8695_timer = {
.init = ks8695_timer_init,
- .offset = ks8695_gettimeoffset,
- .resume = ks8695_timer_setup,
};
void ks8695_restart(char mode, const char *cmd)
@@ -119,12 +166,12 @@
soft_restart(0);
/* disable timer0 */
- reg = __raw_readl(KS8695_TMR_VA + KS8695_TMCON);
- __raw_writel(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
+ reg = readl_relaxed(KS8695_TMR_VA + KS8695_TMCON);
+ writel_relaxed(reg & ~TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
/* enable watchdog mode */
- __raw_writel((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC);
+ writel_relaxed((10 << 8) | T0TC_WATCHDOG, KS8695_TMR_VA + KS8695_T0TC);
/* re-enable timer0 */
- __raw_writel(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
+ writel_relaxed(reg | TMCON_T0EN, KS8695_TMR_VA + KS8695_TMCON);
}
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index b786f7e..095c155 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -2,13 +2,19 @@
# Makefile for Marvell's PXA168 processors line
#
-obj-y += common.o clock.o devices.o time.o irq.o
+obj-y += common.o devices.o time.o irq.o
# SoC support
obj-$(CONFIG_CPU_PXA168) += pxa168.o
obj-$(CONFIG_CPU_PXA910) += pxa910.o
obj-$(CONFIG_CPU_MMP2) += mmp2.o sram.o
+ifeq ($(CONFIG_COMMON_CLK), )
+obj-y += clock.o
+obj-$(CONFIG_CPU_PXA168) += clock-pxa168.o
+obj-$(CONFIG_CPU_PXA910) += clock-pxa910.o
+obj-$(CONFIG_CPU_MMP2) += clock-mmp2.o
+endif
ifeq ($(CONFIG_PM),y)
obj-$(CONFIG_CPU_PXA910) += pm-pxa910.o
obj-$(CONFIG_CPU_MMP2) += pm-mmp2.o
diff --git a/arch/arm/mach-mmp/clock-mmp2.c b/arch/arm/mach-mmp/clock-mmp2.c
new file mode 100644
index 0000000..21d2200
--- /dev/null
+++ b/arch/arm/mach-mmp/clock-mmp2.c
@@ -0,0 +1,111 @@
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+
+#include <mach/addr-map.h>
+
+#include "common.h"
+#include "clock.h"
+
+/*
+ * APB Clock register offsets for MMP2
+ */
+#define APBC_RTC APBC_REG(0x000)
+#define APBC_TWSI1 APBC_REG(0x004)
+#define APBC_TWSI2 APBC_REG(0x008)
+#define APBC_TWSI3 APBC_REG(0x00c)
+#define APBC_TWSI4 APBC_REG(0x010)
+#define APBC_KPC APBC_REG(0x018)
+#define APBC_UART1 APBC_REG(0x02c)
+#define APBC_UART2 APBC_REG(0x030)
+#define APBC_UART3 APBC_REG(0x034)
+#define APBC_GPIO APBC_REG(0x038)
+#define APBC_PWM0 APBC_REG(0x03c)
+#define APBC_PWM1 APBC_REG(0x040)
+#define APBC_PWM2 APBC_REG(0x044)
+#define APBC_PWM3 APBC_REG(0x048)
+#define APBC_SSP0 APBC_REG(0x04c)
+#define APBC_SSP1 APBC_REG(0x050)
+#define APBC_SSP2 APBC_REG(0x054)
+#define APBC_SSP3 APBC_REG(0x058)
+#define APBC_SSP4 APBC_REG(0x05c)
+#define APBC_SSP5 APBC_REG(0x060)
+#define APBC_TWSI5 APBC_REG(0x07c)
+#define APBC_TWSI6 APBC_REG(0x080)
+#define APBC_UART4 APBC_REG(0x088)
+
+#define APMU_USB APMU_REG(0x05c)
+#define APMU_NAND APMU_REG(0x060)
+#define APMU_SDH0 APMU_REG(0x054)
+#define APMU_SDH1 APMU_REG(0x058)
+#define APMU_SDH2 APMU_REG(0x0e8)
+#define APMU_SDH3 APMU_REG(0x0ec)
+
+static void sdhc_clk_enable(struct clk *clk)
+{
+ uint32_t clk_rst;
+
+ clk_rst = __raw_readl(clk->clk_rst);
+ clk_rst |= clk->enable_val;
+ __raw_writel(clk_rst, clk->clk_rst);
+}
+
+static void sdhc_clk_disable(struct clk *clk)
+{
+ uint32_t clk_rst;
+
+ clk_rst = __raw_readl(clk->clk_rst);
+ clk_rst &= ~clk->enable_val;
+ __raw_writel(clk_rst, clk->clk_rst);
+}
+
+struct clkops sdhc_clk_ops = {
+ .enable = sdhc_clk_enable,
+ .disable = sdhc_clk_disable,
+};
+
+/* APB peripheral clocks */
+static APBC_CLK(uart1, UART1, 1, 26000000);
+static APBC_CLK(uart2, UART2, 1, 26000000);
+static APBC_CLK(uart3, UART3, 1, 26000000);
+static APBC_CLK(uart4, UART4, 1, 26000000);
+static APBC_CLK(twsi1, TWSI1, 0, 26000000);
+static APBC_CLK(twsi2, TWSI2, 0, 26000000);
+static APBC_CLK(twsi3, TWSI3, 0, 26000000);
+static APBC_CLK(twsi4, TWSI4, 0, 26000000);
+static APBC_CLK(twsi5, TWSI5, 0, 26000000);
+static APBC_CLK(twsi6, TWSI6, 0, 26000000);
+static APBC_CLK(gpio, GPIO, 0, 26000000);
+
+static APMU_CLK(nand, NAND, 0xbf, 100000000);
+static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops);
+static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops);
+static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops);
+static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops);
+
+static struct clk_lookup mmp2_clkregs[] = {
+ INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
+ INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
+ INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
+ INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL),
+ INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL),
+ INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL),
+ INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL),
+ INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL),
+ INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
+ INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
+ INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
+ INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
+ INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"),
+ INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"),
+ INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"),
+ INIT_CLKREG(&clk_sdh3, "sdhci-pxav3.3", "PXA-SDHCLK"),
+};
+
+void __init mmp2_clk_init(void)
+{
+ clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs));
+}
diff --git a/arch/arm/mach-mmp/clock-pxa168.c b/arch/arm/mach-mmp/clock-pxa168.c
new file mode 100644
index 0000000..5e6c18c
--- /dev/null
+++ b/arch/arm/mach-mmp/clock-pxa168.c
@@ -0,0 +1,91 @@
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+
+#include <mach/addr-map.h>
+
+#include "common.h"
+#include "clock.h"
+
+/*
+ * APB clock register offsets for PXA168
+ */
+#define APBC_UART1 APBC_REG(0x000)
+#define APBC_UART2 APBC_REG(0x004)
+#define APBC_GPIO APBC_REG(0x008)
+#define APBC_PWM1 APBC_REG(0x00c)
+#define APBC_PWM2 APBC_REG(0x010)
+#define APBC_PWM3 APBC_REG(0x014)
+#define APBC_PWM4 APBC_REG(0x018)
+#define APBC_RTC APBC_REG(0x028)
+#define APBC_TWSI0 APBC_REG(0x02c)
+#define APBC_KPC APBC_REG(0x030)
+#define APBC_TWSI1 APBC_REG(0x06c)
+#define APBC_UART3 APBC_REG(0x070)
+#define APBC_SSP1 APBC_REG(0x81c)
+#define APBC_SSP2 APBC_REG(0x820)
+#define APBC_SSP3 APBC_REG(0x84c)
+#define APBC_SSP4 APBC_REG(0x858)
+#define APBC_SSP5 APBC_REG(0x85c)
+
+#define APMU_NAND APMU_REG(0x060)
+#define APMU_LCD APMU_REG(0x04c)
+#define APMU_ETH APMU_REG(0x0fc)
+#define APMU_USB APMU_REG(0x05c)
+
+/* APB peripheral clocks */
+static APBC_CLK(uart1, UART1, 1, 14745600);
+static APBC_CLK(uart2, UART2, 1, 14745600);
+static APBC_CLK(uart3, UART3, 1, 14745600);
+static APBC_CLK(twsi0, TWSI0, 1, 33000000);
+static APBC_CLK(twsi1, TWSI1, 1, 33000000);
+static APBC_CLK(pwm1, PWM1, 1, 13000000);
+static APBC_CLK(pwm2, PWM2, 1, 13000000);
+static APBC_CLK(pwm3, PWM3, 1, 13000000);
+static APBC_CLK(pwm4, PWM4, 1, 13000000);
+static APBC_CLK(ssp1, SSP1, 4, 0);
+static APBC_CLK(ssp2, SSP2, 4, 0);
+static APBC_CLK(ssp3, SSP3, 4, 0);
+static APBC_CLK(ssp4, SSP4, 4, 0);
+static APBC_CLK(ssp5, SSP5, 4, 0);
+static APBC_CLK(gpio, GPIO, 0, 13000000);
+static APBC_CLK(keypad, KPC, 0, 32000);
+static APBC_CLK(rtc, RTC, 8, 32768);
+
+static APMU_CLK(nand, NAND, 0x19b, 156000000);
+static APMU_CLK(lcd, LCD, 0x7f, 312000000);
+static APMU_CLK(eth, ETH, 0x09, 0);
+static APMU_CLK(usb, USB, 0x12, 0);
+
+/* device and clock bindings */
+static struct clk_lookup pxa168_clkregs[] = {
+ INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
+ INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
+ INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
+ INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
+ INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
+ INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL),
+ INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL),
+ INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL),
+ INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL),
+ INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL),
+ INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL),
+ INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL),
+ INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL),
+ INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL),
+ INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
+ INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
+ INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
+ INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
+ INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
+ INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"),
+ INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
+};
+
+void __init pxa168_clk_init(void)
+{
+ clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs));
+}
diff --git a/arch/arm/mach-mmp/clock-pxa910.c b/arch/arm/mach-mmp/clock-pxa910.c
new file mode 100644
index 0000000..933ea71
--- /dev/null
+++ b/arch/arm/mach-mmp/clock-pxa910.c
@@ -0,0 +1,67 @@
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+
+#include <mach/addr-map.h>
+
+#include "common.h"
+#include "clock.h"
+
+/*
+ * APB Clock register offsets for PXA910
+ */
+#define APBC_UART0 APBC_REG(0x000)
+#define APBC_UART1 APBC_REG(0x004)
+#define APBC_GPIO APBC_REG(0x008)
+#define APBC_PWM1 APBC_REG(0x00c)
+#define APBC_PWM2 APBC_REG(0x010)
+#define APBC_PWM3 APBC_REG(0x014)
+#define APBC_PWM4 APBC_REG(0x018)
+#define APBC_SSP1 APBC_REG(0x01c)
+#define APBC_SSP2 APBC_REG(0x020)
+#define APBC_RTC APBC_REG(0x028)
+#define APBC_TWSI0 APBC_REG(0x02c)
+#define APBC_KPC APBC_REG(0x030)
+#define APBC_SSP3 APBC_REG(0x04c)
+#define APBC_TWSI1 APBC_REG(0x06c)
+
+#define APMU_NAND APMU_REG(0x060)
+#define APMU_USB APMU_REG(0x05c)
+
+static APBC_CLK(uart1, UART0, 1, 14745600);
+static APBC_CLK(uart2, UART1, 1, 14745600);
+static APBC_CLK(twsi0, TWSI0, 1, 33000000);
+static APBC_CLK(twsi1, TWSI1, 1, 33000000);
+static APBC_CLK(pwm1, PWM1, 1, 13000000);
+static APBC_CLK(pwm2, PWM2, 1, 13000000);
+static APBC_CLK(pwm3, PWM3, 1, 13000000);
+static APBC_CLK(pwm4, PWM4, 1, 13000000);
+static APBC_CLK(gpio, GPIO, 0, 13000000);
+static APBC_CLK(rtc, RTC, 8, 32768);
+
+static APMU_CLK(nand, NAND, 0x19b, 156000000);
+static APMU_CLK(u2o, USB, 0x1b, 480000000);
+
+/* device and clock bindings */
+static struct clk_lookup pxa910_clkregs[] = {
+ INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
+ INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
+ INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
+ INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
+ INIT_CLKREG(&clk_pwm1, "pxa910-pwm.0", NULL),
+ INIT_CLKREG(&clk_pwm2, "pxa910-pwm.1", NULL),
+ INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL),
+ INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL),
+ INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
+ INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
+ INIT_CLKREG(&clk_u2o, NULL, "U2OCLK"),
+ INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
+};
+
+void __init pxa910_clk_init(void)
+{
+ clkdev_add_table(ARRAY_AND_SIZE(pxa910_clkregs));
+}
diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h
index 1c9d6c1..bd45327 100644
--- a/arch/arm/mach-mmp/common.h
+++ b/arch/arm/mach-mmp/common.h
@@ -7,3 +7,6 @@
extern void __init icu_init_irq(void);
extern void __init mmp_map_io(void);
extern void mmp_restart(char, const char *);
+extern void __init pxa168_clk_init(void);
+extern void __init pxa910_clk_init(void);
+extern void __init mmp2_clk_init(void);
diff --git a/arch/arm/mach-mmp/include/mach/regs-apbc.h b/arch/arm/mach-mmp/include/mach/regs-apbc.h
index 68b0c93..ddc812f 100644
--- a/arch/arm/mach-mmp/include/mach/regs-apbc.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apbc.h
@@ -13,101 +13,6 @@
#include <mach/addr-map.h>
-/*
- * APB clock register offsets for PXA168
- */
-#define APBC_PXA168_UART1 APBC_REG(0x000)
-#define APBC_PXA168_UART2 APBC_REG(0x004)
-#define APBC_PXA168_GPIO APBC_REG(0x008)
-#define APBC_PXA168_PWM1 APBC_REG(0x00c)
-#define APBC_PXA168_PWM2 APBC_REG(0x010)
-#define APBC_PXA168_PWM3 APBC_REG(0x014)
-#define APBC_PXA168_PWM4 APBC_REG(0x018)
-#define APBC_PXA168_RTC APBC_REG(0x028)
-#define APBC_PXA168_TWSI0 APBC_REG(0x02c)
-#define APBC_PXA168_KPC APBC_REG(0x030)
-#define APBC_PXA168_TIMERS APBC_REG(0x034)
-#define APBC_PXA168_AIB APBC_REG(0x03c)
-#define APBC_PXA168_SW_JTAG APBC_REG(0x040)
-#define APBC_PXA168_ONEWIRE APBC_REG(0x048)
-#define APBC_PXA168_ASFAR APBC_REG(0x050)
-#define APBC_PXA168_ASSAR APBC_REG(0x054)
-#define APBC_PXA168_TWSI1 APBC_REG(0x06c)
-#define APBC_PXA168_UART3 APBC_REG(0x070)
-#define APBC_PXA168_AC97 APBC_REG(0x084)
-#define APBC_PXA168_SSP1 APBC_REG(0x81c)
-#define APBC_PXA168_SSP2 APBC_REG(0x820)
-#define APBC_PXA168_SSP3 APBC_REG(0x84c)
-#define APBC_PXA168_SSP4 APBC_REG(0x858)
-#define APBC_PXA168_SSP5 APBC_REG(0x85c)
-
-/*
- * APB Clock register offsets for PXA910
- */
-#define APBC_PXA910_UART0 APBC_REG(0x000)
-#define APBC_PXA910_UART1 APBC_REG(0x004)
-#define APBC_PXA910_GPIO APBC_REG(0x008)
-#define APBC_PXA910_PWM1 APBC_REG(0x00c)
-#define APBC_PXA910_PWM2 APBC_REG(0x010)
-#define APBC_PXA910_PWM3 APBC_REG(0x014)
-#define APBC_PXA910_PWM4 APBC_REG(0x018)
-#define APBC_PXA910_SSP1 APBC_REG(0x01c)
-#define APBC_PXA910_SSP2 APBC_REG(0x020)
-#define APBC_PXA910_IPC APBC_REG(0x024)
-#define APBC_PXA910_RTC APBC_REG(0x028)
-#define APBC_PXA910_TWSI0 APBC_REG(0x02c)
-#define APBC_PXA910_KPC APBC_REG(0x030)
-#define APBC_PXA910_TIMERS APBC_REG(0x034)
-#define APBC_PXA910_TBROT APBC_REG(0x038)
-#define APBC_PXA910_AIB APBC_REG(0x03c)
-#define APBC_PXA910_SW_JTAG APBC_REG(0x040)
-#define APBC_PXA910_TIMERS1 APBC_REG(0x044)
-#define APBC_PXA910_ONEWIRE APBC_REG(0x048)
-#define APBC_PXA910_SSP3 APBC_REG(0x04c)
-#define APBC_PXA910_ASFAR APBC_REG(0x050)
-#define APBC_PXA910_ASSAR APBC_REG(0x054)
-
-/*
- * APB Clock register offsets for MMP2
- */
-#define APBC_MMP2_RTC APBC_REG(0x000)
-#define APBC_MMP2_TWSI1 APBC_REG(0x004)
-#define APBC_MMP2_TWSI2 APBC_REG(0x008)
-#define APBC_MMP2_TWSI3 APBC_REG(0x00c)
-#define APBC_MMP2_TWSI4 APBC_REG(0x010)
-#define APBC_MMP2_ONEWIRE APBC_REG(0x014)
-#define APBC_MMP2_KPC APBC_REG(0x018)
-#define APBC_MMP2_TB_ROTARY APBC_REG(0x01c)
-#define APBC_MMP2_SW_JTAG APBC_REG(0x020)
-#define APBC_MMP2_TIMERS APBC_REG(0x024)
-#define APBC_MMP2_UART1 APBC_REG(0x02c)
-#define APBC_MMP2_UART2 APBC_REG(0x030)
-#define APBC_MMP2_UART3 APBC_REG(0x034)
-#define APBC_MMP2_GPIO APBC_REG(0x038)
-#define APBC_MMP2_PWM0 APBC_REG(0x03c)
-#define APBC_MMP2_PWM1 APBC_REG(0x040)
-#define APBC_MMP2_PWM2 APBC_REG(0x044)
-#define APBC_MMP2_PWM3 APBC_REG(0x048)
-#define APBC_MMP2_SSP0 APBC_REG(0x04c)
-#define APBC_MMP2_SSP1 APBC_REG(0x050)
-#define APBC_MMP2_SSP2 APBC_REG(0x054)
-#define APBC_MMP2_SSP3 APBC_REG(0x058)
-#define APBC_MMP2_SSP4 APBC_REG(0x05c)
-#define APBC_MMP2_SSP5 APBC_REG(0x060)
-#define APBC_MMP2_AIB APBC_REG(0x064)
-#define APBC_MMP2_ASFAR APBC_REG(0x068)
-#define APBC_MMP2_ASSAR APBC_REG(0x06c)
-#define APBC_MMP2_USIM APBC_REG(0x070)
-#define APBC_MMP2_MPMU APBC_REG(0x074)
-#define APBC_MMP2_IPC APBC_REG(0x078)
-#define APBC_MMP2_TWSI5 APBC_REG(0x07c)
-#define APBC_MMP2_TWSI6 APBC_REG(0x080)
-#define APBC_MMP2_TWSI_INTSTS APBC_REG(0x084)
-#define APBC_MMP2_UART4 APBC_REG(0x088)
-#define APBC_MMP2_RIPC APBC_REG(0x08c)
-#define APBC_MMP2_THSENS1 APBC_REG(0x090) /* Thermal Sensor */
-#define APBC_MMP2_THSENS_INTSTS APBC_REG(0x0a4)
-
/* Common APB clock register bit definitions */
#define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */
#define APBC_FNCLK (1 << 1) /* Functional Clock Enable */
diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h b/arch/arm/mach-mmp/include/mach/regs-apmu.h
index 7af8deb..93c8d0e 100644
--- a/arch/arm/mach-mmp/include/mach/regs-apmu.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h
@@ -13,21 +13,6 @@
#include <mach/addr-map.h>
-/* Clock Reset Control */
-#define APMU_IRE APMU_REG(0x048)
-#define APMU_LCD APMU_REG(0x04c)
-#define APMU_CCIC APMU_REG(0x050)
-#define APMU_SDH0 APMU_REG(0x054)
-#define APMU_SDH1 APMU_REG(0x058)
-#define APMU_USB APMU_REG(0x05c)
-#define APMU_NAND APMU_REG(0x060)
-#define APMU_DMA APMU_REG(0x064)
-#define APMU_GEU APMU_REG(0x068)
-#define APMU_BUS APMU_REG(0x06c)
-#define APMU_SDH2 APMU_REG(0x0e8)
-#define APMU_SDH3 APMU_REG(0x0ec)
-#define APMU_ETH APMU_REG(0x0fc)
-
#define APMU_FNCLK_EN (1 << 4)
#define APMU_AXICLK_EN (1 << 3)
#define APMU_FNRST_DIS (1 << 1)
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index c709a24..c2ce3d0 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -20,7 +20,6 @@
#include <asm/mach/time.h>
#include <mach/addr-map.h>
#include <mach/regs-apbc.h>
-#include <mach/regs-apmu.h>
#include <mach/cputype.h>
#include <mach/irqs.h>
#include <mach/dma.h>
@@ -29,7 +28,6 @@
#include <mach/mmp2.h>
#include "common.h"
-#include "clock.h"
#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000)
@@ -98,67 +96,6 @@
mmp2_init_icu();
}
-static void sdhc_clk_enable(struct clk *clk)
-{
- uint32_t clk_rst;
-
- clk_rst = __raw_readl(clk->clk_rst);
- clk_rst |= clk->enable_val;
- __raw_writel(clk_rst, clk->clk_rst);
-}
-
-static void sdhc_clk_disable(struct clk *clk)
-{
- uint32_t clk_rst;
-
- clk_rst = __raw_readl(clk->clk_rst);
- clk_rst &= ~clk->enable_val;
- __raw_writel(clk_rst, clk->clk_rst);
-}
-
-struct clkops sdhc_clk_ops = {
- .enable = sdhc_clk_enable,
- .disable = sdhc_clk_disable,
-};
-
-/* APB peripheral clocks */
-static APBC_CLK(uart1, MMP2_UART1, 1, 26000000);
-static APBC_CLK(uart2, MMP2_UART2, 1, 26000000);
-static APBC_CLK(uart3, MMP2_UART3, 1, 26000000);
-static APBC_CLK(uart4, MMP2_UART4, 1, 26000000);
-static APBC_CLK(twsi1, MMP2_TWSI1, 0, 26000000);
-static APBC_CLK(twsi2, MMP2_TWSI2, 0, 26000000);
-static APBC_CLK(twsi3, MMP2_TWSI3, 0, 26000000);
-static APBC_CLK(twsi4, MMP2_TWSI4, 0, 26000000);
-static APBC_CLK(twsi5, MMP2_TWSI5, 0, 26000000);
-static APBC_CLK(twsi6, MMP2_TWSI6, 0, 26000000);
-static APBC_CLK(gpio, MMP2_GPIO, 0, 26000000);
-
-static APMU_CLK(nand, NAND, 0xbf, 100000000);
-static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops);
-static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops);
-static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops);
-static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops);
-
-static struct clk_lookup mmp2_clkregs[] = {
- INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
- INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
- INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
- INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL),
- INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL),
- INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL),
- INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL),
- INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL),
- INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
- INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
- INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
- INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
- INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"),
- INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"),
- INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"),
- INIT_CLKREG(&clk_sdh3, "sdhci-pxav3.3", "PXA-SDHCLK"),
-};
-
static int __init mmp2_init(void)
{
if (cpu_is_mmp2()) {
@@ -168,25 +105,27 @@
mfp_init_base(MFPR_VIRT_BASE);
mfp_init_addr(mmp2_addr_map);
pxa_init_dma(IRQ_MMP2_DMA_RIQ, 16);
- clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs));
+ mmp2_clk_init();
}
return 0;
}
postcore_initcall(mmp2_init);
+#define APBC_TIMERS APBC_REG(0x024)
+
static void __init mmp2_timer_init(void)
{
unsigned long clk_rst;
- __raw_writel(APBC_APBCLK | APBC_RST, APBC_MMP2_TIMERS);
+ __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
/*
* enable bus/functional clock, enable 6.5MHz (divider 4),
* release reset
*/
clk_rst = APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1);
- __raw_writel(clk_rst, APBC_MMP2_TIMERS);
+ __raw_writel(clk_rst, APBC_TIMERS);
timer_init(IRQ_MMP2_TIMER1);
}
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index 62d787c..b7f074f 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -18,8 +18,8 @@
#include <asm/mach/time.h>
#include <asm/system_misc.h>
-#include <mach/addr-map.h>
#include <mach/cputype.h>
+#include <mach/addr-map.h>
#include <mach/regs-apbc.h>
#include <mach/regs-apmu.h>
#include <mach/irqs.h>
@@ -50,62 +50,13 @@
icu_init_irq();
}
-/* APB peripheral clocks */
-static APBC_CLK(uart1, PXA168_UART1, 1, 14745600);
-static APBC_CLK(uart2, PXA168_UART2, 1, 14745600);
-static APBC_CLK(uart3, PXA168_UART3, 1, 14745600);
-static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000);
-static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000);
-static APBC_CLK(pwm1, PXA168_PWM1, 1, 13000000);
-static APBC_CLK(pwm2, PXA168_PWM2, 1, 13000000);
-static APBC_CLK(pwm3, PXA168_PWM3, 1, 13000000);
-static APBC_CLK(pwm4, PXA168_PWM4, 1, 13000000);
-static APBC_CLK(ssp1, PXA168_SSP1, 4, 0);
-static APBC_CLK(ssp2, PXA168_SSP2, 4, 0);
-static APBC_CLK(ssp3, PXA168_SSP3, 4, 0);
-static APBC_CLK(ssp4, PXA168_SSP4, 4, 0);
-static APBC_CLK(ssp5, PXA168_SSP5, 4, 0);
-static APBC_CLK(gpio, PXA168_GPIO, 0, 13000000);
-static APBC_CLK(keypad, PXA168_KPC, 0, 32000);
-static APBC_CLK(rtc, PXA168_RTC, 8, 32768);
-
-static APMU_CLK(nand, NAND, 0x19b, 156000000);
-static APMU_CLK(lcd, LCD, 0x7f, 312000000);
-static APMU_CLK(eth, ETH, 0x09, 0);
-static APMU_CLK(usb, USB, 0x12, 0);
-
-/* device and clock bindings */
-static struct clk_lookup pxa168_clkregs[] = {
- INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
- INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
- INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
- INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
- INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
- INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL),
- INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL),
- INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL),
- INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL),
- INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL),
- INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL),
- INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL),
- INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL),
- INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL),
- INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
- INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
- INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
- INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
- INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
- INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"),
- INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
-};
-
static int __init pxa168_init(void)
{
if (cpu_is_pxa168()) {
mfp_init_base(MFPR_VIRT_BASE);
mfp_init_addr(pxa168_mfp_addr_map);
pxa_init_dma(IRQ_PXA168_DMA_INT0, 32);
- clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs));
+ pxa168_clk_init();
}
return 0;
@@ -114,6 +65,7 @@
/* system timer - clock enabled, 3.25MHz */
#define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3))
+#define APBC_TIMERS APBC_REG(0x34)
static void __init pxa168_timer_init(void)
{
@@ -121,10 +73,10 @@
* ourselves instead of using clk_* API. Clock rate is defined
* by APBC_TIMERS_CLK_RST (3.25MHz) and enabled free-running
*/
- __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA168_TIMERS);
+ __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
/* 3.25MHz, bus/functional clock enabled, release reset */
- __raw_writel(TIMER_CLK_RST, APBC_PXA168_TIMERS);
+ __raw_writel(TIMER_CLK_RST, APBC_TIMERS);
timer_init(IRQ_PXA168_TIMER1);
}
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index 6da52e9..7d84521 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -17,7 +17,6 @@
#include <asm/mach/time.h>
#include <mach/addr-map.h>
#include <mach/regs-apbc.h>
-#include <mach/regs-apmu.h>
#include <mach/cputype.h>
#include <mach/irqs.h>
#include <mach/dma.h>
@@ -25,7 +24,6 @@
#include <mach/devices.h>
#include "common.h"
-#include "clock.h"
#define MFPR_VIRT_BASE (APB_VIRT_BASE + 0x1e000)
@@ -82,44 +80,13 @@
icu_init_irq();
}
-/* APB peripheral clocks */
-static APBC_CLK(uart1, PXA910_UART0, 1, 14745600);
-static APBC_CLK(uart2, PXA910_UART1, 1, 14745600);
-static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000);
-static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000);
-static APBC_CLK(pwm1, PXA910_PWM1, 1, 13000000);
-static APBC_CLK(pwm2, PXA910_PWM2, 1, 13000000);
-static APBC_CLK(pwm3, PXA910_PWM3, 1, 13000000);
-static APBC_CLK(pwm4, PXA910_PWM4, 1, 13000000);
-static APBC_CLK(gpio, PXA910_GPIO, 0, 13000000);
-static APBC_CLK(rtc, PXA910_RTC, 8, 32768);
-
-static APMU_CLK(nand, NAND, 0x19b, 156000000);
-static APMU_CLK(u2o, USB, 0x1b, 480000000);
-
-/* device and clock bindings */
-static struct clk_lookup pxa910_clkregs[] = {
- INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
- INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
- INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
- INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
- INIT_CLKREG(&clk_pwm1, "pxa910-pwm.0", NULL),
- INIT_CLKREG(&clk_pwm2, "pxa910-pwm.1", NULL),
- INIT_CLKREG(&clk_pwm3, "pxa910-pwm.2", NULL),
- INIT_CLKREG(&clk_pwm4, "pxa910-pwm.3", NULL),
- INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
- INIT_CLKREG(&clk_gpio, "pxa-gpio", NULL),
- INIT_CLKREG(&clk_u2o, NULL, "U2OCLK"),
- INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
-};
-
static int __init pxa910_init(void)
{
if (cpu_is_pxa910()) {
mfp_init_base(MFPR_VIRT_BASE);
mfp_init_addr(pxa910_mfp_addr_map);
pxa_init_dma(IRQ_PXA910_DMA_INT0, 32);
- clkdev_add_table(ARRAY_AND_SIZE(pxa910_clkregs));
+ pxa910_clk_init();
}
return 0;
@@ -128,12 +95,13 @@
/* system timer - clock enabled, 3.25MHz */
#define TIMER_CLK_RST (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3))
+#define APBC_TIMERS APBC_REG(0x34)
static void __init pxa910_timer_init(void)
{
/* reset and configure */
- __raw_writel(APBC_APBCLK | APBC_RST, APBC_PXA910_TIMERS);
- __raw_writel(TIMER_CLK_RST, APBC_PXA910_TIMERS);
+ __raw_writel(APBC_APBCLK | APBC_RST, APBC_TIMERS);
+ __raw_writel(TIMER_CLK_RST, APBC_TIMERS);
timer_init(IRQ_PXA910_AP1_TIMER1);
}
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index 4ad3969..6a6c197 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -1,11 +1,11 @@
-obj-y += io.o idle.o timer.o
+obj-y += io.o timer.o
obj-y += clock.o
obj-$(CONFIG_DEBUG_FS) += clock-debug.o
obj-$(CONFIG_MSM_VIC) += irq-vic.o
obj-$(CONFIG_MSM_IOMMU) += devices-iommu.o
-obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o acpuclock-arm11.o
+obj-$(CONFIG_ARCH_MSM7X00A) += dma.o irq.o
obj-$(CONFIG_ARCH_MSM7X30) += dma.o
obj-$(CONFIG_ARCH_QSD8X50) += dma.o sirc.o
diff --git a/arch/arm/mach-msm/acpuclock-arm11.c b/arch/arm/mach-msm/acpuclock-arm11.c
deleted file mode 100644
index 805d4ee..0000000
--- a/arch/arm/mach-msm/acpuclock-arm11.c
+++ /dev/null
@@ -1,525 +0,0 @@
-/* arch/arm/mach-msm/acpuclock.c
- *
- * MSM architecture clock driver
- *
- * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2007 QUALCOMM Incorporated
- * Author: San Mehat <san@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/string.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/cpufreq.h>
-#include <linux/mutex.h>
-#include <linux/io.h>
-#include <mach/board.h>
-#include <mach/msm_iomap.h>
-
-#include "proc_comm.h"
-#include "acpuclock.h"
-
-
-#define A11S_CLK_CNTL_ADDR (MSM_CSR_BASE + 0x100)
-#define A11S_CLK_SEL_ADDR (MSM_CSR_BASE + 0x104)
-#define A11S_VDD_SVS_PLEVEL_ADDR (MSM_CSR_BASE + 0x124)
-
-/*
- * ARM11 clock configuration for specific ACPU speeds
- */
-
-#define ACPU_PLL_TCXO -1
-#define ACPU_PLL_0 0
-#define ACPU_PLL_1 1
-#define ACPU_PLL_2 2
-#define ACPU_PLL_3 3
-
-#define PERF_SWITCH_DEBUG 0
-#define PERF_SWITCH_STEP_DEBUG 0
-
-struct clock_state
-{
- struct clkctl_acpu_speed *current_speed;
- struct mutex lock;
- uint32_t acpu_switch_time_us;
- uint32_t max_speed_delta_khz;
- uint32_t vdd_switch_time_us;
- unsigned long power_collapse_khz;
- unsigned long wait_for_irq_khz;
-};
-
-static struct clk *ebi1_clk;
-static struct clock_state drv_state = { 0 };
-
-static void __init acpuclk_init(void);
-
-/* MSM7201A Levels 3-6 all correspond to 1.2V, level 7 corresponds to 1.325V. */
-enum {
- VDD_0 = 0,
- VDD_1 = 1,
- VDD_2 = 2,
- VDD_3 = 3,
- VDD_4 = 3,
- VDD_5 = 3,
- VDD_6 = 3,
- VDD_7 = 7,
- VDD_END
-};
-
-struct clkctl_acpu_speed {
- unsigned int a11clk_khz;
- int pll;
- unsigned int a11clk_src_sel;
- unsigned int a11clk_src_div;
- unsigned int ahbclk_khz;
- unsigned int ahbclk_div;
- int vdd;
- unsigned int axiclk_khz;
- unsigned long lpj; /* loops_per_jiffy */
-/* Index in acpu_freq_tbl[] for steppings. */
- short down;
- short up;
-};
-
-/*
- * ACPU speed table. Complete table is shown but certain speeds are commented
- * out to optimized speed switching. Initialize loops_per_jiffy to 0.
- *
- * Table stepping up/down is optimized for 256mhz jumps while staying on the
- * same PLL.
- */
-#if (0)
-static struct clkctl_acpu_speed acpu_freq_tbl[] = {
- { 19200, ACPU_PLL_TCXO, 0, 0, 19200, 0, VDD_0, 30720, 0, 0, 8 },
- { 61440, ACPU_PLL_0, 4, 3, 61440, 0, VDD_0, 30720, 0, 0, 8 },
- { 81920, ACPU_PLL_0, 4, 2, 40960, 1, VDD_0, 61440, 0, 0, 8 },
- { 96000, ACPU_PLL_1, 1, 7, 48000, 1, VDD_0, 61440, 0, 0, 9 },
- { 122880, ACPU_PLL_0, 4, 1, 61440, 1, VDD_3, 61440, 0, 0, 8 },
- { 128000, ACPU_PLL_1, 1, 5, 64000, 1, VDD_3, 61440, 0, 0, 12 },
- { 176000, ACPU_PLL_2, 2, 5, 88000, 1, VDD_3, 61440, 0, 0, 11 },
- { 192000, ACPU_PLL_1, 1, 3, 64000, 2, VDD_3, 61440, 0, 0, 12 },
- { 245760, ACPU_PLL_0, 4, 0, 81920, 2, VDD_4, 61440, 0, 0, 12 },
- { 256000, ACPU_PLL_1, 1, 2, 128000, 2, VDD_5, 128000, 0, 0, 12 },
- { 264000, ACPU_PLL_2, 2, 3, 88000, 2, VDD_5, 128000, 0, 6, 13 },
- { 352000, ACPU_PLL_2, 2, 2, 88000, 3, VDD_5, 128000, 0, 6, 13 },
- { 384000, ACPU_PLL_1, 1, 1, 128000, 2, VDD_6, 128000, 0, 5, -1 },
- { 528000, ACPU_PLL_2, 2, 1, 132000, 3, VDD_7, 128000, 0, 11, -1 },
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
-};
-#else /* Table of freq we currently use. */
-static struct clkctl_acpu_speed acpu_freq_tbl[] = {
- { 19200, ACPU_PLL_TCXO, 0, 0, 19200, 0, VDD_0, 30720, 0, 0, 4 },
- { 122880, ACPU_PLL_0, 4, 1, 61440, 1, VDD_3, 61440, 0, 0, 4 },
- { 128000, ACPU_PLL_1, 1, 5, 64000, 1, VDD_3, 61440, 0, 0, 6 },
- { 176000, ACPU_PLL_2, 2, 5, 88000, 1, VDD_3, 61440, 0, 0, 5 },
- { 245760, ACPU_PLL_0, 4, 0, 81920, 2, VDD_4, 61440, 0, 0, 5 },
- { 352000, ACPU_PLL_2, 2, 2, 88000, 3, VDD_5, 128000, 0, 3, 7 },
- { 384000, ACPU_PLL_1, 1, 1, 128000, 2, VDD_6, 128000, 0, 2, -1 },
- { 528000, ACPU_PLL_2, 2, 1, 132000, 3, VDD_7, 128000, 0, 5, -1 },
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
-};
-#endif
-
-
-#ifdef CONFIG_CPU_FREQ_TABLE
-static struct cpufreq_frequency_table freq_table[] = {
- { 0, 122880 },
- { 1, 128000 },
- { 2, 245760 },
- { 3, 384000 },
- { 4, 528000 },
- { 5, CPUFREQ_TABLE_END },
-};
-#endif
-
-static int pc_pll_request(unsigned id, unsigned on)
-{
- int res;
- on = !!on;
-
-#if PERF_SWITCH_DEBUG
- if (on)
- printk(KERN_DEBUG "Enabling PLL %d\n", id);
- else
- printk(KERN_DEBUG "Disabling PLL %d\n", id);
-#endif
-
- res = msm_proc_comm(PCOM_CLKCTL_RPC_PLL_REQUEST, &id, &on);
- if (res < 0)
- return res;
-
-#if PERF_SWITCH_DEBUG
- if (on)
- printk(KERN_DEBUG "PLL %d enabled\n", id);
- else
- printk(KERN_DEBUG "PLL %d disabled\n", id);
-#endif
- return res;
-}
-
-
-/*----------------------------------------------------------------------------
- * ARM11 'owned' clock control
- *---------------------------------------------------------------------------*/
-
-unsigned long acpuclk_power_collapse(void) {
- int ret = acpuclk_get_rate();
- ret *= 1000;
- if (ret > drv_state.power_collapse_khz)
- acpuclk_set_rate(drv_state.power_collapse_khz, 1);
- return ret;
-}
-
-unsigned long acpuclk_get_wfi_rate(void)
-{
- return drv_state.wait_for_irq_khz;
-}
-
-unsigned long acpuclk_wait_for_irq(void) {
- int ret = acpuclk_get_rate();
- ret *= 1000;
- if (ret > drv_state.wait_for_irq_khz)
- acpuclk_set_rate(drv_state.wait_for_irq_khz, 1);
- return ret;
-}
-
-static int acpuclk_set_vdd_level(int vdd)
-{
- uint32_t current_vdd;
-
- current_vdd = readl(A11S_VDD_SVS_PLEVEL_ADDR) & 0x07;
-
-#if PERF_SWITCH_DEBUG
- printk(KERN_DEBUG "acpuclock: Switching VDD from %u -> %d\n",
- current_vdd, vdd);
-#endif
- writel((1 << 7) | (vdd << 3), A11S_VDD_SVS_PLEVEL_ADDR);
- udelay(drv_state.vdd_switch_time_us);
- if ((readl(A11S_VDD_SVS_PLEVEL_ADDR) & 0x7) != vdd) {
-#if PERF_SWITCH_DEBUG
- printk(KERN_ERR "acpuclock: VDD set failed\n");
-#endif
- return -EIO;
- }
-
-#if PERF_SWITCH_DEBUG
- printk(KERN_DEBUG "acpuclock: VDD switched\n");
-#endif
- return 0;
-}
-
-/* Set proper dividers for the given clock speed. */
-static void acpuclk_set_div(const struct clkctl_acpu_speed *hunt_s) {
- uint32_t reg_clkctl, reg_clksel, clk_div;
-
- /* AHB_CLK_DIV */
- clk_div = (readl(A11S_CLK_SEL_ADDR) >> 1) & 0x03;
- /*
- * If the new clock divider is higher than the previous, then
- * program the divider before switching the clock
- */
- if (hunt_s->ahbclk_div > clk_div) {
- reg_clksel = readl(A11S_CLK_SEL_ADDR);
- reg_clksel &= ~(0x3 << 1);
- reg_clksel |= (hunt_s->ahbclk_div << 1);
- writel(reg_clksel, A11S_CLK_SEL_ADDR);
- }
- if ((readl(A11S_CLK_SEL_ADDR) & 0x01) == 0) {
- /* SRC0 */
-
- /* Program clock source */
- reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
- reg_clkctl &= ~(0x07 << 4);
- reg_clkctl |= (hunt_s->a11clk_src_sel << 4);
- writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
-
- /* Program clock divider */
- reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
- reg_clkctl &= ~0xf;
- reg_clkctl |= hunt_s->a11clk_src_div;
- writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
-
- /* Program clock source selection */
- reg_clksel = readl(A11S_CLK_SEL_ADDR);
- reg_clksel |= 1; /* CLK_SEL_SRC1NO == SRC1 */
- writel(reg_clksel, A11S_CLK_SEL_ADDR);
- } else {
- /* SRC1 */
-
- /* Program clock source */
- reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
- reg_clkctl &= ~(0x07 << 12);
- reg_clkctl |= (hunt_s->a11clk_src_sel << 12);
- writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
-
- /* Program clock divider */
- reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
- reg_clkctl &= ~(0xf << 8);
- reg_clkctl |= (hunt_s->a11clk_src_div << 8);
- writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
-
- /* Program clock source selection */
- reg_clksel = readl(A11S_CLK_SEL_ADDR);
- reg_clksel &= ~1; /* CLK_SEL_SRC1NO == SRC0 */
- writel(reg_clksel, A11S_CLK_SEL_ADDR);
- }
-
- /*
- * If the new clock divider is lower than the previous, then
- * program the divider after switching the clock
- */
- if (hunt_s->ahbclk_div < clk_div) {
- reg_clksel = readl(A11S_CLK_SEL_ADDR);
- reg_clksel &= ~(0x3 << 1);
- reg_clksel |= (hunt_s->ahbclk_div << 1);
- writel(reg_clksel, A11S_CLK_SEL_ADDR);
- }
-}
-
-int acpuclk_set_rate(unsigned long rate, int for_power_collapse)
-{
- uint32_t reg_clkctl;
- struct clkctl_acpu_speed *cur_s, *tgt_s, *strt_s;
- int rc = 0;
- unsigned int plls_enabled = 0, pll;
-
- strt_s = cur_s = drv_state.current_speed;
-
- WARN_ONCE(cur_s == NULL, "acpuclk_set_rate: not initialized\n");
- if (cur_s == NULL)
- return -ENOENT;
-
- if (rate == (cur_s->a11clk_khz * 1000))
- return 0;
-
- for (tgt_s = acpu_freq_tbl; tgt_s->a11clk_khz != 0; tgt_s++) {
- if (tgt_s->a11clk_khz == (rate / 1000))
- break;
- }
-
- if (tgt_s->a11clk_khz == 0)
- return -EINVAL;
-
- /* Choose the highest speed speed at or below 'rate' with same PLL. */
- if (for_power_collapse && tgt_s->a11clk_khz < cur_s->a11clk_khz) {
- while (tgt_s->pll != ACPU_PLL_TCXO && tgt_s->pll != cur_s->pll)
- tgt_s--;
- }
-
- if (strt_s->pll != ACPU_PLL_TCXO)
- plls_enabled |= 1 << strt_s->pll;
-
- if (!for_power_collapse) {
- mutex_lock(&drv_state.lock);
- if (strt_s->pll != tgt_s->pll && tgt_s->pll != ACPU_PLL_TCXO) {
- rc = pc_pll_request(tgt_s->pll, 1);
- if (rc < 0) {
- pr_err("PLL%d enable failed (%d)\n",
- tgt_s->pll, rc);
- goto out;
- }
- plls_enabled |= 1 << tgt_s->pll;
- }
- /* Increase VDD if needed. */
- if (tgt_s->vdd > cur_s->vdd) {
- if ((rc = acpuclk_set_vdd_level(tgt_s->vdd)) < 0) {
- printk(KERN_ERR "Unable to switch ACPU vdd\n");
- goto out;
- }
- }
- }
-
- /* Set wait states for CPU between frequency changes */
- reg_clkctl = readl(A11S_CLK_CNTL_ADDR);
- reg_clkctl |= (100 << 16); /* set WT_ST_CNT */
- writel(reg_clkctl, A11S_CLK_CNTL_ADDR);
-
-#if PERF_SWITCH_DEBUG
- printk(KERN_INFO "acpuclock: Switching from ACPU rate %u -> %u\n",
- strt_s->a11clk_khz * 1000, tgt_s->a11clk_khz * 1000);
-#endif
-
- while (cur_s != tgt_s) {
- /*
- * Always jump to target freq if within 256mhz, regulardless of
- * PLL. If differnece is greater, use the predefinied
- * steppings in the table.
- */
- int d = abs((int)(cur_s->a11clk_khz - tgt_s->a11clk_khz));
- if (d > drv_state.max_speed_delta_khz) {
- /* Step up or down depending on target vs current. */
- int clk_index = tgt_s->a11clk_khz > cur_s->a11clk_khz ?
- cur_s->up : cur_s->down;
- if (clk_index < 0) { /* This should not happen. */
- printk(KERN_ERR "cur:%u target: %u\n",
- cur_s->a11clk_khz, tgt_s->a11clk_khz);
- rc = -EINVAL;
- goto out;
- }
- cur_s = &acpu_freq_tbl[clk_index];
- } else {
- cur_s = tgt_s;
- }
-#if PERF_SWITCH_STEP_DEBUG
- printk(KERN_DEBUG "%s: STEP khz = %u, pll = %d\n",
- __FUNCTION__, cur_s->a11clk_khz, cur_s->pll);
-#endif
- if (!for_power_collapse&& cur_s->pll != ACPU_PLL_TCXO
- && !(plls_enabled & (1 << cur_s->pll))) {
- rc = pc_pll_request(cur_s->pll, 1);
- if (rc < 0) {
- pr_err("PLL%d enable failed (%d)\n",
- cur_s->pll, rc);
- goto out;
- }
- plls_enabled |= 1 << cur_s->pll;
- }
-
- acpuclk_set_div(cur_s);
- drv_state.current_speed = cur_s;
- /* Re-adjust lpj for the new clock speed. */
- loops_per_jiffy = cur_s->lpj;
- udelay(drv_state.acpu_switch_time_us);
- }
-
- /* Nothing else to do for power collapse. */
- if (for_power_collapse)
- return 0;
-
- /* Disable PLLs we are not using anymore. */
- plls_enabled &= ~(1 << tgt_s->pll);
- for (pll = ACPU_PLL_0; pll <= ACPU_PLL_2; pll++)
- if (plls_enabled & (1 << pll)) {
- rc = pc_pll_request(pll, 0);
- if (rc < 0) {
- pr_err("PLL%d disable failed (%d)\n", pll, rc);
- goto out;
- }
- }
-
- /* Change the AXI bus frequency if we can. */
- if (strt_s->axiclk_khz != tgt_s->axiclk_khz) {
- rc = clk_set_rate(ebi1_clk, tgt_s->axiclk_khz * 1000);
- if (rc < 0)
- pr_err("Setting AXI min rate failed!\n");
- }
-
- /* Drop VDD level if we can. */
- if (tgt_s->vdd < strt_s->vdd) {
- if (acpuclk_set_vdd_level(tgt_s->vdd) < 0)
- printk(KERN_ERR "acpuclock: Unable to drop ACPU vdd\n");
- }
-
-#if PERF_SWITCH_DEBUG
- printk(KERN_DEBUG "%s: ACPU speed change complete\n", __FUNCTION__);
-#endif
-out:
- if (!for_power_collapse)
- mutex_unlock(&drv_state.lock);
- return rc;
-}
-
-static void __init acpuclk_init(void)
-{
- struct clkctl_acpu_speed *speed;
- uint32_t div, sel;
- int rc;
-
- /*
- * Determine the rate of ACPU clock
- */
-
- if (!(readl(A11S_CLK_SEL_ADDR) & 0x01)) { /* CLK_SEL_SRC1N0 */
- /* CLK_SRC0_SEL */
- sel = (readl(A11S_CLK_CNTL_ADDR) >> 12) & 0x7;
- /* CLK_SRC0_DIV */
- div = (readl(A11S_CLK_CNTL_ADDR) >> 8) & 0x0f;
- } else {
- /* CLK_SRC1_SEL */
- sel = (readl(A11S_CLK_CNTL_ADDR) >> 4) & 0x07;
- /* CLK_SRC1_DIV */
- div = readl(A11S_CLK_CNTL_ADDR) & 0x0f;
- }
-
- for (speed = acpu_freq_tbl; speed->a11clk_khz != 0; speed++) {
- if (speed->a11clk_src_sel == sel
- && (speed->a11clk_src_div == div))
- break;
- }
- if (speed->a11clk_khz == 0) {
- printk(KERN_WARNING "Warning - ACPU clock reports invalid speed\n");
- return;
- }
-
- drv_state.current_speed = speed;
-
- rc = clk_set_rate(ebi1_clk, speed->axiclk_khz * 1000);
- if (rc < 0)
- pr_err("Setting AXI min rate failed!\n");
-
- printk(KERN_INFO "ACPU running at %d KHz\n", speed->a11clk_khz);
-}
-
-unsigned long acpuclk_get_rate(void)
-{
- WARN_ONCE(drv_state.current_speed == NULL,
- "acpuclk_get_rate: not initialized\n");
- if (drv_state.current_speed)
- return drv_state.current_speed->a11clk_khz;
- else
- return 0;
-}
-
-uint32_t acpuclk_get_switch_time(void)
-{
- return drv_state.acpu_switch_time_us;
-}
-
-/*----------------------------------------------------------------------------
- * Clock driver initialization
- *---------------------------------------------------------------------------*/
-
-/* Initialize the lpj field in the acpu_freq_tbl. */
-static void __init lpj_init(void)
-{
- int i;
- const struct clkctl_acpu_speed *base_clk = drv_state.current_speed;
- for (i = 0; acpu_freq_tbl[i].a11clk_khz; i++) {
- acpu_freq_tbl[i].lpj = cpufreq_scale(loops_per_jiffy,
- base_clk->a11clk_khz,
- acpu_freq_tbl[i].a11clk_khz);
- }
-}
-
-void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *clkdata)
-{
- pr_info("acpu_clock_init()\n");
-
- ebi1_clk = clk_get(NULL, "ebi1_clk");
-
- mutex_init(&drv_state.lock);
- drv_state.acpu_switch_time_us = clkdata->acpu_switch_time_us;
- drv_state.max_speed_delta_khz = clkdata->max_speed_delta_khz;
- drv_state.vdd_switch_time_us = clkdata->vdd_switch_time_us;
- drv_state.power_collapse_khz = clkdata->power_collapse_khz;
- drv_state.wait_for_irq_khz = clkdata->wait_for_irq_khz;
- acpuclk_init();
- lpj_init();
-#ifdef CONFIG_CPU_FREQ_TABLE
- cpufreq_frequency_table_get_attr(freq_table, smp_processor_id());
-#endif
-}
diff --git a/arch/arm/mach-msm/acpuclock.h b/arch/arm/mach-msm/acpuclock.h
deleted file mode 100644
index 415de2e..0000000
--- a/arch/arm/mach-msm/acpuclock.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* arch/arm/mach-msm/acpuclock.h
- *
- * MSM architecture clock driver header
- *
- * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2007 QUALCOMM Incorporated
- * Author: San Mehat <san@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ARCH_ARM_MACH_MSM_ACPUCLOCK_H
-#define __ARCH_ARM_MACH_MSM_ACPUCLOCK_H
-
-int acpuclk_set_rate(unsigned long rate, int for_power_collapse);
-unsigned long acpuclk_get_rate(void);
-uint32_t acpuclk_get_switch_time(void);
-unsigned long acpuclk_wait_for_irq(void);
-unsigned long acpuclk_power_collapse(void);
-unsigned long acpuclk_get_wfi_rate(void);
-
-
-#endif
-
diff --git a/arch/arm/mach-msm/board-mahimahi.c b/arch/arm/mach-msm/board-mahimahi.c
index cf1f89a..df00bc0 100644
--- a/arch/arm/mach-msm/board-mahimahi.c
+++ b/arch/arm/mach-msm/board-mahimahi.c
@@ -30,7 +30,6 @@
#include <mach/board.h>
#include <mach/hardware.h>
-#include <mach/system.h>
#include "board-mahimahi.h"
#include "devices.h"
diff --git a/arch/arm/mach-msm/board-msm7x27.c b/arch/arm/mach-msm/board-msm7x27.c
deleted file mode 100644
index 451ab1d..0000000
--- a/arch/arm/mach-msm/board-msm7x27.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/gpio.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/input.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/power_supply.h>
-
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/flash.h>
-#include <asm/setup.h>
-#ifdef CONFIG_CACHE_L2X0
-#include <asm/hardware/cache-l2x0.h>
-#endif
-
-#include <mach/vreg.h>
-#include <mach/mpp.h>
-#include <mach/board.h>
-#include <mach/msm_iomap.h>
-
-#include <linux/mtd/nand.h>
-#include <linux/mtd/partitions.h>
-
-#include "devices.h"
-#include "socinfo.h"
-#include "clock.h"
-
-static struct resource smc91x_resources[] = {
- [0] = {
- .start = 0x9C004300,
- .end = 0x9C0043ff,
- .flags = IORESOURCE_MEM,
- },
- [1] = {
- .start = MSM_GPIO_TO_INT(132),
- .end = MSM_GPIO_TO_INT(132),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device smc91x_device = {
- .name = "smc91x",
- .id = 0,
- .num_resources = ARRAY_SIZE(smc91x_resources),
- .resource = smc91x_resources,
-};
-
-static struct platform_device *devices[] __initdata = {
- &msm_device_uart3,
- &msm_device_smd,
- &msm_device_dmov,
- &msm_device_nand,
- &smc91x_device,
-};
-
-extern struct sys_timer msm_timer;
-
-static void __init msm7x2x_init_irq(void)
-{
- msm_init_irq();
-}
-
-static void __init msm7x2x_init(void)
-{
- if (socinfo_init() < 0)
- BUG();
-
- if (machine_is_msm7x25_ffa() || machine_is_msm7x27_ffa()) {
- smc91x_resources[0].start = 0x98000300;
- smc91x_resources[0].end = 0x980003ff;
- smc91x_resources[1].start = MSM_GPIO_TO_INT(85);
- smc91x_resources[1].end = MSM_GPIO_TO_INT(85);
- if (gpio_tlmm_config(GPIO_CFG(85, 0,
- GPIO_INPUT,
- GPIO_PULL_DOWN,
- GPIO_2MA),
- GPIO_ENABLE)) {
- printk(KERN_ERR
- "%s: Err: Config GPIO-85 INT\n",
- __func__);
- }
- }
-
- platform_add_devices(devices, ARRAY_SIZE(devices));
-}
-
-static void __init msm7x2x_map_io(void)
-{
- msm_map_common_io();
- /* Technically dependent on the SoC but using machine_is
- * macros since socinfo is not available this early and there
- * are plans to restructure the code which will eliminate the
- * need for socinfo.
- */
- if (machine_is_msm7x27_surf() || machine_is_msm7x27_ffa())
- msm_clock_init(msm_clocks_7x27, msm_num_clocks_7x27);
-
- if (machine_is_msm7x25_surf() || machine_is_msm7x25_ffa())
- msm_clock_init(msm_clocks_7x25, msm_num_clocks_7x25);
-
-#ifdef CONFIG_CACHE_L2X0
- if (machine_is_msm7x27_surf() || machine_is_msm7x27_ffa()) {
- /* 7x27 has 256KB L2 cache:
- 64Kb/Way and 4-Way Associativity;
- R/W latency: 3 cycles;
- evmon/parity/share disabled. */
- l2x0_init(MSM_L2CC_BASE, 0x00068012, 0xfe000000);
- }
-#endif
-}
-
-static void __init msm7x2x_init_late(void)
-{
- smd_debugfs_init();
-}
-
-MACHINE_START(MSM7X27_SURF, "QCT MSM7x27 SURF")
- .atag_offset = 0x100,
- .map_io = msm7x2x_map_io,
- .init_irq = msm7x2x_init_irq,
- .init_machine = msm7x2x_init,
- .init_late = msm7x2x_init_late,
- .timer = &msm_timer,
-MACHINE_END
-
-MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA")
- .atag_offset = 0x100,
- .map_io = msm7x2x_map_io,
- .init_irq = msm7x2x_init_irq,
- .init_machine = msm7x2x_init,
- .init_late = msm7x2x_init_late,
- .timer = &msm_timer,
-MACHINE_END
-
-MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF")
- .atag_offset = 0x100,
- .map_io = msm7x2x_map_io,
- .init_irq = msm7x2x_init_irq,
- .init_machine = msm7x2x_init,
- .init_late = msm7x2x_init_late,
- .timer = &msm_timer,
-MACHINE_END
-
-MACHINE_START(MSM7X25_FFA, "QCT MSM7x25 FFA")
- .atag_offset = 0x100,
- .map_io = msm7x2x_map_io,
- .init_irq = msm7x2x_init_irq,
- .init_machine = msm7x2x_init,
- .init_late = msm7x2x_init_late,
- .timer = &msm_timer,
-MACHINE_END
diff --git a/arch/arm/mach-msm/board-sapphire.c b/arch/arm/mach-msm/board-sapphire.c
index 2e569ab..b7b0fc7 100644
--- a/arch/arm/mach-msm/board-sapphire.c
+++ b/arch/arm/mach-msm/board-sapphire.c
@@ -27,7 +27,6 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/flash.h>
-#include <mach/system.h>
#include <mach/vreg.h>
#include <mach/board.h>
diff --git a/arch/arm/mach-msm/clock-pcom.c b/arch/arm/mach-msm/clock-pcom.c
index 63b7113..a52c970 100644
--- a/arch/arm/mach-msm/clock-pcom.c
+++ b/arch/arm/mach-msm/clock-pcom.c
@@ -25,7 +25,7 @@
/*
* glue for the proc_comm interface
*/
-int pc_clk_enable(unsigned id)
+static int pc_clk_enable(unsigned id)
{
int rc = msm_proc_comm(PCOM_CLKCTL_RPC_ENABLE, &id, NULL);
if (rc < 0)
@@ -34,7 +34,7 @@
return (int)id < 0 ? -EINVAL : 0;
}
-void pc_clk_disable(unsigned id)
+static void pc_clk_disable(unsigned id)
{
msm_proc_comm(PCOM_CLKCTL_RPC_DISABLE, &id, NULL);
}
@@ -54,7 +54,7 @@
return (int)id < 0 ? -EINVAL : 0;
}
-int pc_clk_set_rate(unsigned id, unsigned rate)
+static int pc_clk_set_rate(unsigned id, unsigned rate)
{
/* The rate _might_ be rounded off to the nearest KHz value by the
* remote function. So a return value of 0 doesn't necessarily mean
@@ -67,7 +67,7 @@
return (int)id < 0 ? -EINVAL : 0;
}
-int pc_clk_set_min_rate(unsigned id, unsigned rate)
+static int pc_clk_set_min_rate(unsigned id, unsigned rate)
{
int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MIN_RATE, &id, &rate);
if (rc < 0)
@@ -76,7 +76,7 @@
return (int)id < 0 ? -EINVAL : 0;
}
-int pc_clk_set_max_rate(unsigned id, unsigned rate)
+static int pc_clk_set_max_rate(unsigned id, unsigned rate)
{
int rc = msm_proc_comm(PCOM_CLKCTL_RPC_MAX_RATE, &id, &rate);
if (rc < 0)
@@ -85,7 +85,7 @@
return (int)id < 0 ? -EINVAL : 0;
}
-int pc_clk_set_flags(unsigned id, unsigned flags)
+static int pc_clk_set_flags(unsigned id, unsigned flags)
{
int rc = msm_proc_comm(PCOM_CLKCTL_RPC_SET_FLAGS, &id, &flags);
if (rc < 0)
@@ -94,7 +94,7 @@
return (int)id < 0 ? -EINVAL : 0;
}
-unsigned pc_clk_get_rate(unsigned id)
+static unsigned pc_clk_get_rate(unsigned id)
{
if (msm_proc_comm(PCOM_CLKCTL_RPC_RATE, &id, NULL))
return 0;
@@ -102,7 +102,7 @@
return id;
}
-unsigned pc_clk_is_enabled(unsigned id)
+static unsigned pc_clk_is_enabled(unsigned id)
{
if (msm_proc_comm(PCOM_CLKCTL_RPC_ENABLED, &id, NULL))
return 0;
@@ -110,7 +110,7 @@
return id;
}
-long pc_clk_round_rate(unsigned id, unsigned rate)
+static long pc_clk_round_rate(unsigned id, unsigned rate)
{
/* Not really supported; pc_clk_set_rate() does rounding on it's own. */
diff --git a/arch/arm/mach-msm/dma.c b/arch/arm/mach-msm/dma.c
index 02cae5e..354b91d 100644
--- a/arch/arm/mach-msm/dma.c
+++ b/arch/arm/mach-msm/dma.c
@@ -223,8 +223,7 @@
PRINT_FLOW("msm_datamover_irq_handler id %d, status %x\n", id, ch_status);
if ((ch_status & DMOV_STATUS_CMD_PTR_RDY) && !list_empty(&ready_commands[id])) {
cmd = list_entry(ready_commands[id].next, typeof(*cmd), list);
- list_del(&cmd->list);
- list_add_tail(&cmd->list, &active_commands[id]);
+ list_move_tail(&cmd->list, &active_commands[id]);
if (cmd->execute_func)
cmd->execute_func(cmd);
PRINT_FLOW("msm_datamover_irq_handler id %d, start command\n", id);
diff --git a/arch/arm/mach-msm/idle.c b/arch/arm/mach-msm/idle.c
deleted file mode 100644
index 0c9e13c..0000000
--- a/arch/arm/mach-msm/idle.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/* arch/arm/mach-msm/idle.c
- *
- * Idle processing for MSM7K - work around bugs with SWFI.
- *
- * Copyright (c) 2007 QUALCOMM Incorporated.
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/init.h>
-#include <asm/system.h>
-
-static void msm_idle(void)
-{
-#ifdef CONFIG_MSM7X00A_IDLE
- asm volatile (
-
- "mrc p15, 0, r1, c1, c0, 0 /* read current CR */ \n\t"
- "bic r0, r1, #(1 << 2) /* clear dcache bit */ \n\t"
- "bic r0, r0, #(1 << 12) /* clear icache bit */ \n\t"
- "mcr p15, 0, r0, c1, c0, 0 /* disable d/i cache */ \n\t"
-
- "mov r0, #0 /* prepare wfi value */ \n\t"
- "mcr p15, 0, r0, c7, c10, 0 /* flush the cache */ \n\t"
- "mcr p15, 0, r0, c7, c10, 4 /* memory barrier */ \n\t"
- "mcr p15, 0, r0, c7, c0, 4 /* wait for interrupt */ \n\t"
-
- "mcr p15, 0, r1, c1, c0, 0 /* restore d/i cache */ \n\t"
-
- : : : "r0","r1" );
-#endif
-}
-
-static int __init msm_idle_init(void)
-{
- arm_pm_idle = msm_idle;
- return 0;
-}
-
-arch_initcall(msm_idle_init);
diff --git a/arch/arm/mach-msm/include/mach/board.h b/arch/arm/mach-msm/include/mach/board.h
index 435f8ed..5a0811a 100644
--- a/arch/arm/mach-msm/include/mach/board.h
+++ b/arch/arm/mach-msm/include/mach/board.h
@@ -22,15 +22,6 @@
/* platform device data structures */
-struct msm_acpu_clock_platform_data
-{
- uint32_t acpu_switch_time_us;
- uint32_t max_speed_delta_khz;
- uint32_t vdd_switch_time_us;
- unsigned long power_collapse_khz;
- unsigned long wait_for_irq_khz;
-};
-
struct clk_lookup;
extern struct sys_timer msm_timer;
@@ -42,7 +33,6 @@
void __init msm_init_irq(void);
void __init msm_init_gpio(void);
void __init msm_clock_init(struct clk_lookup *clock_tbl, unsigned num_clocks);
-void __init msm_acpu_clock_init(struct msm_acpu_clock_platform_data *);
int __init msm_add_sdcc(unsigned int controller,
struct msm_mmc_platform_data *plat,
unsigned int stat_irq, unsigned long stat_irq_flags);
diff --git a/arch/arm/mach-msm/include/mach/system.h b/arch/arm/mach-msm/include/mach/system.h
deleted file mode 100644
index f5fb2ec..0000000
--- a/arch/arm/mach-msm/include/mach/system.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* arch/arm/mach-msm/include/mach/system.h
- *
- * Copyright (C) 2007 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-/* low level hardware reset hook -- for example, hitting the
- * PSHOLD line on the PMIC to hard reset the system
- */
-extern void (*msm_hw_reset_hook)(void);
diff --git a/arch/arm/mach-msm/io.c b/arch/arm/mach-msm/io.c
index a1e7b11..9704233 100644
--- a/arch/arm/mach-msm/io.c
+++ b/arch/arm/mach-msm/io.c
@@ -38,8 +38,7 @@
#define MSM_DEVICE(name) MSM_CHIP_DEVICE(name, MSM)
-#if defined(CONFIG_ARCH_MSM7X00A) || defined(CONFIG_ARCH_MSM7X27) \
- || defined(CONFIG_ARCH_MSM7X25)
+#if defined(CONFIG_ARCH_MSM7X00A)
static struct map_desc msm_io_desc[] __initdata = {
MSM_DEVICE(VIC),
MSM_CHIP_DEVICE(CSR, MSM7X00),
diff --git a/arch/arm/mach-msm/proc_comm.c b/arch/arm/mach-msm/proc_comm.c
index 9980dc7..8f1eecd 100644
--- a/arch/arm/mach-msm/proc_comm.c
+++ b/arch/arm/mach-msm/proc_comm.c
@@ -19,7 +19,6 @@
#include <linux/io.h>
#include <linux/spinlock.h>
#include <mach/msm_iomap.h>
-#include <mach/system.h>
#include "proc_comm.h"
diff --git a/arch/arm/mach-msm/smd.c b/arch/arm/mach-msm/smd.c
index 657be73..84183ed 100644
--- a/arch/arm/mach-msm/smd.c
+++ b/arch/arm/mach-msm/smd.c
@@ -30,7 +30,6 @@
#include <linux/delay.h>
#include <mach/msm_smd.h>
-#include <mach/system.h>
#include "smd_private.h"
#include "proc_comm.h"
@@ -39,8 +38,6 @@
#define CONFIG_QDSP6 1
#endif
-void (*msm_hw_reset_hook)(void);
-
#define MODULE_NAME "msm_smd"
enum {
@@ -101,10 +98,6 @@
pr_err("ARM9 has CRASHED\n");
smd_diag();
- /* hard reboot if possible */
- if (msm_hw_reset_hook)
- msm_hw_reset_hook();
-
/* in this case the modem or watchdog should reboot us */
for (;;)
;
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 81280825..004f935 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -101,7 +101,7 @@
static union {
struct clock_event_device *evt;
- struct clock_event_device __percpu **percpu_evt;
+ struct clock_event_device * __percpu *percpu_evt;
} msm_evt;
static void __iomem *source_base;
diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c
index a9bc841..137e479 100644
--- a/arch/arm/mach-mv78xx0/addr-map.c
+++ b/arch/arm/mach-mv78xx0/addr-map.c
@@ -13,6 +13,7 @@
#include <linux/mbus.h>
#include <linux/io.h>
#include <plat/addr-map.h>
+#include <mach/mv78xx0.h>
#include "common.h"
/*
@@ -81,7 +82,7 @@
int maj, int min)
{
orion_setup_cpu_win(&addr_map_cfg, window, base, size,
- TARGET_PCIE(maj), ATTR_PCIE_IO(min), -1);
+ TARGET_PCIE(maj), ATTR_PCIE_IO(min), 0);
}
void __init mv78xx0_setup_pcie_mem_win(int window, u32 base, u32 size,
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 3057f7d..6b0c387 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -135,11 +135,6 @@
.length = MV78XX0_CORE_REGS_SIZE,
.type = MT_DEVICE,
}, {
- .virtual = MV78XX0_PCIE_IO_VIRT_BASE(0),
- .pfn = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)),
- .length = MV78XX0_PCIE_IO_SIZE * 8,
- .type = MT_DEVICE,
- }, {
.virtual = MV78XX0_REGS_VIRT_BASE,
.pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
.length = MV78XX0_REGS_SIZE,
diff --git a/arch/arm/mach-mv78xx0/include/mach/io.h b/arch/arm/mach-mv78xx0/include/mach/io.h
deleted file mode 100644
index c7d9d00..0000000
--- a/arch/arm/mach-mv78xx0/include/mach/io.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * arch/arm/mach-mv78xx0/include/mach/io.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-
-#include "mv78xx0.h"
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-static inline void __iomem *__io(unsigned long addr)
-{
- return (void __iomem *)((addr - MV78XX0_PCIE_IO_PHYS_BASE(0))
- + MV78XX0_PCIE_IO_VIRT_BASE(0));
-}
-
-#define __io(a) __io(a)
-
-#endif
diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
index e807c4c..bd03fed 100644
--- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
+++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
@@ -29,15 +29,15 @@
*
* virt phys size
* fe400000 f102x000 16K core-specific peripheral registers
- * fe700000 f0800000 1M PCIe #0 I/O space
- * fe800000 f0900000 1M PCIe #1 I/O space
- * fe900000 f0a00000 1M PCIe #2 I/O space
- * fea00000 f0b00000 1M PCIe #3 I/O space
- * feb00000 f0c00000 1M PCIe #4 I/O space
- * fec00000 f0d00000 1M PCIe #5 I/O space
- * fed00000 f0e00000 1M PCIe #6 I/O space
- * fee00000 f0f00000 1M PCIe #7 I/O space
- * fef00000 f1000000 1M on-chip peripheral registers
+ * fee00000 f0800000 64K PCIe #0 I/O space
+ * fee10000 f0900000 64K PCIe #1 I/O space
+ * fee20000 f0a00000 64K PCIe #2 I/O space
+ * fee30000 f0b00000 64K PCIe #3 I/O space
+ * fee40000 f0c00000 64K PCIe #4 I/O space
+ * fee50000 f0d00000 64K PCIe #5 I/O space
+ * fee60000 f0e00000 64K PCIe #6 I/O space
+ * fee70000 f0f00000 64K PCIe #7 I/O space
+ * fd000000 f1000000 1M on-chip peripheral registers
*/
#define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
#define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
@@ -46,11 +46,10 @@
#define MV78XX0_CORE_REGS_SIZE SZ_16K
#define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
-#define MV78XX0_PCIE_IO_VIRT_BASE(i) (0xfe700000 + ((i) << 20))
#define MV78XX0_PCIE_IO_SIZE SZ_1M
#define MV78XX0_REGS_PHYS_BASE 0xf1000000
-#define MV78XX0_REGS_VIRT_BASE 0xfef00000
+#define MV78XX0_REGS_VIRT_BASE 0xfd000000
#define MV78XX0_REGS_SIZE SZ_1M
#define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
index 2e56e86..26a059b 100644
--- a/arch/arm/mach-mv78xx0/pcie.c
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -15,6 +15,7 @@
#include <asm/mach/pci.h>
#include <plat/pcie.h>
#include <plat/addr-map.h>
+#include <mach/mv78xx0.h>
#include "common.h"
struct pcie_port {
@@ -23,16 +24,13 @@
u8 root_bus_nr;
void __iomem *base;
spinlock_t conf_lock;
- char io_space_name[16];
char mem_space_name[16];
- struct resource res[2];
+ struct resource res;
};
static struct pcie_port pcie_port[8];
static int num_pcie_ports;
static struct resource pcie_io_space;
-static struct resource pcie_mem_space;
-
void __init mv78xx0_pcie_id(u32 *dev, u32 *rev)
{
@@ -40,102 +38,59 @@
*rev = orion_pcie_rev((void __iomem *)PCIE00_VIRT_BASE);
}
+u32 pcie_port_size[8] = {
+ 0,
+ 0x30000000,
+ 0x10000000,
+ 0x10000000,
+ 0x08000000,
+ 0x08000000,
+ 0x08000000,
+ 0x04000000,
+};
+
static void __init mv78xx0_pcie_preinit(void)
{
int i;
u32 size_each;
u32 start;
- int win;
+ int win = 0;
pcie_io_space.name = "PCIe I/O Space";
pcie_io_space.start = MV78XX0_PCIE_IO_PHYS_BASE(0);
pcie_io_space.end =
MV78XX0_PCIE_IO_PHYS_BASE(0) + MV78XX0_PCIE_IO_SIZE * 8 - 1;
- pcie_io_space.flags = IORESOURCE_IO;
+ pcie_io_space.flags = IORESOURCE_MEM;
if (request_resource(&iomem_resource, &pcie_io_space))
panic("can't allocate PCIe I/O space");
- pcie_mem_space.name = "PCIe MEM Space";
- pcie_mem_space.start = MV78XX0_PCIE_MEM_PHYS_BASE;
- pcie_mem_space.end =
- MV78XX0_PCIE_MEM_PHYS_BASE + MV78XX0_PCIE_MEM_SIZE - 1;
- pcie_mem_space.flags = IORESOURCE_MEM;
- if (request_resource(&iomem_resource, &pcie_mem_space))
- panic("can't allocate PCIe MEM space");
-
- for (i = 0; i < num_pcie_ports; i++) {
- struct pcie_port *pp = pcie_port + i;
-
- snprintf(pp->io_space_name, sizeof(pp->io_space_name),
- "PCIe %d.%d I/O", pp->maj, pp->min);
- pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
- pp->res[0].name = pp->io_space_name;
- pp->res[0].start = MV78XX0_PCIE_IO_PHYS_BASE(i);
- pp->res[0].end = pp->res[0].start + MV78XX0_PCIE_IO_SIZE - 1;
- pp->res[0].flags = IORESOURCE_IO;
-
- snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
- "PCIe %d.%d MEM", pp->maj, pp->min);
- pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
- pp->res[1].name = pp->mem_space_name;
- pp->res[1].flags = IORESOURCE_MEM;
- }
-
- switch (num_pcie_ports) {
- case 0:
- size_each = 0;
- break;
-
- case 1:
- size_each = 0x30000000;
- break;
-
- case 2 ... 3:
- size_each = 0x10000000;
- break;
-
- case 4 ... 6:
- size_each = 0x08000000;
- break;
-
- case 7:
- size_each = 0x04000000;
- break;
-
- default:
+ if (num_pcie_ports > 7)
panic("invalid number of PCIe ports");
- }
+
+ size_each = pcie_port_size[num_pcie_ports];
start = MV78XX0_PCIE_MEM_PHYS_BASE;
for (i = 0; i < num_pcie_ports; i++) {
struct pcie_port *pp = pcie_port + i;
- pp->res[1].start = start;
- pp->res[1].end = start + size_each - 1;
+ snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
+ "PCIe %d.%d MEM", pp->maj, pp->min);
+ pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
+ pp->res.name = pp->mem_space_name;
+ pp->res.flags = IORESOURCE_MEM;
+ pp->res.start = start;
+ pp->res.end = start + size_each - 1;
start += size_each;
- }
- for (i = 0; i < num_pcie_ports; i++) {
- struct pcie_port *pp = pcie_port + i;
-
- if (request_resource(&pcie_io_space, &pp->res[0]))
- panic("can't allocate PCIe I/O sub-space");
-
- if (request_resource(&pcie_mem_space, &pp->res[1]))
+ if (request_resource(&iomem_resource, &pp->res))
panic("can't allocate PCIe MEM sub-space");
- }
- win = 0;
- for (i = 0; i < num_pcie_ports; i++) {
- struct pcie_port *pp = pcie_port + i;
-
- mv78xx0_setup_pcie_io_win(win++, pp->res[0].start,
- resource_size(&pp->res[0]),
- pp->maj, pp->min);
-
- mv78xx0_setup_pcie_mem_win(win++, pp->res[1].start,
- resource_size(&pp->res[1]),
+ mv78xx0_setup_pcie_mem_win(win + i + 8, pp->res.start,
+ resource_size(&pp->res),
pp->maj, pp->min);
+
+ mv78xx0_setup_pcie_io_win(win + i, i * SZ_64K, SZ_64K,
+ pp->maj, pp->min);
}
}
@@ -156,8 +111,9 @@
orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
orion_pcie_setup(pp->base);
- pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
- pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
+ pci_ioremap_io(nr * SZ_64K, MV78XX0_PCIE_IO_PHYS_BASE(nr));
+
+ pci_add_resource_offset(&sys->resources, &pp->res, sys->mem_offset);
return 1;
}
@@ -281,7 +237,7 @@
pp->root_bus_nr = -1;
pp->base = (void __iomem *)base;
spin_lock_init(&pp->conf_lock);
- memset(pp->res, 0, sizeof(pp->res));
+ memset(&pp->res, 0, sizeof(pp->res));
} else {
printk("link down, ignoring\n");
}
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index a5ac352..1dcb751 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -475,8 +475,7 @@
break;
}
if (!tries)
- printk(KERN_WARNING "Timeout waiting for end of frame "
- "-- LCD may not be available\n");
+ pr_err("Timeout waiting for end of frame -- LCD may not be available\n");
/* turn off DMA */
reg = omap_readw(OMAP_DMA_LCD_CCR);
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index a9ee06b..638f407 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -587,8 +587,8 @@
/* Clocks in the DSP domain need api_ck. Just assume bootloader
* has not enabled any DSP clocks */
if (clk->enable_reg == DSP_IDLECT2) {
- printk(KERN_INFO "Skipping reset check for DSP domain "
- "clock \"%s\"\n", clk->name);
+ pr_info("Skipping reset check for DSP domain clock \"%s\"\n",
+ clk->name);
return;
}
diff --git a/arch/arm/mach-omap1/clock_data.c b/arch/arm/mach-omap1/clock_data.c
index 6a32b9b..9b45f4b 100644
--- a/arch/arm/mach-omap1/clock_data.c
+++ b/arch/arm/mach-omap1/clock_data.c
@@ -775,11 +775,10 @@
static void __init omap1_show_rates(void)
{
- pr_notice("Clocking rate (xtal/DPLL1/MPU): "
- "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
- ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
- ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
- arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
+ pr_notice("Clocking rate (xtal/DPLL1/MPU): %ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
+ ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
+ ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
+ arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
}
u32 cpu_mask;
@@ -840,8 +839,8 @@
if (cpu_is_omap16xx() && crystal_type == 2)
ck_ref.rate = 19200000;
- pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: "
- "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
+ pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n",
+ omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
omap_readw(ARM_CKCTL));
/* We want to be in syncronous scalable mode */
diff --git a/arch/arm/mach-omap1/dma.c b/arch/arm/mach-omap1/dma.c
index b0b0f0f..29007fe 100644
--- a/arch/arm/mach-omap1/dma.c
+++ b/arch/arm/mach-omap1/dma.c
@@ -331,8 +331,9 @@
d->chan = kzalloc(sizeof(struct omap_dma_lch) *
(d->lch_count), GFP_KERNEL);
if (!d->chan) {
- dev_err(&pdev->dev, "%s: Memory allocation failed"
- "for d->chan!!!\n", __func__);
+ dev_err(&pdev->dev,
+ "%s: Memory allocation failed for d->chan!\n",
+ __func__);
goto exit_release_d;
}
diff --git a/arch/arm/mach-omap1/lcd_dma.c b/arch/arm/mach-omap1/lcd_dma.c
index 5769c71..ed42628 100644
--- a/arch/arm/mach-omap1/lcd_dma.c
+++ b/arch/arm/mach-omap1/lcd_dma.c
@@ -113,8 +113,7 @@
void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
{
if (cpu_is_omap15xx()) {
- printk(KERN_ERR "DMA virtual resolution is not supported "
- "in 1510 mode\n");
+ pr_err("DMA virtual resolution is not supported in 1510 mode\n");
BUG();
}
lcd_dma.vxres = vxres;
@@ -437,8 +436,7 @@
r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
"LCD DMA", NULL);
if (r != 0)
- printk(KERN_ERR "unable to request IRQ for LCD DMA "
- "(error %d)\n", r);
+ pr_err("unable to request IRQ for LCD DMA (error %d)\n", r);
return r;
}
diff --git a/arch/arm/mach-omap1/leds-h2p2-debug.c b/arch/arm/mach-omap1/leds-h2p2-debug.c
index 7f4bba9..6f958ae 100644
--- a/arch/arm/mach-omap1/leds-h2p2-debug.c
+++ b/arch/arm/mach-omap1/leds-h2p2-debug.c
@@ -69,11 +69,13 @@
gpio_set_value(GPIO_IDLE, 0);
}
- __raw_writew(~0, &fpga->leds);
led_state &= ~LED_STATE_ENABLED;
- if (evt == led_halted) {
- iounmap(fpga);
- fpga = NULL;
+ if (fpga) {
+ __raw_writew(~0, &fpga->leds);
+ if (evt == led_halted) {
+ iounmap(fpga);
+ fpga = NULL;
+ }
}
goto done;
@@ -159,7 +161,7 @@
/*
* Actually burn the LEDs
*/
- if (led_state & LED_STATE_ENABLED)
+ if (led_state & LED_STATE_ENABLED && fpga)
__raw_writew(~hw_led_state, &fpga->leds);
done:
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index f6a24b3..eb203ec 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -4,36 +4,30 @@
# Common support
obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
- common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o
+ common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o
-omap-2-3-common = irq.o
-hwmod-common = omap_hwmod.o \
- omap_hwmod_common_data.o
-clock-common = clock.o clock_common_data.o \
- clkt_dpll.o clkt_clksel.o
-secure-common = omap-smc.o omap-secure.o
+# INTCPS IP block support - XXX should be moved to drivers/
+obj-$(CONFIG_ARCH_OMAP2) += irq.o
+obj-$(CONFIG_ARCH_OMAP3) += irq.o
+obj-$(CONFIG_SOC_AM33XX) += irq.o
-obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(hwmod-common)
-obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(hwmod-common) $(secure-common)
-obj-$(CONFIG_ARCH_OMAP4) += prm44xx.o $(hwmod-common) $(secure-common)
-obj-$(CONFIG_SOC_AM33XX) += irq.o $(hwmod-common)
-obj-$(CONFIG_SOC_OMAP5) += prm44xx.o $(hwmod-common) $(secure-common)
+# Secure monitor API support
+obj-$(CONFIG_ARCH_OMAP3) += omap-smc.o omap-secure.o
+obj-$(CONFIG_ARCH_OMAP4) += omap-smc.o omap-secure.o
+obj-$(CONFIG_SOC_OMAP5) += omap-smc.o omap-secure.o
ifneq ($(CONFIG_SND_OMAP_SOC_MCBSP),)
obj-y += mcbsp.o
endif
-obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
-obj-$(CONFIG_SOC_HAS_OMAP2_SDRC) += sdrc.o
+obj-$(CONFIG_TWL4030_CORE) += omap_twl.o
# SMP support ONLY available for OMAP4
obj-$(CONFIG_SMP) += omap-smp.o omap-headsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += omap-hotplug.o
-omap-4-5-common = omap4-common.o omap-wakeupgen.o \
- sleep44xx.o
-obj-$(CONFIG_ARCH_OMAP4) += $(omap-4-5-common)
-obj-$(CONFIG_SOC_OMAP5) += $(omap-4-5-common)
+obj-$(CONFIG_ARCH_OMAP4) += omap4-common.o omap-wakeupgen.o
+obj-$(CONFIG_SOC_OMAP5) += omap4-common.o omap-wakeupgen.o
plus_sec := $(call as-instr,.arch_extension sec,+sec)
AFLAGS_omap-headsmp.o :=-Wa,-march=armv7-a$(plus_sec)
@@ -58,6 +52,7 @@
# SMS/SDRC
obj-$(CONFIG_ARCH_OMAP2) += sdrc2xxx.o
# obj-$(CONFIG_ARCH_OMAP3) += sdrc3xxx.o
+obj-$(CONFIG_SOC_HAS_OMAP2_SDRC) += sdrc.o
# OPP table initialization
ifeq ($(CONFIG_PM_OPP),y)
@@ -68,15 +63,15 @@
# Power Management
ifeq ($(CONFIG_PM),y)
-obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o
-obj-$(CONFIG_ARCH_OMAP2) += sleep24xx.o
+obj-$(CONFIG_ARCH_OMAP2) += pm24xx.o sleep24xx.o
obj-$(CONFIG_ARCH_OMAP3) += pm34xx.o sleep34xx.o
obj-$(CONFIG_ARCH_OMAP4) += pm44xx.o omap-mpuss-lowpower.o
-obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o
+obj-$(CONFIG_ARCH_OMAP4) += sleep44xx.o
+obj-$(CONFIG_SOC_OMAP5) += omap-mpuss-lowpower.o sleep44xx.o
obj-$(CONFIG_PM_DEBUG) += pm-debug.o
obj-$(CONFIG_POWER_AVS_OMAP) += sr_device.o
-obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) += smartreflex-class3.o
+obj-$(CONFIG_POWER_AVS_OMAP_CLASS3) += smartreflex-class3.o
AFLAGS_sleep24xx.o :=-Wa,-march=armv6
AFLAGS_sleep34xx.o :=-Wa,-march=armv7-a$(plus_sec)
@@ -88,92 +83,76 @@
endif
ifeq ($(CONFIG_CPU_IDLE),y)
-obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o
-obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o
+obj-$(CONFIG_ARCH_OMAP3) += cpuidle34xx.o
+obj-$(CONFIG_ARCH_OMAP4) += cpuidle44xx.o
endif
# PRCM
-omap-prcm-4-5-common = prcm.o cminst44xx.o cm44xx.o \
- prcm_mpu44xx.o prminst44xx.o \
- vc44xx_data.o vp44xx_data.o
-obj-y += prm_common.o
-obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
-obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o
+obj-y += prcm.o prm_common.o
+obj-$(CONFIG_ARCH_OMAP2) += cm2xxx_3xxx.o prm2xxx_3xxx.o
+obj-$(CONFIG_ARCH_OMAP3) += cm2xxx_3xxx.o prm2xxx_3xxx.o
obj-$(CONFIG_ARCH_OMAP3) += vc3xxx_data.o vp3xxx_data.o
-obj-$(CONFIG_SOC_AM33XX) += prcm.o prm33xx.o cm33xx.o
-obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common) prm44xx.o
+obj-$(CONFIG_SOC_AM33XX) += prm33xx.o cm33xx.o
+omap-prcm-4-5-common = cminst44xx.o cm44xx.o prm44xx.o \
+ prcm_mpu44xx.o prminst44xx.o \
+ vc44xx_data.o vp44xx_data.o \
+ prm44xx.o
+obj-$(CONFIG_ARCH_OMAP4) += $(omap-prcm-4-5-common)
obj-$(CONFIG_SOC_OMAP5) += $(omap-prcm-4-5-common)
# OMAP voltage domains
-voltagedomain-common := voltage.o vc.o vp.o
-obj-$(CONFIG_ARCH_OMAP2) += $(voltagedomain-common)
+obj-y += voltage.o vc.o vp.o
obj-$(CONFIG_ARCH_OMAP2) += voltagedomains2xxx_data.o
-obj-$(CONFIG_ARCH_OMAP3) += $(voltagedomain-common)
obj-$(CONFIG_ARCH_OMAP3) += voltagedomains3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4) += $(voltagedomain-common)
obj-$(CONFIG_ARCH_OMAP4) += voltagedomains44xx_data.o
-obj-$(CONFIG_SOC_AM33XX) += $(voltagedomain-common)
-obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o
-obj-$(CONFIG_SOC_OMAP5) += $(voltagedomain-common)
+obj-$(CONFIG_SOC_AM33XX) += voltagedomains33xx_data.o
# OMAP powerdomain framework
-powerdomain-common += powerdomain.o powerdomain-common.o
-obj-$(CONFIG_ARCH_OMAP2) += $(powerdomain-common)
+obj-y += powerdomain.o powerdomain-common.o
obj-$(CONFIG_ARCH_OMAP2) += powerdomains2xxx_data.o
obj-$(CONFIG_ARCH_OMAP2) += powerdomain2xxx_3xxx.o
obj-$(CONFIG_ARCH_OMAP2) += powerdomains2xxx_3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP3) += $(powerdomain-common)
obj-$(CONFIG_ARCH_OMAP3) += powerdomain2xxx_3xxx.o
obj-$(CONFIG_ARCH_OMAP3) += powerdomains3xxx_data.o
obj-$(CONFIG_ARCH_OMAP3) += powerdomains2xxx_3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4) += $(powerdomain-common)
obj-$(CONFIG_ARCH_OMAP4) += powerdomain44xx.o
obj-$(CONFIG_ARCH_OMAP4) += powerdomains44xx_data.o
-obj-$(CONFIG_SOC_AM33XX) += $(powerdomain-common)
obj-$(CONFIG_SOC_AM33XX) += powerdomain33xx.o
obj-$(CONFIG_SOC_AM33XX) += powerdomains33xx_data.o
-obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common)
obj-$(CONFIG_SOC_OMAP5) += powerdomain44xx.o
# PRCM clockdomain control
-clockdomain-common += clockdomain.o
-obj-$(CONFIG_ARCH_OMAP2) += $(clockdomain-common)
+obj-y += clockdomain.o
obj-$(CONFIG_ARCH_OMAP2) += clockdomain2xxx_3xxx.o
obj-$(CONFIG_ARCH_OMAP2) += clockdomains2xxx_3xxx_data.o
obj-$(CONFIG_SOC_OMAP2420) += clockdomains2420_data.o
obj-$(CONFIG_SOC_OMAP2430) += clockdomains2430_data.o
-obj-$(CONFIG_ARCH_OMAP3) += $(clockdomain-common)
obj-$(CONFIG_ARCH_OMAP3) += clockdomain2xxx_3xxx.o
obj-$(CONFIG_ARCH_OMAP3) += clockdomains2xxx_3xxx_data.o
obj-$(CONFIG_ARCH_OMAP3) += clockdomains3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP4) += $(clockdomain-common)
obj-$(CONFIG_ARCH_OMAP4) += clockdomain44xx.o
obj-$(CONFIG_ARCH_OMAP4) += clockdomains44xx_data.o
-obj-$(CONFIG_SOC_AM33XX) += $(clockdomain-common)
obj-$(CONFIG_SOC_AM33XX) += clockdomain33xx.o
obj-$(CONFIG_SOC_AM33XX) += clockdomains33xx_data.o
-obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common)
obj-$(CONFIG_SOC_OMAP5) += clockdomain44xx.o
# Clock framework
-obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
-obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_sys.o
-obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o
+obj-y += clock.o clock_common_data.o \
+ clkt_dpll.o clkt_clksel.o
+obj-$(CONFIG_ARCH_OMAP2) += clock2xxx.o
+obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpllcore.o clkt2xxx_sys.o
obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_virt_prcm_set.o
obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_apll.o clkt2xxx_osc.o
obj-$(CONFIG_ARCH_OMAP2) += clkt2xxx_dpll.o clkt_iclk.o
obj-$(CONFIG_SOC_OMAP2420) += clock2420_data.o
obj-$(CONFIG_SOC_OMAP2430) += clock2430.o clock2430_data.o
-obj-$(CONFIG_ARCH_OMAP3) += $(clock-common) clock3xxx.o
+obj-$(CONFIG_ARCH_OMAP3) += clock3xxx.o
obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clkt34xx_dpll3m2.o
-obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o
+obj-$(CONFIG_ARCH_OMAP3) += clock3517.o clock36xx.o clkt_iclk.o
obj-$(CONFIG_ARCH_OMAP3) += dpll3xxx.o clock3xxx_data.o
-obj-$(CONFIG_ARCH_OMAP3) += clkt_iclk.o
-obj-$(CONFIG_ARCH_OMAP4) += $(clock-common) clock44xx_data.o
+obj-$(CONFIG_ARCH_OMAP4) += clock44xx_data.o
obj-$(CONFIG_ARCH_OMAP4) += dpll3xxx.o dpll44xx.o
-obj-$(CONFIG_SOC_AM33XX) += $(clock-common) dpll3xxx.o
-obj-$(CONFIG_SOC_AM33XX) += clock33xx_data.o
-obj-$(CONFIG_SOC_OMAP5) += $(clock-common)
+obj-$(CONFIG_SOC_AM33XX) += dpll3xxx.o clock33xx_data.o
obj-$(CONFIG_SOC_OMAP5) += dpll3xxx.o dpll44xx.o
# OMAP2 clock rate set data (old "OPP" data)
@@ -181,6 +160,7 @@
obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o
# hwmod data
+obj-y += omap_hwmod_common_data.o
obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o
obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_3xxx_ipblock_data.o
obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_interconnect_data.o
@@ -229,10 +209,10 @@
obj-$(CONFIG_MACH_OMAP_2430SDP) += board-2430sdp.o
obj-$(CONFIG_MACH_OMAP_APOLLON) += board-apollon.o
obj-$(CONFIG_MACH_OMAP3_BEAGLE) += board-omap3beagle.o
-obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o
+obj-$(CONFIG_MACH_DEVKIT8000) += board-devkit8000.o
obj-$(CONFIG_MACH_OMAP_LDP) += board-ldp.o
-obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o
-obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o
+obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o
+obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o
obj-$(CONFIG_MACH_ENCORE) += board-omap3encore.o
obj-$(CONFIG_MACH_OVERO) += board-overo.o
obj-$(CONFIG_MACH_OMAP3EVM) += board-omap3evm.o
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index d8deaea..4b43fe3 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -550,8 +550,8 @@
ret = menelaus_set_regulator_sleep(1, val);
if (ret < 0) {
- printk(KERN_ERR "Could not set regulators to sleep on "
- "menelaus: %u\n", ret);
+ pr_err("Could not set regulators to sleep on menelaus: %u\n",
+ ret);
return ret;
}
return 0;
@@ -563,8 +563,7 @@
ret = menelaus_set_vcore_hw(1400, 1050);
if (ret < 0) {
- printk(KERN_ERR "Could not set VCORE voltage on "
- "menelaus: %u\n", ret);
+ pr_err("Could not set VCORE voltage on menelaus: %u\n", ret);
return ret;
}
return 0;
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 7a62d13..13c101c 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -516,8 +516,7 @@
udelay(10);
gpio_set_value(OVERO_GPIO_W2W_NRESET, 1);
} else {
- printk(KERN_ERR "could not obtain gpio for "
- "OVERO_GPIO_W2W_NRESET\n");
+ pr_err("could not obtain gpio for OVERO_GPIO_W2W_NRESET\n");
}
ret = gpio_request_array(overo_bt_gpios, ARRAY_SIZE(overo_bt_gpios));
@@ -536,8 +535,7 @@
if (ret == 0)
gpio_export(OVERO_GPIO_USBH_CPEN, 0);
else
- printk(KERN_ERR "could not obtain gpio for "
- "OVERO_GPIO_USBH_CPEN\n");
+ pr_err("could not obtain gpio for OVERO_GPIO_USBH_CPEN\n");
}
MACHINE_START(OVERO, "Gumstix Overo")
diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c
index 5ec069e..0d8d919 100644
--- a/arch/arm/mach-omap2/board-zoom-debugboard.c
+++ b/arch/arm/mach-omap2/board-zoom-debugboard.c
@@ -84,8 +84,7 @@
quart_cs = ZOOM_QUADUART_CS;
if (gpmc_cs_request(quart_cs, SZ_1M, &cs_mem_base) < 0) {
- printk(KERN_ERR "Failed to request GPMC mem"
- "for Quad UART(TL16CP754C)\n");
+ pr_err("Failed to request GPMC mem for Quad UART(TL16CP754C)\n");
return;
}
@@ -107,8 +106,8 @@
if (gpio_request_one(debug_board_detect, GPIOF_IN,
"Zoom debug board detect") < 0) {
- printk(KERN_ERR "Failed to request GPIO%d for Zoom debug"
- "board detect\n", debug_board_detect);
+ pr_err("Failed to request GPIO%d for Zoom debug board detect\n",
+ debug_board_detect);
return 0;
}
diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
index d6e34dd..298887b 100644
--- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
+++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
@@ -92,15 +92,13 @@
pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
validrate);
- pr_debug("clock: SDRC CS0 timing params used:"
- " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
+ pr_debug("clock: SDRC CS0 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
if (sdrc_cs1)
- pr_debug("clock: SDRC CS1 timing params used: "
- " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
- sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
- sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
+ pr_debug("clock: SDRC CS1 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
+ sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
+ sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
if (sdrc_cs1)
omap3_configure_core_dpll(
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index 04d551b..19a9809 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -71,8 +71,8 @@
if (!clks->parent) {
/* This indicates a data problem */
- WARN(1, "clock: Could not find parent clock %s in clksel array "
- "of clock %s\n", src_clk->name, clk->name);
+ WARN(1, "clock: %s: could not find parent clock %s in clksel array\n",
+ clk->name, src_clk->name);
return NULL;
}
@@ -126,8 +126,8 @@
if (max_div == 0) {
/* This indicates an error in the clksel data */
- WARN(1, "clock: Could not find divisor for clock %s parent %s"
- "\n", clk->name, src_clk->parent->name);
+ WARN(1, "clock: %s: could not find divisor for parent %s\n",
+ clk->name, src_clk->parent->name);
return 0;
}
@@ -191,8 +191,8 @@
if (!clkr->div) {
/* This indicates a data error */
- WARN(1, "clock: Could not find fieldval %d for clock %s parent "
- "%s\n", field_val, clk->name, clk->parent->name);
+ WARN(1, "clock: %s: could not find fieldval %d parent %s\n",
+ clk->name, field_val, clk->parent->name);
return 0;
}
@@ -230,8 +230,8 @@
}
if (!clkr->div) {
- pr_err("clock: Could not find divisor %d for clock %s parent "
- "%s\n", div, clk->name, clk->parent->name);
+ pr_err("clock: %s: could not find divisor %d parent %s\n",
+ clk->name, div, clk->parent->name);
return ~0;
}
@@ -300,8 +300,8 @@
/* Sanity check */
if (clkr->div <= last_div)
- pr_err("clock: clksel_rate table not sorted "
- "for clock %s", clk->name);
+ pr_err("clock: %s: clksel_rate table not sorted",
+ clk->name);
last_div = clkr->div;
@@ -312,9 +312,8 @@
}
if (!clkr->div) {
- pr_err("clock: Could not find divisor for target "
- "rate %ld for clock %s parent %s\n", target_rate,
- clk->name, clk->parent->name);
+ pr_err("clock: %s: could not find divisor for target rate %ld parent %s\n",
+ clk->name, target_rate, clk->parent->name);
return ~0;
}
@@ -359,8 +358,7 @@
if (clkr->val == r) {
if (clk->parent != clks->parent) {
- pr_debug("clock: inited %s parent "
- "to %s (was %s)\n",
+ pr_debug("clock: %s: inited parent to %s (was %s)\n",
clk->name, clks->parent->name,
((clk->parent) ?
clk->parent->name : "NULL"));
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index ae624c3..a3b60c7 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -105,13 +105,13 @@
}
if (fint < fint_min) {
- pr_debug("rejecting n=%d due to Fint failure, "
- "lowering max_divider\n", n);
+ pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n",
+ n);
dd->max_divider = n;
ret = DPLL_FINT_UNDERFLOW;
} else if (fint > fint_max) {
- pr_debug("rejecting n=%d due to Fint failure, "
- "boosting min_divider\n", n);
+ pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n",
+ n);
dd->min_divider = n;
ret = DPLL_FINT_INVALID;
} else if (cpu_is_omap3430() && fint > OMAP3430_DPLL_FINT_BAND1_MAX &&
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 1a1f97f..e97f98f 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -104,8 +104,8 @@
clk->name, clk->clkdm_name);
clk->clkdm = clkdm;
} else {
- pr_debug("clock: could not associate clk %s to "
- "clkdm %s\n", clk->name, clk->clkdm_name);
+ pr_debug("clock: could not associate clk %s to clkdm %s\n",
+ clk->name, clk->clkdm_name);
}
}
@@ -228,8 +228,7 @@
* 'Independent' here refers to a clock which is not
* controlled by its parent.
*/
- printk(KERN_ERR "clock: clk_disable called on independent "
- "clock %s which has no enable_reg\n", clk->name);
+ pr_err("clock: clk_disable called on independent clock %s which has no enable_reg\n", clk->name);
return;
}
@@ -272,8 +271,7 @@
void omap2_clk_disable(struct clk *clk)
{
if (clk->usecount == 0) {
- WARN(1, "clock: %s: omap2_clk_disable() called, but usecount "
- "already 0?", clk->name);
+ WARN(1, "clock: %s: omap2_clk_disable() called, but usecount already 0?", clk->name);
return;
}
@@ -334,8 +332,8 @@
if (clkdm_control && clk->clkdm) {
ret = clkdm_clk_enable(clk->clkdm, clk);
if (ret) {
- WARN(1, "clock: %s: could not enable clockdomain %s: "
- "%d\n", clk->name, clk->clkdm->name, ret);
+ WARN(1, "clock: %s: could not enable clockdomain %s: %d\n",
+ clk->name, clk->clkdm->name, ret);
goto oce_err2;
}
}
@@ -503,10 +501,8 @@
hfclkin_rate = clk_get_rate(hfclkin_ck);
- pr_info("Switched to new clocking rate (Crystal/Core/MPU): "
- "%ld.%01ld/%ld/%ld MHz\n",
- (hfclkin_rate / 1000000),
- ((hfclkin_rate / 100000) % 10),
+ pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
+ (hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10),
(clk_get_rate(core_ck) / 1000000),
(clk_get_rate(mpu_ck) / 1000000));
}
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
index fc2765b..15cdc647 100644
--- a/arch/arm/mach-omap2/clock3xxx.c
+++ b/arch/arm/mach-omap2/clock3xxx.c
@@ -49,8 +49,7 @@
* on DPLL4.
*/
if (omap_rev() == OMAP3430_REV_ES1_0) {
- pr_err("clock: DPLL4 cannot change rate due to "
- "silicon 'Limitation 2.5' on 3430ES1.\n");
+ pr_err("clock: DPLL4 cannot change rate due to silicon 'Limitation 2.5' on 3430ES1.\n");
return -EINVAL;
}
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 8664f5a..a155562 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -174,9 +174,8 @@
if (IS_ERR(autodep->clkdm.ptr))
continue;
- pr_debug("clockdomain: adding %s sleepdep/wkdep for "
- "clkdm %s\n", autodep->clkdm.ptr->name,
- clkdm->name);
+ pr_debug("clockdomain: %s: adding %s sleepdep/wkdep\n",
+ clkdm->name, autodep->clkdm.ptr->name);
clkdm_add_sleepdep(clkdm, autodep->clkdm.ptr);
clkdm_add_wkdep(clkdm, autodep->clkdm.ptr);
@@ -205,9 +204,8 @@
if (IS_ERR(autodep->clkdm.ptr))
continue;
- pr_debug("clockdomain: removing %s sleepdep/wkdep for "
- "clkdm %s\n", autodep->clkdm.ptr->name,
- clkdm->name);
+ pr_debug("clockdomain: %s: removing %s sleepdep/wkdep\n",
+ clkdm->name, autodep->clkdm.ptr->name);
clkdm_del_sleepdep(clkdm, autodep->clkdm.ptr);
clkdm_del_wkdep(clkdm, autodep->clkdm.ptr);
@@ -469,14 +467,14 @@
ret = -EINVAL;
if (ret) {
- pr_debug("clockdomain: hardware cannot set/clear wake up of "
- "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
+ pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n",
+ clkdm1->name, clkdm2->name);
return ret;
}
if (atomic_inc_return(&cd->wkdep_usecount) == 1) {
- pr_debug("clockdomain: hardware will wake up %s when %s wakes "
- "up\n", clkdm1->name, clkdm2->name);
+ pr_debug("clockdomain: hardware will wake up %s when %s wakes up\n",
+ clkdm1->name, clkdm2->name);
ret = arch_clkdm->clkdm_add_wkdep(clkdm1, clkdm2);
}
@@ -510,14 +508,14 @@
ret = -EINVAL;
if (ret) {
- pr_debug("clockdomain: hardware cannot set/clear wake up of "
- "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
+ pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n",
+ clkdm1->name, clkdm2->name);
return ret;
}
if (atomic_dec_return(&cd->wkdep_usecount) == 0) {
- pr_debug("clockdomain: hardware will no longer wake up %s "
- "after %s wakes up\n", clkdm1->name, clkdm2->name);
+ pr_debug("clockdomain: hardware will no longer wake up %s after %s wakes up\n",
+ clkdm1->name, clkdm2->name);
ret = arch_clkdm->clkdm_del_wkdep(clkdm1, clkdm2);
}
@@ -555,8 +553,8 @@
ret = -EINVAL;
if (ret) {
- pr_debug("clockdomain: hardware cannot set/clear wake up of "
- "%s when %s wakes up\n", clkdm1->name, clkdm2->name);
+ pr_debug("clockdomain: hardware cannot set/clear wake up of %s when %s wakes up\n",
+ clkdm1->name, clkdm2->name);
return ret;
}
@@ -613,15 +611,14 @@
ret = -EINVAL;
if (ret) {
- pr_debug("clockdomain: hardware cannot set/clear sleep "
- "dependency affecting %s from %s\n", clkdm1->name,
- clkdm2->name);
+ pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n",
+ clkdm1->name, clkdm2->name);
return ret;
}
if (atomic_inc_return(&cd->sleepdep_usecount) == 1) {
- pr_debug("clockdomain: will prevent %s from sleeping if %s "
- "is active\n", clkdm1->name, clkdm2->name);
+ pr_debug("clockdomain: will prevent %s from sleeping if %s is active\n",
+ clkdm1->name, clkdm2->name);
ret = arch_clkdm->clkdm_add_sleepdep(clkdm1, clkdm2);
}
@@ -657,16 +654,14 @@
ret = -EINVAL;
if (ret) {
- pr_debug("clockdomain: hardware cannot set/clear sleep "
- "dependency affecting %s from %s\n", clkdm1->name,
- clkdm2->name);
+ pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n",
+ clkdm1->name, clkdm2->name);
return ret;
}
if (atomic_dec_return(&cd->sleepdep_usecount) == 0) {
- pr_debug("clockdomain: will no longer prevent %s from "
- "sleeping if %s is active\n", clkdm1->name,
- clkdm2->name);
+ pr_debug("clockdomain: will no longer prevent %s from sleeping if %s is active\n",
+ clkdm1->name, clkdm2->name);
ret = arch_clkdm->clkdm_del_sleepdep(clkdm1, clkdm2);
}
@@ -706,9 +701,8 @@
ret = -EINVAL;
if (ret) {
- pr_debug("clockdomain: hardware cannot set/clear sleep "
- "dependency affecting %s from %s\n", clkdm1->name,
- clkdm2->name);
+ pr_debug("clockdomain: hardware cannot set/clear sleep dependency affecting %s from %s\n",
+ clkdm1->name, clkdm2->name);
return ret;
}
@@ -755,8 +749,8 @@
return -EINVAL;
if (!(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
- pr_debug("clockdomain: %s does not support forcing "
- "sleep via software\n", clkdm->name);
+ pr_debug("clockdomain: %s does not support forcing sleep via software\n",
+ clkdm->name);
return -EINVAL;
}
@@ -790,8 +784,8 @@
return -EINVAL;
if (!(clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) {
- pr_debug("clockdomain: %s does not support forcing "
- "wakeup via software\n", clkdm->name);
+ pr_debug("clockdomain: %s does not support forcing wakeup via software\n",
+ clkdm->name);
return -EINVAL;
}
@@ -826,8 +820,8 @@
return;
if (!(clkdm->flags & CLKDM_CAN_ENABLE_AUTO)) {
- pr_debug("clock: automatic idle transitions cannot be enabled "
- "on clockdomain %s\n", clkdm->name);
+ pr_debug("clock: %s: automatic idle transitions cannot be enabled\n",
+ clkdm->name);
return;
}
@@ -861,8 +855,8 @@
return;
if (!(clkdm->flags & CLKDM_CAN_DISABLE_AUTO)) {
- pr_debug("clockdomain: automatic idle transitions cannot be "
- "disabled on %s\n", clkdm->name);
+ pr_debug("clockdomain: %s: automatic idle transitions cannot be disabled\n",
+ clkdm->name);
return;
}
@@ -927,7 +921,7 @@
pwrdm_state_switch(clkdm->pwrdm.ptr);
spin_unlock_irqrestore(&clkdm->lock, flags);
- pr_debug("clockdomain: clkdm %s: enabled\n", clkdm->name);
+ pr_debug("clockdomain: %s: enabled\n", clkdm->name);
return 0;
}
@@ -952,7 +946,7 @@
pwrdm_state_switch(clkdm->pwrdm.ptr);
spin_unlock_irqrestore(&clkdm->lock, flags);
- pr_debug("clockdomain: clkdm %s: disabled\n", clkdm->name);
+ pr_debug("clockdomain: %s: disabled\n", clkdm->name);
return 0;
}
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
index 013fedc..f81dd0a 100644
--- a/arch/arm/mach-omap2/common-board-devices.c
+++ b/arch/arm/mach-omap2/common-board-devices.c
@@ -120,8 +120,7 @@
}
if (nandcs > GPMC_CS_NUM) {
- printk(KERN_INFO "NAND: Unable to find configuration "
- "in GPMC\n ");
+ pr_info("NAND: Unable to find configuration in GPMC\n");
return;
}
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 6ef4010..f6cbcdc 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -22,7 +22,6 @@
#include <asm/mach-types.h>
#include <asm/mach/map.h>
-#include <asm/pmu.h>
#include "iomap.h"
#include <plat/dma.h>
@@ -446,7 +445,7 @@
static struct platform_device omap_pmu_device = {
.name = "arm-pmu",
- .id = ARM_PMU_DEVICE_CPU,
+ .id = -1,
.num_resources = 1,
};
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index d8318dc..ef66645 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -623,8 +623,11 @@
while (pclk && !pclk->dpll_data)
pclk = pclk->parent;
- /* clk does not have a DPLL as a parent? */
- WARN_ON(!pclk);
+ /* clk does not have a DPLL as a parent? error in the clock data */
+ if (!pclk) {
+ WARN_ON(1);
+ return 0;
+ }
dd = pclk->dpll_data;
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c
index 7b52bdf..e7b246d 100644
--- a/arch/arm/mach-omap2/gpio.c
+++ b/arch/arm/mach-omap2/gpio.c
@@ -61,6 +61,7 @@
pdata->regs = kzalloc(sizeof(struct omap_gpio_reg_offs), GFP_KERNEL);
if (!pdata->regs) {
pr_err("gpio%d: Memory allocation failed\n", id);
+ kfree(pdata);
return -ENOMEM;
}
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 055ae8b..72428bd 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -297,7 +297,7 @@
div = gpmc_cs_calc_divider(cs, t->sync_clk);
if (div < 0)
- return -1;
+ return div;
GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 7219df0..6b98a17 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -161,9 +161,8 @@
}
if (j == ARRAY_SIZE(omap_ids)) {
- printk(KERN_ERR "Unknown OMAP device type. "
- "Handling it as OMAP%04x\n",
- omap_ids[i].type >> 16);
+ pr_err("Unknown OMAP device type. Handling it as OMAP%04x\n",
+ omap_ids[i].type >> 16);
j = i;
}
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index efed4f5..3926f37 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -108,9 +108,8 @@
unsigned long tmp;
tmp = intc_bank_read_reg(bank, INTC_REVISION) & 0xff;
- printk(KERN_INFO "IRQ: Found an INTC at 0x%p "
- "(revision %ld.%ld) with %d interrupts\n",
- bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
+ pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n",
+ bank->base_reg, tmp >> 4, tmp & 0xf, bank->nr_irqs);
tmp = intc_bank_read_reg(bank, INTC_SYSCONFIG);
tmp |= 1 << 1; /* soft reset */
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 9db1684..80b7359 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1438,8 +1438,8 @@
* Return the bit position of the reset line that match the
* input name. Return -ENOENT if not found.
*/
-static u8 _lookup_hardreset(struct omap_hwmod *oh, const char *name,
- struct omap_hwmod_rst_info *ohri)
+static int _lookup_hardreset(struct omap_hwmod *oh, const char *name,
+ struct omap_hwmod_rst_info *ohri)
{
int i;
@@ -1475,7 +1475,7 @@
static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
{
struct omap_hwmod_rst_info ohri;
- u8 ret = -EINVAL;
+ int ret = -EINVAL;
if (!oh)
return -EINVAL;
@@ -1484,7 +1484,7 @@
return -ENOSYS;
ret = _lookup_hardreset(oh, name, &ohri);
- if (IS_ERR_VALUE(ret))
+ if (ret < 0)
return ret;
ret = soc_ops.assert_hardreset(oh, &ohri);
@@ -1542,7 +1542,7 @@
static int _read_hardreset(struct omap_hwmod *oh, const char *name)
{
struct omap_hwmod_rst_info ohri;
- u8 ret = -EINVAL;
+ int ret = -EINVAL;
if (!oh)
return -EINVAL;
@@ -1551,7 +1551,7 @@
return -ENOSYS;
ret = _lookup_hardreset(oh, name, &ohri);
- if (IS_ERR_VALUE(ret))
+ if (ret < 0)
return ret;
return soc_ops.is_hardreset_asserted(oh, &ohri);
@@ -1641,8 +1641,8 @@
/* clocks must be on for this operation */
if (oh->_state != _HWMOD_STATE_ENABLED) {
- pr_warning("omap_hwmod: %s: reset can only be entered from "
- "enabled state\n", oh->name);
+ pr_warn("omap_hwmod: %s: reset can only be entered from enabled state\n",
+ oh->name);
return -EINVAL;
}
diff --git a/arch/arm/mach-omap2/opp.c b/arch/arm/mach-omap2/opp.c
index d8f6dbf..45ad7f7 100644
--- a/arch/arm/mach-omap2/opp.c
+++ b/arch/arm/mach-omap2/opp.c
@@ -64,25 +64,22 @@
}
oh = omap_hwmod_lookup(opp_def->hwmod_name);
if (!oh || !oh->od) {
- pr_debug("%s: no hwmod or odev for %s, [%d] "
- "cannot add OPPs.\n", __func__,
- opp_def->hwmod_name, i);
+ pr_debug("%s: no hwmod or odev for %s, [%d] cannot add OPPs.\n",
+ __func__, opp_def->hwmod_name, i);
continue;
}
dev = &oh->od->pdev->dev;
r = opp_add(dev, opp_def->freq, opp_def->u_volt);
if (r) {
- dev_err(dev, "%s: add OPP %ld failed for %s [%d] "
- "result=%d\n",
- __func__, opp_def->freq,
- opp_def->hwmod_name, i, r);
+ dev_err(dev, "%s: add OPP %ld failed for %s [%d] result=%d\n",
+ __func__, opp_def->freq,
+ opp_def->hwmod_name, i, r);
} else {
if (!opp_def->default_available)
r = opp_disable(dev, opp_def->freq);
if (r)
- dev_err(dev, "%s: disable %ld failed for %s "
- "[%d] result=%d\n",
+ dev_err(dev, "%s: disable %ld failed for %s [%d] result=%d\n",
__func__, opp_def->freq,
opp_def->hwmod_name, i, r);
}
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 9cb5cede..939bd6f 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -203,8 +203,8 @@
bootup_volt = opp_get_voltage(opp);
rcu_read_unlock();
if (!bootup_volt) {
- pr_err("%s: unable to find voltage corresponding "
- "to the bootup OPP for vdd_%s\n", __func__, vdd_name);
+ pr_err("%s: unable to find voltage corresponding to the bootup OPP for vdd_%s\n",
+ __func__, vdd_name);
goto exit;
}
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 90480f7..ba670db 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -391,9 +391,8 @@
list_for_each_entry(pwrst, &pwrst_list, node) {
state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
if (state > pwrst->next_state) {
- pr_info("Powerdomain (%s) didn't enter "
- "target state %d\n",
- pwrst->pwrdm->name, pwrst->next_state);
+ pr_info("Powerdomain (%s) didn't enter target state %d\n",
+ pwrst->pwrdm->name, pwrst->next_state);
ret = -1;
}
omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
@@ -733,8 +732,7 @@
omap3_secure_ram_storage =
kmalloc(0x803F, GFP_KERNEL);
if (!omap3_secure_ram_storage)
- pr_err("Memory allocation failed when "
- "allocating for secure sram context\n");
+ pr_err("Memory allocation failed when allocating for secure sram context\n");
local_irq_disable();
local_fiq_disable();
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index ea24174..04922d1 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -69,9 +69,8 @@
list_for_each_entry(pwrst, &pwrst_list, node) {
state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
if (state > pwrst->next_state) {
- pr_info("Powerdomain (%s) didn't enter "
- "target state %d\n",
- pwrst->pwrdm->name, pwrst->next_state);
+ pr_info("Powerdomain (%s) didn't enter target state %d\n",
+ pwrst->pwrdm->name, pwrst->next_state);
ret = -1;
}
omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
@@ -189,8 +188,7 @@
ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm);
ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
if (ret) {
- pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 "
- "wakeup dependency\n");
+ pr_err("Failed to add MPUSS -> L3/EMIF/L4PER, DUCATI -> L3 wakeup dependency\n");
goto err2;
}
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index ca5be83..1678a32 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -341,8 +341,8 @@
if (!pwrdm || !clkdm)
return -EINVAL;
- pr_debug("powerdomain: associating clockdomain %s with powerdomain "
- "%s\n", clkdm->name, pwrdm->name);
+ pr_debug("powerdomain: %s: associating clockdomain %s\n",
+ pwrdm->name, clkdm->name);
for (i = 0; i < PWRDM_MAX_CLKDMS; i++) {
if (!pwrdm->pwrdm_clkdms[i])
@@ -356,8 +356,8 @@
}
if (i == PWRDM_MAX_CLKDMS) {
- pr_debug("powerdomain: increase PWRDM_MAX_CLKDMS for "
- "pwrdm %s clkdm %s\n", pwrdm->name, clkdm->name);
+ pr_debug("powerdomain: %s: increase PWRDM_MAX_CLKDMS for clkdm %s\n",
+ pwrdm->name, clkdm->name);
WARN_ON(1);
ret = -ENOMEM;
goto pac_exit;
@@ -389,16 +389,16 @@
if (!pwrdm || !clkdm)
return -EINVAL;
- pr_debug("powerdomain: dissociating clockdomain %s from powerdomain "
- "%s\n", clkdm->name, pwrdm->name);
+ pr_debug("powerdomain: %s: dissociating clockdomain %s\n",
+ pwrdm->name, clkdm->name);
for (i = 0; i < PWRDM_MAX_CLKDMS; i++)
if (pwrdm->pwrdm_clkdms[i] == clkdm)
break;
if (i == PWRDM_MAX_CLKDMS) {
- pr_debug("powerdomain: clkdm %s not associated with pwrdm "
- "%s ?!\n", clkdm->name, pwrdm->name);
+ pr_debug("powerdomain: %s: clkdm %s not associated?!\n",
+ pwrdm->name, clkdm->name);
ret = -ENOENT;
goto pdc_exit;
}
@@ -487,7 +487,7 @@
if (!(pwrdm->pwrsts & (1 << pwrst)))
return -EINVAL;
- pr_debug("powerdomain: setting next powerstate for %s to %0x\n",
+ pr_debug("powerdomain: %s: setting next powerstate to %0x\n",
pwrdm->name, pwrst);
if (arch_pwrdm && arch_pwrdm->pwrdm_set_next_pwrst) {
@@ -589,7 +589,7 @@
if (!(pwrdm->pwrsts_logic_ret & (1 << pwrst)))
return -EINVAL;
- pr_debug("powerdomain: setting next logic powerstate for %s to %0x\n",
+ pr_debug("powerdomain: %s: setting next logic powerstate to %0x\n",
pwrdm->name, pwrst);
if (arch_pwrdm && arch_pwrdm->pwrdm_set_logic_retst)
@@ -626,8 +626,8 @@
if (!(pwrdm->pwrsts_mem_on[bank] & (1 << pwrst)))
return -EINVAL;
- pr_debug("powerdomain: setting next memory powerstate for domain %s "
- "bank %0x while pwrdm-ON to %0x\n", pwrdm->name, bank, pwrst);
+ pr_debug("powerdomain: %s: setting next memory powerstate for bank %0x while pwrdm-ON to %0x\n",
+ pwrdm->name, bank, pwrst);
if (arch_pwrdm && arch_pwrdm->pwrdm_set_mem_onst)
ret = arch_pwrdm->pwrdm_set_mem_onst(pwrdm, bank, pwrst);
@@ -664,8 +664,8 @@
if (!(pwrdm->pwrsts_mem_ret[bank] & (1 << pwrst)))
return -EINVAL;
- pr_debug("powerdomain: setting next memory powerstate for domain %s "
- "bank %0x while pwrdm-RET to %0x\n", pwrdm->name, bank, pwrst);
+ pr_debug("powerdomain: %s: setting next memory powerstate for bank %0x while pwrdm-RET to %0x\n",
+ pwrdm->name, bank, pwrst);
if (arch_pwrdm && arch_pwrdm->pwrdm_set_mem_retst)
ret = arch_pwrdm->pwrdm_set_mem_retst(pwrdm, bank, pwrst);
@@ -843,7 +843,7 @@
* warn & fail if it is not ON.
*/
- pr_debug("powerdomain: clearing previous power state reg for %s\n",
+ pr_debug("powerdomain: %s: clearing previous power state reg\n",
pwrdm->name);
if (arch_pwrdm && arch_pwrdm->pwrdm_clear_all_prev_pwrst)
@@ -873,8 +873,7 @@
if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR))
return ret;
- pr_debug("powerdomain: %s: setting SAVEANDRESTORE bit\n",
- pwrdm->name);
+ pr_debug("powerdomain: %s: setting SAVEANDRESTORE bit\n", pwrdm->name);
if (arch_pwrdm && arch_pwrdm->pwrdm_enable_hdwr_sar)
ret = arch_pwrdm->pwrdm_enable_hdwr_sar(pwrdm);
@@ -903,8 +902,7 @@
if (!(pwrdm->flags & PWRDM_HAS_HDWR_SAR))
return ret;
- pr_debug("powerdomain: %s: clearing SAVEANDRESTORE bit\n",
- pwrdm->name);
+ pr_debug("powerdomain: %s: clearing SAVEANDRESTORE bit\n", pwrdm->name);
if (arch_pwrdm && arch_pwrdm->pwrdm_disable_hdwr_sar)
ret = arch_pwrdm->pwrdm_disable_hdwr_sar(pwrdm);
diff --git a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
index 0f0a9f1..3950ccf 100644
--- a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c
@@ -122,8 +122,8 @@
udelay(1);
if (c > PWRDM_TRANSITION_BAILOUT) {
- printk(KERN_ERR "powerdomain: waited too long for "
- "powerdomain %s to complete transition\n", pwrdm->name);
+ pr_err("powerdomain: %s: waited too long to complete transition\n",
+ pwrdm->name);
return -EAGAIN;
}
diff --git a/arch/arm/mach-omap2/powerdomain44xx.c b/arch/arm/mach-omap2/powerdomain44xx.c
index 601325b..aeac6f3 100644
--- a/arch/arm/mach-omap2/powerdomain44xx.c
+++ b/arch/arm/mach-omap2/powerdomain44xx.c
@@ -198,8 +198,8 @@
udelay(1);
if (c > PWRDM_TRANSITION_BAILOUT) {
- printk(KERN_ERR "powerdomain: waited too long for "
- "powerdomain %s to complete transition\n", pwrdm->name);
+ pr_err("powerdomain: %s: waited too long to complete transition\n",
+ pwrdm->name);
return -EAGAIN;
}
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 9c9d23c..0f51e03 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -139,11 +139,11 @@
MAX_MODULE_ENABLE_WAIT, i);
if (i < MAX_MODULE_ENABLE_WAIT)
- pr_debug("cm: Module associated with clock %s ready after %d "
- "loops\n", name, i);
+ pr_debug("cm: Module associated with clock %s ready after %d loops\n",
+ name, i);
else
- pr_err("cm: Module associated with clock %s didn't enable in "
- "%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
+ pr_err("cm: Module associated with clock %s didn't enable in %d tries\n",
+ name, MAX_MODULE_ENABLE_WAIT);
return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
};
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 7ca266e..0405c81 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -232,9 +232,8 @@
if (console_loglevel >= 10) {
uart_debug = true;
- pr_info("%s used as console in debug mode"
- " uart%d clocks will not be"
- " gated", uart_name, uart->num);
+ pr_info("%s used as console in debug mode: uart%d clocks will not be gated",
+ uart_name, uart->num);
}
if (cmdline_find_option("no_console_suspend"))
@@ -319,8 +318,11 @@
pdev = omap_device_build(name, uart->num, oh, pdata, pdata_size,
NULL, 0, false);
- WARN(IS_ERR(pdev), "Could not build omap_device for %s: %s.\n",
- name, oh->name);
+ if (IS_ERR(pdev)) {
+ WARN(1, "Could not build omap_device for %s: %s.\n", name,
+ oh->name);
+ return;
+ }
if ((console_uart_id == bdata->id) && no_console_suspend)
omap_device_disable_idle_on_suspend(pdev);
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index d033a65..cbeae56 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -104,16 +104,15 @@
sr_data = kzalloc(sizeof(struct omap_sr_data), GFP_KERNEL);
if (!sr_data) {
- pr_err("%s: Unable to allocate memory for %s sr_data.Error!\n",
- __func__, oh->name);
+ pr_err("%s: Unable to allocate memory for %s sr_data\n",
+ __func__, oh->name);
return -ENOMEM;
}
sr_dev_attr = (struct omap_smartreflex_dev_attr *)oh->dev_attr;
if (!sr_dev_attr || !sr_dev_attr->sensor_voltdm_name) {
- pr_err("%s: No voltage domain specified for %s."
- "Cannot initialize\n", __func__,
- oh->name);
+ pr_err("%s: No voltage domain specified for %s. Cannot initialize\n",
+ __func__, oh->name);
goto exit;
}
@@ -131,8 +130,8 @@
omap_voltage_get_volttable(sr_data->voltdm, &volt_data);
if (!volt_data) {
- pr_warning("%s: No Voltage table registered fo VDD%d."
- "Something really wrong\n\n", __func__, i + 1);
+ pr_err("%s: No Voltage table registered for VDD%d\n",
+ __func__, i + 1);
goto exit;
}
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 25cbe73..e17cf97 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -213,7 +213,7 @@
res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
BUG_ON(res);
- omap2_gp_timer_irq.dev_id = (void *)&clkev;
+ omap2_gp_timer_irq.dev_id = &clkev;
setup_irq(clkev.irq, &omap2_gp_timer_irq);
__omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
diff --git a/arch/arm/mach-omap2/vc.c b/arch/arm/mach-omap2/vc.c
index b451f3c..880249b 100644
--- a/arch/arm/mach-omap2/vc.c
+++ b/arch/arm/mach-omap2/vc.c
@@ -115,9 +115,8 @@
}
if (!voltdm->pmic->uv_to_vsel) {
- pr_err("%s: PMIC function to convert voltage in uV to"
- "vsel not registered. Hence unable to scale voltage"
- "for vdd_%s\n", __func__, voltdm->name);
+ pr_err("%s: PMIC function to convert voltage in uV to vsel not registered. Hence unable to scale voltage for vdd_%s\n",
+ __func__, voltdm->name);
return -ENODATA;
}
diff --git a/arch/arm/mach-omap2/voltage.c b/arch/arm/mach-omap2/voltage.c
index 4dc60e8..3ac8fe1 100644
--- a/arch/arm/mach-omap2/voltage.c
+++ b/arch/arm/mach-omap2/voltage.c
@@ -195,8 +195,8 @@
return &voltdm->volt_data[i];
}
- pr_notice("%s: Unable to match the current voltage with the voltage"
- "table for vdd_%s\n", __func__, voltdm->name);
+ pr_notice("%s: Unable to match the current voltage with the voltage table for vdd_%s\n",
+ __func__, voltdm->name);
return ERR_PTR(-ENODATA);
}
@@ -249,8 +249,8 @@
voltdm->scale = omap_vc_bypass_scale;
return;
default:
- pr_warning("%s: Trying to change the method of voltage scaling"
- "to an unsupported one!\n", __func__);
+ pr_warn("%s: Trying to change the method of voltage scaling to an unsupported one!\n",
+ __func__);
}
}
@@ -331,8 +331,8 @@
if (!voltdm || !pwrdm)
return -EINVAL;
- pr_debug("voltagedomain: associating powerdomain %s with voltagedomain "
- "%s\n", pwrdm->name, voltdm->name);
+ pr_debug("voltagedomain: %s: associating powerdomain %s\n",
+ voltdm->name, pwrdm->name);
list_add(&pwrdm->voltdm_node, &voltdm->pwrdm_list);
diff --git a/arch/arm/mach-omap2/vp.c b/arch/arm/mach-omap2/vp.c
index f95c1ba..85241b8 100644
--- a/arch/arm/mach-omap2/vp.c
+++ b/arch/arm/mach-omap2/vp.c
@@ -138,8 +138,8 @@
udelay(1);
}
if (timeout >= VP_TRANXDONE_TIMEOUT) {
- pr_warning("%s: vdd_%s TRANXDONE timeout exceeded."
- "Voltage change aborted", __func__, voltdm->name);
+ pr_warn("%s: vdd_%s TRANXDONE timeout exceeded. Voltage change aborted",
+ __func__, voltdm->name);
return -ETIMEDOUT;
}
@@ -157,9 +157,8 @@
omap_test_timeout(vp->common->ops->check_txdone(vp->id),
VP_TRANXDONE_TIMEOUT, timeout);
if (timeout >= VP_TRANXDONE_TIMEOUT)
- pr_err("%s: vdd_%s TRANXDONE timeout exceeded."
- "TRANXDONE never got set after the voltage update\n",
- __func__, voltdm->name);
+ pr_err("%s: vdd_%s TRANXDONE timeout exceeded. TRANXDONE never got set after the voltage update\n",
+ __func__, voltdm->name);
omap_vc_post_scale(voltdm, target_volt, target_vsel, current_vsel);
@@ -176,8 +175,7 @@
}
if (timeout >= VP_TRANXDONE_TIMEOUT)
- pr_warning("%s: vdd_%s TRANXDONE timeout exceeded while trying"
- "to clear the TRANXDONE status\n",
+ pr_warn("%s: vdd_%s TRANXDONE timeout exceeded while trying to clear the TRANXDONE status\n",
__func__, voltdm->name);
/* Clear force bit */
@@ -257,8 +255,8 @@
/* If VP is already disabled, do nothing. Return */
if (!vp->enabled) {
- pr_warning("%s: Trying to disable VP for vdd_%s when"
- "it is already disabled\n", __func__, voltdm->name);
+ pr_warn("%s: Trying to disable VP for vdd_%s when it is already disabled\n",
+ __func__, voltdm->name);
return;
}
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 410291c..87a6cda 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -47,16 +47,6 @@
.length = ORION5X_REGS_SIZE,
.type = MT_DEVICE,
}, {
- .virtual = ORION5X_PCIE_IO_VIRT_BASE,
- .pfn = __phys_to_pfn(ORION5X_PCIE_IO_PHYS_BASE),
- .length = ORION5X_PCIE_IO_SIZE,
- .type = MT_DEVICE,
- }, {
- .virtual = ORION5X_PCI_IO_VIRT_BASE,
- .pfn = __phys_to_pfn(ORION5X_PCI_IO_PHYS_BASE),
- .length = ORION5X_PCI_IO_SIZE,
- .type = MT_DEVICE,
- }, {
.virtual = ORION5X_PCIE_WA_VIRT_BASE,
.pfn = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
.length = ORION5X_PCIE_WA_SIZE,
diff --git a/arch/arm/mach-orion5x/include/mach/io.h b/arch/arm/mach-orion5x/include/mach/io.h
deleted file mode 100644
index 1aa5d0a..0000000
--- a/arch/arm/mach-orion5x/include/mach/io.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * arch/arm/mach-orion5x/include/mach/io.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-
-#include <mach/orion5x.h>
-#include <asm/sizes.h>
-
-#define IO_SPACE_LIMIT SZ_2M
-static inline void __iomem *__io(unsigned long addr)
-{
- return (void __iomem *)(addr + ORION5X_PCIE_IO_VIRT_BASE);
-}
-
-#define __io(a) __io(a)
-#endif
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h
index 683e085..1b60131 100644
--- a/arch/arm/mach-orion5x/include/mach/orion5x.h
+++ b/arch/arm/mach-orion5x/include/mach/orion5x.h
@@ -31,31 +31,29 @@
* fc000000 device bus mappings (cs0/cs1)
*
* virt phys size
- * fdd00000 f1000000 1M on-chip peripheral registers
- * fde00000 f2000000 1M PCIe I/O space
- * fdf00000 f2100000 1M PCI I/O space
- * fe000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only)
+ * fe000000 f1000000 1M on-chip peripheral registers
+ * fee00000 f2000000 64K PCIe I/O space
+ * fee10000 f2100000 64K PCI I/O space
+ * fd000000 f0000000 16M PCIe WA space (Orion-1/Orion-NAS only)
****************************************************************************/
#define ORION5X_REGS_PHYS_BASE 0xf1000000
-#define ORION5X_REGS_VIRT_BASE 0xfdd00000
+#define ORION5X_REGS_VIRT_BASE 0xfe000000
#define ORION5X_REGS_SIZE SZ_1M
#define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000
-#define ORION5X_PCIE_IO_VIRT_BASE 0xfde00000
#define ORION5X_PCIE_IO_BUS_BASE 0x00000000
-#define ORION5X_PCIE_IO_SIZE SZ_1M
+#define ORION5X_PCIE_IO_SIZE SZ_64K
#define ORION5X_PCI_IO_PHYS_BASE 0xf2100000
-#define ORION5X_PCI_IO_VIRT_BASE 0xfdf00000
-#define ORION5X_PCI_IO_BUS_BASE 0x00100000
-#define ORION5X_PCI_IO_SIZE SZ_1M
+#define ORION5X_PCI_IO_BUS_BASE 0x00010000
+#define ORION5X_PCI_IO_SIZE SZ_64K
#define ORION5X_SRAM_PHYS_BASE (0xf2200000)
#define ORION5X_SRAM_SIZE SZ_8K
/* Relevant only for Orion-1/Orion-NAS */
#define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000
-#define ORION5X_PCIE_WA_VIRT_BASE 0xfe000000
+#define ORION5X_PCIE_WA_VIRT_BASE 0xfd000000
#define ORION5X_PCIE_WA_SIZE SZ_16M
#define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index cb19e16..6921d49 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -162,35 +162,25 @@
pcie_ops.read = pcie_rd_conf_wa;
}
+ pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCIE_IO_PHYS_BASE);
+
/*
* Request resources.
*/
- res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
+ res = kzalloc(sizeof(struct resource), GFP_KERNEL);
if (!res)
panic("pcie_setup unable to alloc resources");
/*
- * IORESOURCE_IO
- */
- sys->io_offset = 0;
- res[0].name = "PCIe I/O Space";
- res[0].flags = IORESOURCE_IO;
- res[0].start = ORION5X_PCIE_IO_BUS_BASE;
- res[0].end = res[0].start + ORION5X_PCIE_IO_SIZE - 1;
- if (request_resource(&ioport_resource, &res[0]))
- panic("Request PCIe IO resource failed\n");
- pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
-
- /*
* IORESOURCE_MEM
*/
- res[1].name = "PCIe Memory Space";
- res[1].flags = IORESOURCE_MEM;
- res[1].start = ORION5X_PCIE_MEM_PHYS_BASE;
- res[1].end = res[1].start + ORION5X_PCIE_MEM_SIZE - 1;
- if (request_resource(&iomem_resource, &res[1]))
+ res->name = "PCIe Memory Space";
+ res->flags = IORESOURCE_MEM;
+ res->start = ORION5X_PCIE_MEM_PHYS_BASE;
+ res->end = res->start + ORION5X_PCIE_MEM_SIZE - 1;
+ if (request_resource(&iomem_resource, res))
panic("Request PCIe Memory resource failed\n");
- pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
+ pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
return 1;
}
@@ -489,35 +479,25 @@
*/
orion5x_setbits(PCI_CMD, PCI_CMD_HOST_REORDER);
+ pci_ioremap_io(sys->busnr * SZ_64K, ORION5X_PCI_IO_PHYS_BASE);
+
/*
* Request resources
*/
- res = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
+ res = kzalloc(sizeof(struct resource), GFP_KERNEL);
if (!res)
panic("pci_setup unable to alloc resources");
/*
- * IORESOURCE_IO
- */
- sys->io_offset = 0;
- res[0].name = "PCI I/O Space";
- res[0].flags = IORESOURCE_IO;
- res[0].start = ORION5X_PCI_IO_BUS_BASE;
- res[0].end = res[0].start + ORION5X_PCI_IO_SIZE - 1;
- if (request_resource(&ioport_resource, &res[0]))
- panic("Request PCI IO resource failed\n");
- pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
-
- /*
* IORESOURCE_MEM
*/
- res[1].name = "PCI Memory Space";
- res[1].flags = IORESOURCE_MEM;
- res[1].start = ORION5X_PCI_MEM_PHYS_BASE;
- res[1].end = res[1].start + ORION5X_PCI_MEM_SIZE - 1;
- if (request_resource(&iomem_resource, &res[1]))
+ res->name = "PCI Memory Space";
+ res->flags = IORESOURCE_MEM;
+ res->start = ORION5X_PCI_MEM_PHYS_BASE;
+ res->end = res->start + ORION5X_PCI_MEM_SIZE - 1;
+ if (request_resource(&iomem_resource, res))
panic("Request PCI Memory resource failed\n");
- pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
+ pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
return 1;
}
diff --git a/arch/arm/mach-pnx4008/Makefile b/arch/arm/mach-pnx4008/Makefile
deleted file mode 100644
index 777564c..0000000
--- a/arch/arm/mach-pnx4008/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-obj-y := core.o irq.o time.o clock.o gpio.o serial.o dma.o i2c.o
-obj-m :=
-obj-n :=
-obj- :=
-
-# Power Management
-obj-$(CONFIG_PM) += pm.o sleep.o
-
diff --git a/arch/arm/mach-pnx4008/Makefile.boot b/arch/arm/mach-pnx4008/Makefile.boot
deleted file mode 100644
index 9fa19ba..0000000
--- a/arch/arm/mach-pnx4008/Makefile.boot
+++ /dev/null
@@ -1,4 +0,0 @@
- zreladdr-y += 0x80008000
-params_phys-y := 0x80000100
-initrd_phys-y := 0x80800000
-
diff --git a/arch/arm/mach-pnx4008/clock.c b/arch/arm/mach-pnx4008/clock.c
deleted file mode 100644
index a4a3819..0000000
--- a/arch/arm/mach-pnx4008/clock.c
+++ /dev/null
@@ -1,1001 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/clock.c
- *
- * Clock control driver for PNX4008
- *
- * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
- * Generic clock management functions are partially based on:
- * linux/arch/arm/mach-omap/clock.c
- *
- * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/device.h>
-#include <linux/err.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-
-#include <mach/hardware.h>
-#include <mach/clock.h>
-#include "clock.h"
-
-/*forward declaration*/
-static struct clk per_ck;
-static struct clk hclk_ck;
-static struct clk ck_1MHz;
-static struct clk ck_13MHz;
-static struct clk ck_pll1;
-static int local_set_rate(struct clk *clk, u32 rate);
-
-static inline void clock_lock(void)
-{
- local_irq_disable();
-}
-
-static inline void clock_unlock(void)
-{
- local_irq_enable();
-}
-
-static void propagate_rate(struct clk *clk)
-{
- struct clk *tmp_clk;
-
- tmp_clk = clk;
- while (tmp_clk->propagate_next) {
- tmp_clk = tmp_clk->propagate_next;
- local_set_rate(tmp_clk, tmp_clk->user_rate);
- }
-}
-
-static void clk_reg_disable(struct clk *clk)
-{
- if (clk->enable_reg)
- __raw_writel(__raw_readl(clk->enable_reg) &
- ~(1 << clk->enable_shift), clk->enable_reg);
-}
-
-static int clk_reg_enable(struct clk *clk)
-{
- if (clk->enable_reg)
- __raw_writel(__raw_readl(clk->enable_reg) |
- (1 << clk->enable_shift), clk->enable_reg);
- return 0;
-}
-
-static inline void clk_reg_disable1(struct clk *clk)
-{
- if (clk->enable_reg1)
- __raw_writel(__raw_readl(clk->enable_reg1) &
- ~(1 << clk->enable_shift1), clk->enable_reg1);
-}
-
-static inline void clk_reg_enable1(struct clk *clk)
-{
- if (clk->enable_reg1)
- __raw_writel(__raw_readl(clk->enable_reg1) |
- (1 << clk->enable_shift1), clk->enable_reg1);
-}
-
-static int clk_wait_for_pll_lock(struct clk *clk)
-{
- int i;
- i = 0;
- while (i++ < 0xFFF && !(__raw_readl(clk->scale_reg) & 1)) ; /*wait for PLL to lock */
-
- if (!(__raw_readl(clk->scale_reg) & 1)) {
- printk(KERN_ERR
- "%s ERROR: failed to lock, scale reg data: %x\n",
- clk->name, __raw_readl(clk->scale_reg));
- return -1;
- }
- return 0;
-}
-
-static int switch_to_dirty_13mhz(struct clk *clk)
-{
- int i;
- int ret;
- u32 tmp_reg;
-
- ret = 0;
-
- if (!clk->rate)
- clk_reg_enable1(clk);
-
- tmp_reg = __raw_readl(clk->parent_switch_reg);
- /*if 13Mhz clock selected, select 13'MHz (dirty) source from OSC */
- if (!(tmp_reg & 1)) {
- tmp_reg |= (1 << 1); /* Trigger switch to 13'MHz (dirty) clock */
- __raw_writel(tmp_reg, clk->parent_switch_reg);
- i = 0;
- while (i++ < 0xFFF && !(__raw_readl(clk->parent_switch_reg) & 1)) ; /*wait for 13'MHz selection status */
-
- if (!(__raw_readl(clk->parent_switch_reg) & 1)) {
- printk(KERN_ERR
- "%s ERROR: failed to select 13'MHz, parent sw reg data: %x\n",
- clk->name, __raw_readl(clk->parent_switch_reg));
- ret = -1;
- }
- }
-
- if (!clk->rate)
- clk_reg_disable1(clk);
-
- return ret;
-}
-
-static int switch_to_clean_13mhz(struct clk *clk)
-{
- int i;
- int ret;
- u32 tmp_reg;
-
- ret = 0;
-
- if (!clk->rate)
- clk_reg_enable1(clk);
-
- tmp_reg = __raw_readl(clk->parent_switch_reg);
- /*if 13'Mhz clock selected, select 13MHz (clean) source from OSC */
- if (tmp_reg & 1) {
- tmp_reg &= ~(1 << 1); /* Trigger switch to 13MHz (clean) clock */
- __raw_writel(tmp_reg, clk->parent_switch_reg);
- i = 0;
- while (i++ < 0xFFF && (__raw_readl(clk->parent_switch_reg) & 1)) ; /*wait for 13MHz selection status */
-
- if (__raw_readl(clk->parent_switch_reg) & 1) {
- printk(KERN_ERR
- "%s ERROR: failed to select 13MHz, parent sw reg data: %x\n",
- clk->name, __raw_readl(clk->parent_switch_reg));
- ret = -1;
- }
- }
-
- if (!clk->rate)
- clk_reg_disable1(clk);
-
- return ret;
-}
-
-static int set_13MHz_parent(struct clk *clk, struct clk *parent)
-{
- int ret = -EINVAL;
-
- if (parent == &ck_13MHz)
- ret = switch_to_clean_13mhz(clk);
- else if (parent == &ck_pll1)
- ret = switch_to_dirty_13mhz(clk);
-
- return ret;
-}
-
-#define PLL160_MIN_FCCO 156000
-#define PLL160_MAX_FCCO 320000
-
-/*
- * Calculate pll160 settings.
- * Possible input: up to 320MHz with step of clk->parent->rate.
- * In PNX4008 parent rate for pll160s may be either 1 or 13MHz.
- * Ignored paths: "feedback" (bit 13 set), "div-by-N".
- * Setting ARM PLL4 rate to 0 will put CPU into direct run mode.
- * Setting PLL5 and PLL3 rate to 0 will disable USB and DSP clock input.
- * Please refer to PNX4008 IC manual for details.
- */
-
-static int pll160_set_rate(struct clk *clk, u32 rate)
-{
- u32 tmp_reg, tmp_m, tmp_2p, i;
- u32 parent_rate;
- int ret = -EINVAL;
-
- parent_rate = clk->parent->rate;
-
- if (!parent_rate)
- goto out;
-
- /* set direct run for ARM or disable output for others */
- clk_reg_disable(clk);
-
- /* disable source input as well (ignored for ARM) */
- clk_reg_disable1(clk);
-
- tmp_reg = __raw_readl(clk->scale_reg);
- tmp_reg &= ~0x1ffff; /*clear all settings, power down */
- __raw_writel(tmp_reg, clk->scale_reg);
-
- rate -= rate % parent_rate; /*round down the input */
-
- if (rate > PLL160_MAX_FCCO)
- rate = PLL160_MAX_FCCO;
-
- if (!rate) {
- clk->rate = 0;
- ret = 0;
- goto out;
- }
-
- clk_reg_enable1(clk);
- tmp_reg = __raw_readl(clk->scale_reg);
-
- if (rate == parent_rate) {
- /*enter direct bypass mode */
- tmp_reg |= ((1 << 14) | (1 << 15));
- __raw_writel(tmp_reg, clk->scale_reg);
- clk->rate = parent_rate;
- clk_reg_enable(clk);
- ret = 0;
- goto out;
- }
-
- i = 0;
- for (tmp_2p = 1; tmp_2p < 16; tmp_2p <<= 1) {
- if (rate * tmp_2p >= PLL160_MIN_FCCO)
- break;
- i++;
- }
-
- if (tmp_2p > 1)
- tmp_reg |= ((i - 1) << 11);
- else
- tmp_reg |= (1 << 14); /*direct mode, no divide */
-
- tmp_m = rate * tmp_2p;
- tmp_m /= parent_rate;
-
- tmp_reg |= (tmp_m - 1) << 1; /*calculate M */
- tmp_reg |= (1 << 16); /*power up PLL */
- __raw_writel(tmp_reg, clk->scale_reg);
-
- if (clk_wait_for_pll_lock(clk) < 0) {
- clk_reg_disable(clk);
- clk_reg_disable1(clk);
-
- tmp_reg = __raw_readl(clk->scale_reg);
- tmp_reg &= ~0x1ffff; /*clear all settings, power down */
- __raw_writel(tmp_reg, clk->scale_reg);
- clk->rate = 0;
- ret = -EFAULT;
- goto out;
- }
-
- clk->rate = (tmp_m * parent_rate) / tmp_2p;
-
- if (clk->flags & RATE_PROPAGATES)
- propagate_rate(clk);
-
- clk_reg_enable(clk);
- ret = 0;
-
-out:
- return ret;
-}
-
-/*configure PER_CLK*/
-static int per_clk_set_rate(struct clk *clk, u32 rate)
-{
- u32 tmp;
-
- tmp = __raw_readl(clk->scale_reg);
- tmp &= ~(0x1f << 2);
- tmp |= ((clk->parent->rate / clk->rate) - 1) << 2;
- __raw_writel(tmp, clk->scale_reg);
- clk->rate = rate;
- return 0;
-}
-
-/*configure HCLK*/
-static int hclk_set_rate(struct clk *clk, u32 rate)
-{
- u32 tmp;
- tmp = __raw_readl(clk->scale_reg);
- tmp = tmp & ~0x3;
- switch (rate) {
- case 1:
- break;
- case 2:
- tmp |= 1;
- break;
- case 4:
- tmp |= 2;
- break;
- }
-
- __raw_writel(tmp, clk->scale_reg);
- clk->rate = rate;
- return 0;
-}
-
-static u32 hclk_round_rate(struct clk *clk, u32 rate)
-{
- switch (rate) {
- case 1:
- case 4:
- return rate;
- }
- return 2;
-}
-
-static u32 per_clk_round_rate(struct clk *clk, u32 rate)
-{
- return CLK_RATE_13MHZ;
-}
-
-static int on_off_set_rate(struct clk *clk, u32 rate)
-{
- if (rate) {
- clk_reg_enable(clk);
- clk->rate = 1;
- } else {
- clk_reg_disable(clk);
- clk->rate = 0;
- }
- return 0;
-}
-
-static int on_off_inv_set_rate(struct clk *clk, u32 rate)
-{
- if (rate) {
- clk_reg_disable(clk); /*enable bit is inverted */
- clk->rate = 1;
- } else {
- clk_reg_enable(clk);
- clk->rate = 0;
- }
- return 0;
-}
-
-static u32 on_off_round_rate(struct clk *clk, u32 rate)
-{
- return (rate ? 1 : 0);
-}
-
-static u32 pll4_round_rate(struct clk *clk, u32 rate)
-{
- if (rate > CLK_RATE_208MHZ)
- rate = CLK_RATE_208MHZ;
- if (rate == CLK_RATE_208MHZ && hclk_ck.user_rate == 1)
- rate = CLK_RATE_208MHZ - CLK_RATE_13MHZ;
- return (rate - (rate % (hclk_ck.user_rate * CLK_RATE_13MHZ)));
-}
-
-static u32 pll3_round_rate(struct clk *clk, u32 rate)
-{
- if (rate > CLK_RATE_208MHZ)
- rate = CLK_RATE_208MHZ;
- return (rate - rate % CLK_RATE_13MHZ);
-}
-
-static u32 pll5_round_rate(struct clk *clk, u32 rate)
-{
- return (rate ? CLK_RATE_48MHZ : 0);
-}
-
-static u32 ck_13MHz_round_rate(struct clk *clk, u32 rate)
-{
- return (rate ? CLK_RATE_13MHZ : 0);
-}
-
-static int ck_13MHz_set_rate(struct clk *clk, u32 rate)
-{
- if (rate) {
- clk_reg_disable(clk); /*enable bit is inverted */
- udelay(500);
- clk->rate = CLK_RATE_13MHZ;
- ck_1MHz.rate = CLK_RATE_1MHZ;
- } else {
- clk_reg_enable(clk);
- clk->rate = 0;
- ck_1MHz.rate = 0;
- }
- return 0;
-}
-
-static int pll1_set_rate(struct clk *clk, u32 rate)
-{
-#if 0 /* doesn't work on some boards, probably a HW BUG */
- if (rate) {
- clk_reg_disable(clk); /*enable bit is inverted */
- if (!clk_wait_for_pll_lock(clk)) {
- clk->rate = CLK_RATE_13MHZ;
- } else {
- clk_reg_enable(clk);
- clk->rate = 0;
- }
-
- } else {
- clk_reg_enable(clk);
- clk->rate = 0;
- }
-#endif
- return 0;
-}
-
-/* Clock sources */
-
-static struct clk osc_13MHz = {
- .name = "osc_13MHz",
- .flags = FIXED_RATE,
- .rate = CLK_RATE_13MHZ,
-};
-
-static struct clk ck_13MHz = {
- .name = "ck_13MHz",
- .parent = &osc_13MHz,
- .flags = NEEDS_INITIALIZATION,
- .round_rate = &ck_13MHz_round_rate,
- .set_rate = &ck_13MHz_set_rate,
- .enable_reg = OSC13CTRL_REG,
- .enable_shift = 0,
- .rate = CLK_RATE_13MHZ,
-};
-
-static struct clk osc_32KHz = {
- .name = "osc_32KHz",
- .flags = FIXED_RATE,
- .rate = CLK_RATE_32KHZ,
-};
-
-/*attached to PLL5*/
-static struct clk ck_1MHz = {
- .name = "ck_1MHz",
- .flags = FIXED_RATE | PARENT_SET_RATE,
- .parent = &ck_13MHz,
-};
-
-/* PLL1 (397) - provides 13' MHz clock */
-static struct clk ck_pll1 = {
- .name = "ck_pll1",
- .parent = &osc_32KHz,
- .flags = NEEDS_INITIALIZATION,
- .round_rate = &ck_13MHz_round_rate,
- .set_rate = &pll1_set_rate,
- .enable_reg = PLLCTRL_REG,
- .enable_shift = 1,
- .scale_reg = PLLCTRL_REG,
- .rate = CLK_RATE_13MHZ,
-};
-
-/* CPU/Bus PLL */
-static struct clk ck_pll4 = {
- .name = "ck_pll4",
- .parent = &ck_pll1,
- .flags = RATE_PROPAGATES | NEEDS_INITIALIZATION,
- .propagate_next = &per_ck,
- .round_rate = &pll4_round_rate,
- .set_rate = &pll160_set_rate,
- .rate = CLK_RATE_208MHZ,
- .scale_reg = HCLKPLLCTRL_REG,
- .enable_reg = PWRCTRL_REG,
- .enable_shift = 2,
- .parent_switch_reg = SYSCLKCTRL_REG,
- .set_parent = &set_13MHz_parent,
-};
-
-/* USB PLL */
-static struct clk ck_pll5 = {
- .name = "ck_pll5",
- .parent = &ck_1MHz,
- .flags = NEEDS_INITIALIZATION,
- .round_rate = &pll5_round_rate,
- .set_rate = &pll160_set_rate,
- .scale_reg = USBCTRL_REG,
- .enable_reg = USBCTRL_REG,
- .enable_shift = 18,
- .enable_reg1 = USBCTRL_REG,
- .enable_shift1 = 17,
-};
-
-/* XPERTTeak DSP PLL */
-static struct clk ck_pll3 = {
- .name = "ck_pll3",
- .parent = &ck_pll1,
- .flags = NEEDS_INITIALIZATION,
- .round_rate = &pll3_round_rate,
- .set_rate = &pll160_set_rate,
- .scale_reg = DSPPLLCTRL_REG,
- .enable_reg = DSPCLKCTRL_REG,
- .enable_shift = 3,
- .enable_reg1 = DSPCLKCTRL_REG,
- .enable_shift1 = 2,
- .parent_switch_reg = DSPCLKCTRL_REG,
- .set_parent = &set_13MHz_parent,
-};
-
-static struct clk hclk_ck = {
- .name = "hclk_ck",
- .parent = &ck_pll4,
- .flags = PARENT_SET_RATE,
- .set_rate = &hclk_set_rate,
- .round_rate = &hclk_round_rate,
- .scale_reg = HCLKDIVCTRL_REG,
- .rate = 2,
- .user_rate = 2,
-};
-
-static struct clk per_ck = {
- .name = "per_ck",
- .parent = &ck_pll4,
- .flags = FIXED_RATE,
- .propagate_next = &hclk_ck,
- .set_rate = &per_clk_set_rate,
- .round_rate = &per_clk_round_rate,
- .scale_reg = HCLKDIVCTRL_REG,
- .rate = CLK_RATE_13MHZ,
- .user_rate = CLK_RATE_13MHZ,
-};
-
-static struct clk m2hclk_ck = {
- .name = "m2hclk_ck",
- .parent = &hclk_ck,
- .flags = NEEDS_INITIALIZATION,
- .round_rate = &on_off_round_rate,
- .set_rate = &on_off_inv_set_rate,
- .rate = 1,
- .enable_shift = 6,
- .enable_reg = PWRCTRL_REG,
-};
-
-static struct clk vfp9_ck = {
- .name = "vfp9_ck",
- .parent = &ck_pll4,
- .flags = NEEDS_INITIALIZATION,
- .round_rate = &on_off_round_rate,
- .set_rate = &on_off_set_rate,
- .rate = 1,
- .enable_shift = 4,
- .enable_reg = VFP9CLKCTRL_REG,
-};
-
-static struct clk keyscan_ck = {
- .name = "keyscan_ck",
- .parent = &osc_32KHz,
- .flags = NEEDS_INITIALIZATION,
- .round_rate = &on_off_round_rate,
- .set_rate = &on_off_set_rate,
- .enable_shift = 0,
- .enable_reg = KEYCLKCTRL_REG,
-};
-
-static struct clk touch_ck = {
- .name = "touch_ck",
- .parent = &osc_32KHz,
- .flags = NEEDS_INITIALIZATION,
- .round_rate = &on_off_round_rate,
- .set_rate = &on_off_set_rate,
- .enable_shift = 0,
- .enable_reg = TSCLKCTRL_REG,
-};
-
-static struct clk pwm1_ck = {
- .name = "pwm1_ck",
- .parent = &osc_32KHz,
- .flags = NEEDS_INITIALIZATION,
- .round_rate = &on_off_round_rate,
- .set_rate = &on_off_set_rate,
- .enable_shift = 0,
- .enable_reg = PWMCLKCTRL_REG,
-};
-
-static struct clk pwm2_ck = {
- .name = "pwm2_ck",
- .parent = &osc_32KHz,
- .flags = NEEDS_INITIALIZATION,
- .round_rate = &on_off_round_rate,
- .set_rate = &on_off_set_rate,
- .enable_shift = 2,
- .enable_reg = PWMCLKCTRL_REG,
-};
-
-static struct clk jpeg_ck = {
- .name = "jpeg_ck",
- .parent = &hclk_ck,
- .flags = NEEDS_INITIALIZATION,
- .round_rate = &on_off_round_rate,
- .set_rate = &on_off_set_rate,
- .enable_shift = 0,
- .enable_reg = JPEGCLKCTRL_REG,
-};
-
-static struct clk ms_ck = {
- .name = "ms_ck",
- .parent = &ck_pll4,
- .flags = NEEDS_INITIALIZATION,
- .round_rate = &on_off_round_rate,
- .set_rate = &on_off_set_rate,
- .enable_shift = 5,
- .enable_reg = MSCTRL_REG,
-};
-
-static struct clk dum_ck = {
- .name = "dum_ck",
- .parent = &hclk_ck,
- .flags = NEEDS_INITIALIZATION,
- .round_rate = &on_off_round_rate,
- .set_rate = &on_off_set_rate,
- .enable_shift = 0,
- .enable_reg = DUMCLKCTRL_REG,
-};
-
-static struct clk flash_ck = {
- .name = "flash_ck",
- .parent = &hclk_ck,
- .round_rate = &on_off_round_rate,
- .set_rate = &on_off_set_rate,
- .enable_shift = 1, /* Only MLC clock supported */
- .enable_reg = FLASHCLKCTRL_REG,
-};
-
-static struct clk i2c0_ck = {
- .name = "i2c0_ck",
- .parent = &per_ck,
- .flags = NEEDS_INITIALIZATION | FIXED_RATE,
- .enable_shift = 0,
- .enable_reg = I2CCLKCTRL_REG,
- .rate = 13000000,
- .enable = clk_reg_enable,
- .disable = clk_reg_disable,
-};
-
-static struct clk i2c1_ck = {
- .name = "i2c1_ck",
- .parent = &per_ck,
- .flags = NEEDS_INITIALIZATION | FIXED_RATE,
- .enable_shift = 1,
- .enable_reg = I2CCLKCTRL_REG,
- .rate = 13000000,
- .enable = clk_reg_enable,
- .disable = clk_reg_disable,
-};
-
-static struct clk i2c2_ck = {
- .name = "i2c2_ck",
- .parent = &per_ck,
- .flags = NEEDS_INITIALIZATION | FIXED_RATE,
- .enable_shift = 2,
- .enable_reg = USB_OTG_CLKCTRL_REG,
- .rate = 13000000,
- .enable = clk_reg_enable,
- .disable = clk_reg_disable,
-};
-
-static struct clk spi0_ck = {
- .name = "spi0_ck",
- .parent = &hclk_ck,
- .flags = NEEDS_INITIALIZATION,
- .round_rate = &on_off_round_rate,
- .set_rate = &on_off_set_rate,
- .enable_shift = 0,
- .enable_reg = SPICTRL_REG,
-};
-
-static struct clk spi1_ck = {
- .name = "spi1_ck",
- .parent = &hclk_ck,
- .flags = NEEDS_INITIALIZATION,
- .round_rate = &on_off_round_rate,
- .set_rate = &on_off_set_rate,
- .enable_shift = 4,
- .enable_reg = SPICTRL_REG,
-};
-
-static struct clk dma_ck = {
- .name = "dma_ck",
- .parent = &hclk_ck,
- .round_rate = &on_off_round_rate,
- .set_rate = &on_off_set_rate,
- .enable_shift = 0,
- .enable_reg = DMACLKCTRL_REG,
-};
-
-static struct clk uart3_ck = {
- .name = "uart3_ck",
- .parent = &per_ck,
- .flags = NEEDS_INITIALIZATION,
- .round_rate = &on_off_round_rate,
- .set_rate = &on_off_set_rate,
- .rate = 1,
- .enable_shift = 0,
- .enable_reg = UARTCLKCTRL_REG,
-};
-
-static struct clk uart4_ck = {
- .name = "uart4_ck",
- .parent = &per_ck,
- .flags = NEEDS_INITIALIZATION,
- .round_rate = &on_off_round_rate,
- .set_rate = &on_off_set_rate,
- .enable_shift = 1,
- .enable_reg = UARTCLKCTRL_REG,
-};
-
-static struct clk uart5_ck = {
- .name = "uart5_ck",
- .parent = &per_ck,
- .flags = NEEDS_INITIALIZATION,
- .round_rate = &on_off_round_rate,
- .set_rate = &on_off_set_rate,
- .rate = 1,
- .enable_shift = 2,
- .enable_reg = UARTCLKCTRL_REG,
-};
-
-static struct clk uart6_ck = {
- .name = "uart6_ck",
- .parent = &per_ck,
- .flags = NEEDS_INITIALIZATION,
- .round_rate = &on_off_round_rate,
- .set_rate = &on_off_set_rate,
- .enable_shift = 3,
- .enable_reg = UARTCLKCTRL_REG,
-};
-
-static struct clk wdt_ck = {
- .name = "wdt_ck",
- .parent = &per_ck,
- .flags = NEEDS_INITIALIZATION,
- .enable_shift = 0,
- .enable_reg = TIMCLKCTRL_REG,
- .enable = clk_reg_enable,
- .disable = clk_reg_disable,
-};
-
-/* These clocks are visible outside this module
- * and can be initialized
- */
-static struct clk *onchip_clks[] __initdata = {
- &ck_13MHz,
- &ck_pll1,
- &ck_pll4,
- &ck_pll5,
- &ck_pll3,
- &vfp9_ck,
- &m2hclk_ck,
- &hclk_ck,
- &dma_ck,
- &flash_ck,
- &dum_ck,
- &keyscan_ck,
- &pwm1_ck,
- &pwm2_ck,
- &jpeg_ck,
- &ms_ck,
- &touch_ck,
- &i2c0_ck,
- &i2c1_ck,
- &i2c2_ck,
- &spi0_ck,
- &spi1_ck,
- &uart3_ck,
- &uart4_ck,
- &uart5_ck,
- &uart6_ck,
- &wdt_ck,
-};
-
-static struct clk_lookup onchip_clkreg[] = {
- { .clk = &ck_13MHz, .con_id = "ck_13MHz" },
- { .clk = &ck_pll1, .con_id = "ck_pll1" },
- { .clk = &ck_pll4, .con_id = "ck_pll4" },
- { .clk = &ck_pll5, .con_id = "ck_pll5" },
- { .clk = &ck_pll3, .con_id = "ck_pll3" },
- { .clk = &vfp9_ck, .con_id = "vfp9_ck" },
- { .clk = &m2hclk_ck, .con_id = "m2hclk_ck" },
- { .clk = &hclk_ck, .con_id = "hclk_ck" },
- { .clk = &dma_ck, .con_id = "dma_ck" },
- { .clk = &flash_ck, .con_id = "flash_ck" },
- { .clk = &dum_ck, .con_id = "dum_ck" },
- { .clk = &keyscan_ck, .con_id = "keyscan_ck" },
- { .clk = &pwm1_ck, .con_id = "pwm1_ck" },
- { .clk = &pwm2_ck, .con_id = "pwm2_ck" },
- { .clk = &jpeg_ck, .con_id = "jpeg_ck" },
- { .clk = &ms_ck, .con_id = "ms_ck" },
- { .clk = &touch_ck, .con_id = "touch_ck" },
- { .clk = &i2c0_ck, .dev_id = "pnx-i2c.0" },
- { .clk = &i2c1_ck, .dev_id = "pnx-i2c.1" },
- { .clk = &i2c2_ck, .dev_id = "pnx-i2c.2" },
- { .clk = &spi0_ck, .con_id = "spi0_ck" },
- { .clk = &spi1_ck, .con_id = "spi1_ck" },
- { .clk = &uart3_ck, .con_id = "uart3_ck" },
- { .clk = &uart4_ck, .con_id = "uart4_ck" },
- { .clk = &uart5_ck, .con_id = "uart5_ck" },
- { .clk = &uart6_ck, .con_id = "uart6_ck" },
- { .clk = &wdt_ck, .dev_id = "pnx4008-watchdog" },
-};
-
-static void local_clk_disable(struct clk *clk)
-{
- if (WARN_ON(clk->usecount == 0))
- return;
-
- if (!(--clk->usecount)) {
- if (clk->disable)
- clk->disable(clk);
- else if (!(clk->flags & FIXED_RATE) && clk->rate && clk->set_rate)
- clk->set_rate(clk, 0);
- if (clk->parent)
- local_clk_disable(clk->parent);
- }
-}
-
-static int local_clk_enable(struct clk *clk)
-{
- int ret = 0;
-
- if (clk->usecount == 0) {
- if (clk->parent) {
- ret = local_clk_enable(clk->parent);
- if (ret != 0)
- goto out;
- }
-
- if (clk->enable)
- ret = clk->enable(clk);
- else if (!(clk->flags & FIXED_RATE) && !clk->rate && clk->set_rate
- && clk->user_rate)
- ret = clk->set_rate(clk, clk->user_rate);
-
- if (ret != 0 && clk->parent) {
- local_clk_disable(clk->parent);
- goto out;
- }
-
- clk->usecount++;
- }
-out:
- return ret;
-}
-
-static int local_set_rate(struct clk *clk, u32 rate)
-{
- int ret = -EINVAL;
- if (clk->set_rate) {
-
- if (clk->user_rate == clk->rate && clk->parent->rate) {
- /* if clock enabled or rate not set */
- clk->user_rate = clk->round_rate(clk, rate);
- ret = clk->set_rate(clk, clk->user_rate);
- } else
- clk->user_rate = clk->round_rate(clk, rate);
- ret = 0;
- }
- return ret;
-}
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret = -EINVAL;
-
- if (clk->flags & FIXED_RATE)
- goto out;
-
- clock_lock();
- if ((clk->flags & PARENT_SET_RATE) && clk->parent) {
-
- clk->user_rate = clk->round_rate(clk, rate);
- /* parent clock needs to be refreshed
- for the setting to take effect */
- } else {
- ret = local_set_rate(clk, rate);
- }
- ret = 0;
- clock_unlock();
-
-out:
- return ret;
-}
-
-EXPORT_SYMBOL(clk_set_rate);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
- unsigned long ret;
- clock_lock();
- ret = clk->rate;
- clock_unlock();
- return ret;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-int clk_enable(struct clk *clk)
-{
- int ret;
-
- clock_lock();
- ret = local_clk_enable(clk);
- clock_unlock();
- return ret;
-}
-
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
- clock_lock();
- local_clk_disable(clk);
- clock_unlock();
-}
-
-EXPORT_SYMBOL(clk_disable);
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
- long ret;
- clock_lock();
- if (clk->round_rate)
- ret = clk->round_rate(clk, rate);
- else
- ret = clk->rate;
- clock_unlock();
- return ret;
-}
-
-EXPORT_SYMBOL(clk_round_rate);
-
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
- int ret = -ENODEV;
- if (!clk->set_parent)
- goto out;
-
- clock_lock();
- ret = clk->set_parent(clk, parent);
- if (!ret)
- clk->parent = parent;
- clock_unlock();
-
-out:
- return ret;
-}
-
-EXPORT_SYMBOL(clk_set_parent);
-
-static int __init clk_init(void)
-{
- struct clk **clkp;
-
- /* Disable autoclocking, as it doesn't seem to work */
- __raw_writel(0xff, AUTOCLK_CTRL);
-
- for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
- clkp++) {
- struct clk *clk = *clkp;
- if (clk->flags & NEEDS_INITIALIZATION) {
- if (clk->set_rate) {
- clk->user_rate = clk->rate;
- local_set_rate(clk, clk->user_rate);
- if (clk->set_parent)
- clk->set_parent(clk, clk->parent);
- }
- if (clk->enable && clk->usecount)
- clk->enable(clk);
- if (clk->disable && !clk->usecount)
- clk->disable(clk);
- }
- pr_debug("%s: clock %s, rate %ld\n",
- __func__, clk->name, clk->rate);
- }
-
- local_clk_enable(&ck_pll4);
-
- /* if ck_13MHz is not used, disable it. */
- if (ck_13MHz.usecount == 0)
- local_clk_disable(&ck_13MHz);
-
- /* Disable autoclocking */
- __raw_writeb(0xff, AUTOCLK_CTRL);
-
- clkdev_add_table(onchip_clkreg, ARRAY_SIZE(onchip_clkreg));
-
- return 0;
-}
-
-arch_initcall(clk_init);
diff --git a/arch/arm/mach-pnx4008/clock.h b/arch/arm/mach-pnx4008/clock.h
deleted file mode 100644
index 39720d6..0000000
--- a/arch/arm/mach-pnx4008/clock.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/clock.h
- *
- * Clock control driver for PNX4008 - internal header file
- *
- * Author: Vitaly Wool <source@mvista.com>
- *
- * 2006 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __ARCH_ARM_PNX4008_CLOCK_H__
-#define __ARCH_ARM_PNX4008_CLOCK_H__
-
-struct clk {
- const char *name;
- struct clk *parent;
- struct clk *propagate_next;
- u32 rate;
- u32 user_rate;
- s8 usecount;
- u32 flags;
- u32 scale_reg;
- u8 enable_shift;
- u32 enable_reg;
- u8 enable_shift1;
- u32 enable_reg1;
- u32 parent_switch_reg;
- u32(*round_rate) (struct clk *, u32);
- int (*set_rate) (struct clk *, u32);
- int (*set_parent) (struct clk * clk, struct clk * parent);
- int (*enable)(struct clk *);
- void (*disable)(struct clk *);
-};
-
-/* Flags */
-#define RATE_PROPAGATES (1<<0)
-#define NEEDS_INITIALIZATION (1<<1)
-#define PARENT_SET_RATE (1<<2)
-#define FIXED_RATE (1<<3)
-
-#endif
diff --git a/arch/arm/mach-pnx4008/core.c b/arch/arm/mach-pnx4008/core.c
deleted file mode 100644
index a00d2f1..0000000
--- a/arch/arm/mach-pnx4008/core.c
+++ /dev/null
@@ -1,290 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/core.c
- *
- * PNX4008 core startup code
- *
- * Authors: Vitaly Wool, Dmitry Chigirev,
- * Grigory Tolstolytkin, Dmitry Pervushin <source@mvista.com>
- *
- * Based on reference code received from Philips:
- * Copyright (C) 2003 Philips Semiconductors
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/mm.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/serial_8250.h>
-#include <linux/device.h>
-#include <linux/spi/spi.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/system_misc.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
-
-#include <mach/irq.h>
-#include <mach/clock.h>
-#include <mach/dma.h>
-
-struct resource spipnx_0_resources[] = {
- {
- .start = PNX4008_SPI1_BASE,
- .end = PNX4008_SPI1_BASE + SZ_4K,
- .flags = IORESOURCE_MEM,
- }, {
- .start = PER_SPI1_REC_XMIT,
- .flags = IORESOURCE_DMA,
- }, {
- .start = SPI1_INT,
- .flags = IORESOURCE_IRQ,
- }, {
- .flags = 0,
- },
-};
-
-struct resource spipnx_1_resources[] = {
- {
- .start = PNX4008_SPI2_BASE,
- .end = PNX4008_SPI2_BASE + SZ_4K,
- .flags = IORESOURCE_MEM,
- }, {
- .start = PER_SPI2_REC_XMIT,
- .flags = IORESOURCE_DMA,
- }, {
- .start = SPI2_INT,
- .flags = IORESOURCE_IRQ,
- }, {
- .flags = 0,
- }
-};
-
-static struct spi_board_info spi_board_info[] __initdata = {
- {
- .modalias = "m25p80",
- .max_speed_hz = 1000000,
- .bus_num = 1,
- .chip_select = 0,
- },
-};
-
-static struct platform_device spipnx_1 = {
- .name = "spipnx",
- .id = 1,
- .num_resources = ARRAY_SIZE(spipnx_0_resources),
- .resource = spipnx_0_resources,
- .dev = {
- .coherent_dma_mask = 0xFFFFFFFF,
- },
-};
-
-static struct platform_device spipnx_2 = {
- .name = "spipnx",
- .id = 2,
- .num_resources = ARRAY_SIZE(spipnx_1_resources),
- .resource = spipnx_1_resources,
- .dev = {
- .coherent_dma_mask = 0xFFFFFFFF,
- },
-};
-
-static struct plat_serial8250_port platform_serial_ports[] = {
- {
- .membase = (void *)__iomem(IO_ADDRESS(PNX4008_UART5_BASE)),
- .mapbase = (unsigned long)PNX4008_UART5_BASE,
- .irq = IIR5_INT,
- .uartclk = PNX4008_UART_CLK,
- .regshift = 2,
- .iotype = UPIO_MEM,
- .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | UPF_SKIP_TEST,
- },
- {
- .membase = (void *)__iomem(IO_ADDRESS(PNX4008_UART3_BASE)),
- .mapbase = (unsigned long)PNX4008_UART3_BASE,
- .irq = IIR3_INT,
- .uartclk = PNX4008_UART_CLK,
- .regshift = 2,
- .iotype = UPIO_MEM,
- .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | UPF_SKIP_TEST,
- },
- {}
-};
-
-static struct platform_device serial_device = {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM,
- .dev = {
- .platform_data = &platform_serial_ports,
- },
-};
-
-static struct platform_device nand_flash_device = {
- .name = "pnx4008-flash",
- .id = -1,
- .dev = {
- .coherent_dma_mask = 0xFFFFFFFF,
- },
-};
-
-/* The dmamask must be set for OHCI to work */
-static u64 ohci_dmamask = ~(u32) 0;
-
-static struct resource ohci_resources[] = {
- {
- .start = IO_ADDRESS(PNX4008_USB_CONFIG_BASE),
- .end = IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0x100),
- .flags = IORESOURCE_MEM,
- }, {
- .start = USB_HOST_INT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device ohci_device = {
- .name = "pnx4008-usb-ohci",
- .id = -1,
- .dev = {
- .dma_mask = &ohci_dmamask,
- .coherent_dma_mask = 0xffffffff,
- },
- .num_resources = ARRAY_SIZE(ohci_resources),
- .resource = ohci_resources,
-};
-
-static struct platform_device sdum_device = {
- .name = "pnx4008-sdum",
- .id = 0,
- .dev = {
- .coherent_dma_mask = 0xffffffff,
- },
-};
-
-static struct platform_device rgbfb_device = {
- .name = "pnx4008-rgbfb",
- .id = 0,
- .dev = {
- .coherent_dma_mask = 0xffffffff,
- }
-};
-
-struct resource watchdog_resources[] = {
- {
- .start = PNX4008_WDOG_BASE,
- .end = PNX4008_WDOG_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device watchdog_device = {
- .name = "pnx4008-watchdog",
- .id = -1,
- .num_resources = ARRAY_SIZE(watchdog_resources),
- .resource = watchdog_resources,
-};
-
-static struct platform_device *devices[] __initdata = {
- &spipnx_1,
- &spipnx_2,
- &serial_device,
- &ohci_device,
- &nand_flash_device,
- &sdum_device,
- &rgbfb_device,
- &watchdog_device,
-};
-
-
-extern void pnx4008_uart_init(void);
-
-static void __init pnx4008_init(void)
-{
- /*disable all START interrupt sources,
- and clear all START interrupt flags */
- __raw_writel(0, START_INT_ER_REG(SE_PIN_BASE_INT));
- __raw_writel(0, START_INT_ER_REG(SE_INT_BASE_INT));
- __raw_writel(0xffffffff, START_INT_RSR_REG(SE_PIN_BASE_INT));
- __raw_writel(0xffffffff, START_INT_RSR_REG(SE_INT_BASE_INT));
-
- platform_add_devices(devices, ARRAY_SIZE(devices));
- spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
- /* Switch on the UART clocks */
- pnx4008_uart_init();
-}
-
-static struct map_desc pnx4008_io_desc[] __initdata = {
- {
- .virtual = IO_ADDRESS(PNX4008_IRAM_BASE),
- .pfn = __phys_to_pfn(PNX4008_IRAM_BASE),
- .length = SZ_64K,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(PNX4008_NDF_FLASH_BASE),
- .pfn = __phys_to_pfn(PNX4008_NDF_FLASH_BASE),
- .length = SZ_1M - SZ_128K,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(PNX4008_JPEG_CONFIG_BASE),
- .pfn = __phys_to_pfn(PNX4008_JPEG_CONFIG_BASE),
- .length = SZ_128K * 3,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(PNX4008_DMA_CONFIG_BASE),
- .pfn = __phys_to_pfn(PNX4008_DMA_CONFIG_BASE),
- .length = SZ_1M,
- .type = MT_DEVICE,
- }, {
- .virtual = IO_ADDRESS(PNX4008_AHB2FAB_BASE),
- .pfn = __phys_to_pfn(PNX4008_AHB2FAB_BASE),
- .length = SZ_1M,
- .type = MT_DEVICE,
- },
-};
-
-void __init pnx4008_map_io(void)
-{
- iotable_init(pnx4008_io_desc, ARRAY_SIZE(pnx4008_io_desc));
-}
-
-static void pnx4008_restart(char mode, const char *cmd)
-{
- soft_restart(0);
-}
-
-#ifdef CONFIG_PM
-extern int pnx4008_pm_init(void);
-#else
-static inline int pnx4008_pm_init(void) { return 0; }
-#endif
-
-void __init pnx4008_init_late(void)
-{
- pnx4008_pm_init();
-}
-
-extern struct sys_timer pnx4008_timer;
-
-MACHINE_START(PNX4008, "Philips PNX4008")
- /* Maintainer: MontaVista Software Inc. */
- .atag_offset = 0x100,
- .map_io = pnx4008_map_io,
- .init_irq = pnx4008_init_irq,
- .init_machine = pnx4008_init,
- .init_late = pnx4008_init_late,
- .timer = &pnx4008_timer,
- .restart = pnx4008_restart,
-MACHINE_END
diff --git a/arch/arm/mach-pnx4008/dma.c b/arch/arm/mach-pnx4008/dma.c
deleted file mode 100644
index a4739e9..0000000
--- a/arch/arm/mach-pnx4008/dma.c
+++ /dev/null
@@ -1,1105 +0,0 @@
-/*
- * linux/arch/arm/mach-pnx4008/dma.c
- *
- * PNX4008 DMA registration and IRQ dispatching
- *
- * Author: Vitaly Wool
- * Copyright: MontaVista Software Inc. (c) 2005
- *
- * Based on the code from Nicolas Pitre
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/interrupt.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/dma-mapping.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/gfp.h>
-
-#include <mach/hardware.h>
-#include <mach/dma.h>
-#include <asm/dma-mapping.h>
-#include <mach/clock.h>
-
-static struct dma_channel {
- char *name;
- void (*irq_handler) (int, int, void *);
- void *data;
- struct pnx4008_dma_ll *ll;
- u32 ll_dma;
- void *target_addr;
- int target_id;
-} dma_channels[MAX_DMA_CHANNELS];
-
-static struct ll_pool {
- void *vaddr;
- void *cur;
- dma_addr_t dma_addr;
- int count;
-} ll_pool;
-
-static DEFINE_SPINLOCK(ll_lock);
-
-struct pnx4008_dma_ll *pnx4008_alloc_ll_entry(dma_addr_t * ll_dma)
-{
- struct pnx4008_dma_ll *ll = NULL;
- unsigned long flags;
-
- spin_lock_irqsave(&ll_lock, flags);
- if (ll_pool.count > 4) { /* can give one more */
- ll = *(struct pnx4008_dma_ll **) ll_pool.cur;
- *ll_dma = ll_pool.dma_addr + ((void *)ll - ll_pool.vaddr);
- *(void **)ll_pool.cur = **(void ***)ll_pool.cur;
- memset(ll, 0, sizeof(*ll));
- ll_pool.count--;
- }
- spin_unlock_irqrestore(&ll_lock, flags);
-
- return ll;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_alloc_ll_entry);
-
-void pnx4008_free_ll_entry(struct pnx4008_dma_ll * ll, dma_addr_t ll_dma)
-{
- unsigned long flags;
-
- if (ll) {
- if ((unsigned long)((long)ll - (long)ll_pool.vaddr) > 0x4000) {
- printk(KERN_ERR "Trying to free entry not allocated by DMA\n");
- BUG();
- }
-
- if (ll->flags & DMA_BUFFER_ALLOCATED)
- ll->free(ll->alloc_data);
-
- spin_lock_irqsave(&ll_lock, flags);
- *(long *)ll = *(long *)ll_pool.cur;
- *(long *)ll_pool.cur = (long)ll;
- ll_pool.count++;
- spin_unlock_irqrestore(&ll_lock, flags);
- }
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_free_ll_entry);
-
-void pnx4008_free_ll(u32 ll_dma, struct pnx4008_dma_ll * ll)
-{
- struct pnx4008_dma_ll *ptr;
- u32 dma;
-
- while (ll) {
- dma = ll->next_dma;
- ptr = ll->next;
- pnx4008_free_ll_entry(ll, ll_dma);
-
- ll_dma = dma;
- ll = ptr;
- }
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_free_ll);
-
-static int dma_channels_requested = 0;
-
-static inline void dma_increment_usage(void)
-{
- if (!dma_channels_requested++) {
- struct clk *clk = clk_get(0, "dma_ck");
- if (!IS_ERR(clk)) {
- clk_set_rate(clk, 1);
- clk_put(clk);
- }
- pnx4008_config_dma(-1, -1, 1);
- }
-}
-static inline void dma_decrement_usage(void)
-{
- if (!--dma_channels_requested) {
- struct clk *clk = clk_get(0, "dma_ck");
- if (!IS_ERR(clk)) {
- clk_set_rate(clk, 0);
- clk_put(clk);
- }
- pnx4008_config_dma(-1, -1, 0);
-
- }
-}
-
-static DEFINE_SPINLOCK(dma_lock);
-
-static inline void pnx4008_dma_lock(void)
-{
- spin_lock_irq(&dma_lock);
-}
-
-static inline void pnx4008_dma_unlock(void)
-{
- spin_unlock_irq(&dma_lock);
-}
-
-#define VALID_CHANNEL(c) (((c) >= 0) && ((c) < MAX_DMA_CHANNELS))
-
-int pnx4008_request_channel(char *name, int ch,
- void (*irq_handler) (int, int, void *), void *data)
-{
- int i, found = 0;
-
- /* basic sanity checks */
- if (!name || (ch != -1 && !VALID_CHANNEL(ch)))
- return -EINVAL;
-
- pnx4008_dma_lock();
-
- /* try grabbing a DMA channel with the requested priority */
- for (i = MAX_DMA_CHANNELS - 1; i >= 0; i--) {
- if (!dma_channels[i].name && (ch == -1 || ch == i)) {
- found = 1;
- break;
- }
- }
-
- if (found) {
- dma_increment_usage();
- dma_channels[i].name = name;
- dma_channels[i].irq_handler = irq_handler;
- dma_channels[i].data = data;
- dma_channels[i].ll = NULL;
- dma_channels[i].ll_dma = 0;
- } else {
- printk(KERN_WARNING "No more available DMA channels for %s\n",
- name);
- i = -ENODEV;
- }
-
- pnx4008_dma_unlock();
- return i;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_request_channel);
-
-void pnx4008_free_channel(int ch)
-{
- if (!dma_channels[ch].name) {
- printk(KERN_CRIT
- "%s: trying to free channel %d which is already freed\n",
- __func__, ch);
- return;
- }
-
- pnx4008_dma_lock();
- pnx4008_free_ll(dma_channels[ch].ll_dma, dma_channels[ch].ll);
- dma_channels[ch].ll = NULL;
- dma_decrement_usage();
-
- dma_channels[ch].name = NULL;
- pnx4008_dma_unlock();
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_free_channel);
-
-int pnx4008_config_dma(int ahb_m1_be, int ahb_m2_be, int enable)
-{
- unsigned long dma_cfg = __raw_readl(DMAC_CONFIG);
-
- switch (ahb_m1_be) {
- case 0:
- dma_cfg &= ~(1 << 1);
- break;
- case 1:
- dma_cfg |= (1 << 1);
- break;
- default:
- break;
- }
-
- switch (ahb_m2_be) {
- case 0:
- dma_cfg &= ~(1 << 2);
- break;
- case 1:
- dma_cfg |= (1 << 2);
- break;
- default:
- break;
- }
-
- switch (enable) {
- case 0:
- dma_cfg &= ~(1 << 0);
- break;
- case 1:
- dma_cfg |= (1 << 0);
- break;
- default:
- break;
- }
-
- pnx4008_dma_lock();
- __raw_writel(dma_cfg, DMAC_CONFIG);
- pnx4008_dma_unlock();
-
- return 0;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_config_dma);
-
-int pnx4008_dma_pack_control(const struct pnx4008_dma_ch_ctrl * ch_ctrl,
- unsigned long *ctrl)
-{
- int i = 0, dbsize, sbsize, err = 0;
-
- if (!ctrl || !ch_ctrl) {
- err = -EINVAL;
- goto out;
- }
-
- *ctrl = 0;
-
- switch (ch_ctrl->tc_mask) {
- case 0:
- break;
- case 1:
- *ctrl |= (1 << 31);
- break;
-
- default:
- err = -EINVAL;
- goto out;
- }
-
- switch (ch_ctrl->cacheable) {
- case 0:
- break;
- case 1:
- *ctrl |= (1 << 30);
- break;
-
- default:
- err = -EINVAL;
- goto out;
- }
- switch (ch_ctrl->bufferable) {
- case 0:
- break;
- case 1:
- *ctrl |= (1 << 29);
- break;
-
- default:
- err = -EINVAL;
- goto out;
- }
- switch (ch_ctrl->priv_mode) {
- case 0:
- break;
- case 1:
- *ctrl |= (1 << 28);
- break;
-
- default:
- err = -EINVAL;
- goto out;
- }
- switch (ch_ctrl->di) {
- case 0:
- break;
- case 1:
- *ctrl |= (1 << 27);
- break;
-
- default:
- err = -EINVAL;
- goto out;
- }
- switch (ch_ctrl->si) {
- case 0:
- break;
- case 1:
- *ctrl |= (1 << 26);
- break;
-
- default:
- err = -EINVAL;
- goto out;
- }
- switch (ch_ctrl->dest_ahb1) {
- case 0:
- break;
- case 1:
- *ctrl |= (1 << 25);
- break;
-
- default:
- err = -EINVAL;
- goto out;
- }
- switch (ch_ctrl->src_ahb1) {
- case 0:
- break;
- case 1:
- *ctrl |= (1 << 24);
- break;
-
- default:
- err = -EINVAL;
- goto out;
- }
- switch (ch_ctrl->dwidth) {
- case WIDTH_BYTE:
- *ctrl &= ~(7 << 21);
- break;
- case WIDTH_HWORD:
- *ctrl &= ~(7 << 21);
- *ctrl |= (1 << 21);
- break;
- case WIDTH_WORD:
- *ctrl &= ~(7 << 21);
- *ctrl |= (2 << 21);
- break;
-
- default:
- err = -EINVAL;
- goto out;
- }
- switch (ch_ctrl->swidth) {
- case WIDTH_BYTE:
- *ctrl &= ~(7 << 18);
- break;
- case WIDTH_HWORD:
- *ctrl &= ~(7 << 18);
- *ctrl |= (1 << 18);
- break;
- case WIDTH_WORD:
- *ctrl &= ~(7 << 18);
- *ctrl |= (2 << 18);
- break;
-
- default:
- err = -EINVAL;
- goto out;
- }
- dbsize = ch_ctrl->dbsize;
- while (!(dbsize & 1)) {
- i++;
- dbsize >>= 1;
- }
- if (ch_ctrl->dbsize != 1 || i > 8 || i == 1) {
- err = -EINVAL;
- goto out;
- } else if (i > 1)
- i--;
- *ctrl &= ~(7 << 15);
- *ctrl |= (i << 15);
-
- sbsize = ch_ctrl->sbsize;
- while (!(sbsize & 1)) {
- i++;
- sbsize >>= 1;
- }
- if (ch_ctrl->sbsize != 1 || i > 8 || i == 1) {
- err = -EINVAL;
- goto out;
- } else if (i > 1)
- i--;
- *ctrl &= ~(7 << 12);
- *ctrl |= (i << 12);
-
- if (ch_ctrl->tr_size > 0x7ff) {
- err = -E2BIG;
- goto out;
- }
- *ctrl &= ~0x7ff;
- *ctrl |= ch_ctrl->tr_size & 0x7ff;
-
-out:
- return err;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_pack_control);
-
-int pnx4008_dma_parse_control(unsigned long ctrl,
- struct pnx4008_dma_ch_ctrl * ch_ctrl)
-{
- int err = 0;
-
- if (!ch_ctrl) {
- err = -EINVAL;
- goto out;
- }
-
- ch_ctrl->tr_size = ctrl & 0x7ff;
- ctrl >>= 12;
-
- ch_ctrl->sbsize = 1 << (ctrl & 7);
- if (ch_ctrl->sbsize > 1)
- ch_ctrl->sbsize <<= 1;
- ctrl >>= 3;
-
- ch_ctrl->dbsize = 1 << (ctrl & 7);
- if (ch_ctrl->dbsize > 1)
- ch_ctrl->dbsize <<= 1;
- ctrl >>= 3;
-
- switch (ctrl & 7) {
- case 0:
- ch_ctrl->swidth = WIDTH_BYTE;
- break;
- case 1:
- ch_ctrl->swidth = WIDTH_HWORD;
- break;
- case 2:
- ch_ctrl->swidth = WIDTH_WORD;
- break;
- default:
- err = -EINVAL;
- goto out;
- }
- ctrl >>= 3;
-
- switch (ctrl & 7) {
- case 0:
- ch_ctrl->dwidth = WIDTH_BYTE;
- break;
- case 1:
- ch_ctrl->dwidth = WIDTH_HWORD;
- break;
- case 2:
- ch_ctrl->dwidth = WIDTH_WORD;
- break;
- default:
- err = -EINVAL;
- goto out;
- }
- ctrl >>= 3;
-
- ch_ctrl->src_ahb1 = ctrl & 1;
- ctrl >>= 1;
-
- ch_ctrl->dest_ahb1 = ctrl & 1;
- ctrl >>= 1;
-
- ch_ctrl->si = ctrl & 1;
- ctrl >>= 1;
-
- ch_ctrl->di = ctrl & 1;
- ctrl >>= 1;
-
- ch_ctrl->priv_mode = ctrl & 1;
- ctrl >>= 1;
-
- ch_ctrl->bufferable = ctrl & 1;
- ctrl >>= 1;
-
- ch_ctrl->cacheable = ctrl & 1;
- ctrl >>= 1;
-
- ch_ctrl->tc_mask = ctrl & 1;
-
-out:
- return err;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_parse_control);
-
-int pnx4008_dma_pack_config(const struct pnx4008_dma_ch_config * ch_cfg,
- unsigned long *cfg)
-{
- int err = 0;
-
- if (!cfg || !ch_cfg) {
- err = -EINVAL;
- goto out;
- }
-
- *cfg = 0;
-
- switch (ch_cfg->halt) {
- case 0:
- break;
- case 1:
- *cfg |= (1 << 18);
- break;
-
- default:
- err = -EINVAL;
- goto out;
- }
- switch (ch_cfg->active) {
- case 0:
- break;
- case 1:
- *cfg |= (1 << 17);
- break;
-
- default:
- err = -EINVAL;
- goto out;
- }
- switch (ch_cfg->lock) {
- case 0:
- break;
- case 1:
- *cfg |= (1 << 16);
- break;
-
- default:
- err = -EINVAL;
- goto out;
- }
- switch (ch_cfg->itc) {
- case 0:
- break;
- case 1:
- *cfg |= (1 << 15);
- break;
-
- default:
- err = -EINVAL;
- goto out;
- }
- switch (ch_cfg->ie) {
- case 0:
- break;
- case 1:
- *cfg |= (1 << 14);
- break;
-
- default:
- err = -EINVAL;
- goto out;
- }
- switch (ch_cfg->flow_cntrl) {
- case FC_MEM2MEM_DMA:
- *cfg &= ~(7 << 11);
- break;
- case FC_MEM2PER_DMA:
- *cfg &= ~(7 << 11);
- *cfg |= (1 << 11);
- break;
- case FC_PER2MEM_DMA:
- *cfg &= ~(7 << 11);
- *cfg |= (2 << 11);
- break;
- case FC_PER2PER_DMA:
- *cfg &= ~(7 << 11);
- *cfg |= (3 << 11);
- break;
- case FC_PER2PER_DPER:
- *cfg &= ~(7 << 11);
- *cfg |= (4 << 11);
- break;
- case FC_MEM2PER_PER:
- *cfg &= ~(7 << 11);
- *cfg |= (5 << 11);
- break;
- case FC_PER2MEM_PER:
- *cfg &= ~(7 << 11);
- *cfg |= (6 << 11);
- break;
- case FC_PER2PER_SPER:
- *cfg |= (7 << 11);
- break;
-
- default:
- err = -EINVAL;
- goto out;
- }
- *cfg &= ~(0x1f << 6);
- *cfg |= ((ch_cfg->dest_per & 0x1f) << 6);
-
- *cfg &= ~(0x1f << 1);
- *cfg |= ((ch_cfg->src_per & 0x1f) << 1);
-
-out:
- return err;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_pack_config);
-
-int pnx4008_dma_parse_config(unsigned long cfg,
- struct pnx4008_dma_ch_config * ch_cfg)
-{
- int err = 0;
-
- if (!ch_cfg) {
- err = -EINVAL;
- goto out;
- }
-
- cfg >>= 1;
-
- ch_cfg->src_per = cfg & 0x1f;
- cfg >>= 5;
-
- ch_cfg->dest_per = cfg & 0x1f;
- cfg >>= 5;
-
- switch (cfg & 7) {
- case 0:
- ch_cfg->flow_cntrl = FC_MEM2MEM_DMA;
- break;
- case 1:
- ch_cfg->flow_cntrl = FC_MEM2PER_DMA;
- break;
- case 2:
- ch_cfg->flow_cntrl = FC_PER2MEM_DMA;
- break;
- case 3:
- ch_cfg->flow_cntrl = FC_PER2PER_DMA;
- break;
- case 4:
- ch_cfg->flow_cntrl = FC_PER2PER_DPER;
- break;
- case 5:
- ch_cfg->flow_cntrl = FC_MEM2PER_PER;
- break;
- case 6:
- ch_cfg->flow_cntrl = FC_PER2MEM_PER;
- break;
- case 7:
- ch_cfg->flow_cntrl = FC_PER2PER_SPER;
- }
- cfg >>= 3;
-
- ch_cfg->ie = cfg & 1;
- cfg >>= 1;
-
- ch_cfg->itc = cfg & 1;
- cfg >>= 1;
-
- ch_cfg->lock = cfg & 1;
- cfg >>= 1;
-
- ch_cfg->active = cfg & 1;
- cfg >>= 1;
-
- ch_cfg->halt = cfg & 1;
-
-out:
- return err;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_parse_config);
-
-void pnx4008_dma_split_head_entry(struct pnx4008_dma_config * config,
- struct pnx4008_dma_ch_ctrl * ctrl)
-{
- int new_len = ctrl->tr_size, num_entries = 0;
- int old_len = new_len;
- int src_width, dest_width, count = 1;
-
- switch (ctrl->swidth) {
- case WIDTH_BYTE:
- src_width = 1;
- break;
- case WIDTH_HWORD:
- src_width = 2;
- break;
- case WIDTH_WORD:
- src_width = 4;
- break;
- default:
- return;
- }
-
- switch (ctrl->dwidth) {
- case WIDTH_BYTE:
- dest_width = 1;
- break;
- case WIDTH_HWORD:
- dest_width = 2;
- break;
- case WIDTH_WORD:
- dest_width = 4;
- break;
- default:
- return;
- }
-
- while (new_len > 0x7FF) {
- num_entries++;
- new_len = (ctrl->tr_size + num_entries) / (num_entries + 1);
- }
- if (num_entries != 0) {
- struct pnx4008_dma_ll *ll = NULL;
- config->ch_ctrl &= ~0x7ff;
- config->ch_ctrl |= new_len;
- if (!config->is_ll) {
- config->is_ll = 1;
- while (num_entries) {
- if (!ll) {
- config->ll =
- pnx4008_alloc_ll_entry(&config->
- ll_dma);
- ll = config->ll;
- } else {
- ll->next =
- pnx4008_alloc_ll_entry(&ll->
- next_dma);
- ll = ll->next;
- }
-
- if (ctrl->si)
- ll->src_addr =
- config->src_addr +
- src_width * new_len * count;
- else
- ll->src_addr = config->src_addr;
- if (ctrl->di)
- ll->dest_addr =
- config->dest_addr +
- dest_width * new_len * count;
- else
- ll->dest_addr = config->dest_addr;
- ll->ch_ctrl = config->ch_ctrl & 0x7fffffff;
- ll->next_dma = 0;
- ll->next = NULL;
- num_entries--;
- count++;
- }
- } else {
- struct pnx4008_dma_ll *ll_old = config->ll;
- unsigned long ll_dma_old = config->ll_dma;
- while (num_entries) {
- if (!ll) {
- config->ll =
- pnx4008_alloc_ll_entry(&config->
- ll_dma);
- ll = config->ll;
- } else {
- ll->next =
- pnx4008_alloc_ll_entry(&ll->
- next_dma);
- ll = ll->next;
- }
-
- if (ctrl->si)
- ll->src_addr =
- config->src_addr +
- src_width * new_len * count;
- else
- ll->src_addr = config->src_addr;
- if (ctrl->di)
- ll->dest_addr =
- config->dest_addr +
- dest_width * new_len * count;
- else
- ll->dest_addr = config->dest_addr;
- ll->ch_ctrl = config->ch_ctrl & 0x7fffffff;
- ll->next_dma = 0;
- ll->next = NULL;
- num_entries--;
- count++;
- }
- ll->next_dma = ll_dma_old;
- ll->next = ll_old;
- }
- /* adjust last length/tc */
- ll->ch_ctrl = config->ch_ctrl & (~0x7ff);
- ll->ch_ctrl |= old_len - new_len * (count - 1);
- config->ch_ctrl &= 0x7fffffff;
- }
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_split_head_entry);
-
-void pnx4008_dma_split_ll_entry(struct pnx4008_dma_ll * cur_ll,
- struct pnx4008_dma_ch_ctrl * ctrl)
-{
- int new_len = ctrl->tr_size, num_entries = 0;
- int old_len = new_len;
- int src_width, dest_width, count = 1;
-
- switch (ctrl->swidth) {
- case WIDTH_BYTE:
- src_width = 1;
- break;
- case WIDTH_HWORD:
- src_width = 2;
- break;
- case WIDTH_WORD:
- src_width = 4;
- break;
- default:
- return;
- }
-
- switch (ctrl->dwidth) {
- case WIDTH_BYTE:
- dest_width = 1;
- break;
- case WIDTH_HWORD:
- dest_width = 2;
- break;
- case WIDTH_WORD:
- dest_width = 4;
- break;
- default:
- return;
- }
-
- while (new_len > 0x7FF) {
- num_entries++;
- new_len = (ctrl->tr_size + num_entries) / (num_entries + 1);
- }
- if (num_entries != 0) {
- struct pnx4008_dma_ll *ll = NULL;
- cur_ll->ch_ctrl &= ~0x7ff;
- cur_ll->ch_ctrl |= new_len;
- if (!cur_ll->next) {
- while (num_entries) {
- if (!ll) {
- cur_ll->next =
- pnx4008_alloc_ll_entry(&cur_ll->
- next_dma);
- ll = cur_ll->next;
- } else {
- ll->next =
- pnx4008_alloc_ll_entry(&ll->
- next_dma);
- ll = ll->next;
- }
-
- if (ctrl->si)
- ll->src_addr =
- cur_ll->src_addr +
- src_width * new_len * count;
- else
- ll->src_addr = cur_ll->src_addr;
- if (ctrl->di)
- ll->dest_addr =
- cur_ll->dest_addr +
- dest_width * new_len * count;
- else
- ll->dest_addr = cur_ll->dest_addr;
- ll->ch_ctrl = cur_ll->ch_ctrl & 0x7fffffff;
- ll->next_dma = 0;
- ll->next = NULL;
- num_entries--;
- count++;
- }
- } else {
- struct pnx4008_dma_ll *ll_old = cur_ll->next;
- unsigned long ll_dma_old = cur_ll->next_dma;
- while (num_entries) {
- if (!ll) {
- cur_ll->next =
- pnx4008_alloc_ll_entry(&cur_ll->
- next_dma);
- ll = cur_ll->next;
- } else {
- ll->next =
- pnx4008_alloc_ll_entry(&ll->
- next_dma);
- ll = ll->next;
- }
-
- if (ctrl->si)
- ll->src_addr =
- cur_ll->src_addr +
- src_width * new_len * count;
- else
- ll->src_addr = cur_ll->src_addr;
- if (ctrl->di)
- ll->dest_addr =
- cur_ll->dest_addr +
- dest_width * new_len * count;
- else
- ll->dest_addr = cur_ll->dest_addr;
- ll->ch_ctrl = cur_ll->ch_ctrl & 0x7fffffff;
- ll->next_dma = 0;
- ll->next = NULL;
- num_entries--;
- count++;
- }
-
- ll->next_dma = ll_dma_old;
- ll->next = ll_old;
- }
- /* adjust last length/tc */
- ll->ch_ctrl = cur_ll->ch_ctrl & (~0x7ff);
- ll->ch_ctrl |= old_len - new_len * (count - 1);
- cur_ll->ch_ctrl &= 0x7fffffff;
- }
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_split_ll_entry);
-
-int pnx4008_config_channel(int ch, struct pnx4008_dma_config * config)
-{
- if (!VALID_CHANNEL(ch) || !dma_channels[ch].name)
- return -EINVAL;
-
- pnx4008_dma_lock();
- __raw_writel(config->src_addr, DMAC_Cx_SRC_ADDR(ch));
- __raw_writel(config->dest_addr, DMAC_Cx_DEST_ADDR(ch));
-
- if (config->is_ll)
- __raw_writel(config->ll_dma, DMAC_Cx_LLI(ch));
- else
- __raw_writel(0, DMAC_Cx_LLI(ch));
-
- __raw_writel(config->ch_ctrl, DMAC_Cx_CONTROL(ch));
- __raw_writel(config->ch_cfg, DMAC_Cx_CONFIG(ch));
- pnx4008_dma_unlock();
-
- return 0;
-
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_config_channel);
-
-int pnx4008_channel_get_config(int ch, struct pnx4008_dma_config * config)
-{
- if (!VALID_CHANNEL(ch) || !dma_channels[ch].name || !config)
- return -EINVAL;
-
- pnx4008_dma_lock();
- config->ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch));
- config->ch_ctrl = __raw_readl(DMAC_Cx_CONTROL(ch));
-
- config->ll_dma = __raw_readl(DMAC_Cx_LLI(ch));
- config->is_ll = config->ll_dma ? 1 : 0;
-
- config->src_addr = __raw_readl(DMAC_Cx_SRC_ADDR(ch));
- config->dest_addr = __raw_readl(DMAC_Cx_DEST_ADDR(ch));
- pnx4008_dma_unlock();
-
- return 0;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_channel_get_config);
-
-int pnx4008_dma_ch_enable(int ch)
-{
- unsigned long ch_cfg;
-
- if (!VALID_CHANNEL(ch) || !dma_channels[ch].name)
- return -EINVAL;
-
- pnx4008_dma_lock();
- ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch));
- ch_cfg |= 1;
- __raw_writel(ch_cfg, DMAC_Cx_CONFIG(ch));
- pnx4008_dma_unlock();
-
- return 0;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_ch_enable);
-
-int pnx4008_dma_ch_disable(int ch)
-{
- unsigned long ch_cfg;
-
- if (!VALID_CHANNEL(ch) || !dma_channels[ch].name)
- return -EINVAL;
-
- pnx4008_dma_lock();
- ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch));
- ch_cfg &= ~1;
- __raw_writel(ch_cfg, DMAC_Cx_CONFIG(ch));
- pnx4008_dma_unlock();
-
- return 0;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_ch_disable);
-
-int pnx4008_dma_ch_enabled(int ch)
-{
- unsigned long ch_cfg;
-
- if (!VALID_CHANNEL(ch) || !dma_channels[ch].name)
- return -EINVAL;
-
- pnx4008_dma_lock();
- ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch));
- pnx4008_dma_unlock();
-
- return ch_cfg & 1;
-}
-
-EXPORT_SYMBOL_GPL(pnx4008_dma_ch_enabled);
-
-static irqreturn_t dma_irq_handler(int irq, void *dev_id)
-{
- int i;
- unsigned long dint = __raw_readl(DMAC_INT_STAT);
- unsigned long tcint = __raw_readl(DMAC_INT_TC_STAT);
- unsigned long eint = __raw_readl(DMAC_INT_ERR_STAT);
- unsigned long i_bit;
-
- for (i = MAX_DMA_CHANNELS - 1; i >= 0; i--) {
- i_bit = 1 << i;
- if (dint & i_bit) {
- struct dma_channel *channel = &dma_channels[i];
-
- if (channel->name && channel->irq_handler) {
- int cause = 0;
-
- if (eint & i_bit)
- cause |= DMA_ERR_INT;
- if (tcint & i_bit)
- cause |= DMA_TC_INT;
- channel->irq_handler(i, cause, channel->data);
- } else {
- /*
- * IRQ for an unregistered DMA channel
- */
- printk(KERN_WARNING
- "spurious IRQ for DMA channel %d\n", i);
- }
- if (tcint & i_bit)
- __raw_writel(i_bit, DMAC_INT_TC_CLEAR);
- if (eint & i_bit)
- __raw_writel(i_bit, DMAC_INT_ERR_CLEAR);
- }
- }
- return IRQ_HANDLED;
-}
-
-static int __init pnx4008_dma_init(void)
-{
- int ret, i;
-
- ret = request_irq(DMA_INT, dma_irq_handler, 0, "DMA", NULL);
- if (ret) {
- printk(KERN_CRIT "Wow! Can't register IRQ for DMA\n");
- goto out;
- }
-
- ll_pool.count = 0x4000 / sizeof(struct pnx4008_dma_ll);
- ll_pool.cur = ll_pool.vaddr =
- dma_alloc_coherent(NULL, ll_pool.count * sizeof(struct pnx4008_dma_ll),
- &ll_pool.dma_addr, GFP_KERNEL);
-
- if (!ll_pool.vaddr) {
- ret = -ENOMEM;
- free_irq(DMA_INT, NULL);
- goto out;
- }
-
- for (i = 0; i < ll_pool.count - 1; i++) {
- void **addr = ll_pool.vaddr + i * sizeof(struct pnx4008_dma_ll);
- *addr = (void *)addr + sizeof(struct pnx4008_dma_ll);
- }
- *(long *)(ll_pool.vaddr +
- (ll_pool.count - 1) * sizeof(struct pnx4008_dma_ll)) =
- (long)ll_pool.vaddr;
-
- __raw_writel(1, DMAC_CONFIG);
-
-out:
- return ret;
-}
-arch_initcall(pnx4008_dma_init);
diff --git a/arch/arm/mach-pnx4008/gpio.c b/arch/arm/mach-pnx4008/gpio.c
deleted file mode 100644
index d3e71d3..0000000
--- a/arch/arm/mach-pnx4008/gpio.c
+++ /dev/null
@@ -1,328 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/gpio.c
- *
- * PNX4008 GPIO driver
- *
- * Author: Dmitry Chigirev <source@mvista.com>
- *
- * Based on reference code by Iwo Mergler and Z.Tabaaloute from Philips:
- * Copyright (c) 2005 Koninklijke Philips Electronics N.V.
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/platform.h>
-#include <mach/gpio-pnx4008.h>
-
-/* register definitions */
-#define PIO_VA_BASE IO_ADDRESS(PNX4008_PIO_BASE)
-
-#define PIO_INP_STATE (0x00U)
-#define PIO_OUTP_SET (0x04U)
-#define PIO_OUTP_CLR (0x08U)
-#define PIO_OUTP_STATE (0x0CU)
-#define PIO_DRV_SET (0x10U)
-#define PIO_DRV_CLR (0x14U)
-#define PIO_DRV_STATE (0x18U)
-#define PIO_SDINP_STATE (0x1CU)
-#define PIO_SDOUTP_SET (0x20U)
-#define PIO_SDOUTP_CLR (0x24U)
-#define PIO_MUX_SET (0x28U)
-#define PIO_MUX_CLR (0x2CU)
-#define PIO_MUX_STATE (0x30U)
-
-static inline void gpio_lock(void)
-{
- local_irq_disable();
-}
-
-static inline void gpio_unlock(void)
-{
- local_irq_enable();
-}
-
-/* Inline functions */
-static inline int gpio_read_bit(u32 reg, int gpio)
-{
- u32 bit, val;
- int ret = -EFAULT;
-
- if (gpio < 0)
- goto out;
-
- bit = GPIO_BIT(gpio);
- if (bit) {
- val = __raw_readl(PIO_VA_BASE + reg);
- ret = (val & bit) ? 1 : 0;
- }
-out:
- return ret;
-}
-
-static inline int gpio_set_bit(u32 reg, int gpio)
-{
- u32 bit, val;
- int ret = -EFAULT;
-
- if (gpio < 0)
- goto out;
-
- bit = GPIO_BIT(gpio);
- if (bit) {
- val = __raw_readl(PIO_VA_BASE + reg);
- val |= bit;
- __raw_writel(val, PIO_VA_BASE + reg);
- ret = 0;
- }
-out:
- return ret;
-}
-
-/* Very simple access control, bitmap for allocated/free */
-static unsigned long access_map[4];
-#define INP_INDEX 0
-#define OUTP_INDEX 1
-#define GPIO_INDEX 2
-#define MUX_INDEX 3
-
-/*GPIO to Input Mapping */
-static short gpio_to_inp_map[32] = {
- -1, -1, -1, -1, -1, -1, -1, -1,
- -1, -1, -1, -1, -1, -1, -1, -1,
- -1, -1, -1, -1, -1, -1, -1, -1,
- -1, 10, 11, 12, 13, 14, 24, -1
-};
-
-/*GPIO to Mux Mapping */
-static short gpio_to_mux_map[32] = {
- -1, -1, -1, -1, -1, -1, -1, -1,
- -1, -1, -1, -1, -1, -1, -1, -1,
- -1, -1, -1, -1, -1, -1, -1, -1,
- -1, -1, -1, 0, 1, 4, 5, -1
-};
-
-/*Output to Mux Mapping */
-static short outp_to_mux_map[32] = {
- -1, -1, -1, 6, -1, -1, -1, -1,
- -1, -1, -1, -1, -1, -1, -1, -1,
- -1, -1, -1, -1, -1, 2, -1, -1,
- -1, -1, -1, -1, -1, -1, -1, -1
-};
-
-int pnx4008_gpio_register_pin(unsigned short pin)
-{
- unsigned long bit = GPIO_BIT(pin);
- int ret = -EBUSY; /* Already in use */
-
- gpio_lock();
-
- if (GPIO_ISBID(pin)) {
- if (access_map[GPIO_INDEX] & bit)
- goto out;
- access_map[GPIO_INDEX] |= bit;
-
- } else if (GPIO_ISRAM(pin)) {
- if (access_map[GPIO_INDEX] & bit)
- goto out;
- access_map[GPIO_INDEX] |= bit;
-
- } else if (GPIO_ISMUX(pin)) {
- if (access_map[MUX_INDEX] & bit)
- goto out;
- access_map[MUX_INDEX] |= bit;
-
- } else if (GPIO_ISOUT(pin)) {
- if (access_map[OUTP_INDEX] & bit)
- goto out;
- access_map[OUTP_INDEX] |= bit;
-
- } else if (GPIO_ISIN(pin)) {
- if (access_map[INP_INDEX] & bit)
- goto out;
- access_map[INP_INDEX] |= bit;
- } else
- goto out;
- ret = 0;
-
-out:
- gpio_unlock();
- return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_register_pin);
-
-int pnx4008_gpio_unregister_pin(unsigned short pin)
-{
- unsigned long bit = GPIO_BIT(pin);
- int ret = -EFAULT; /* Not registered */
-
- gpio_lock();
-
- if (GPIO_ISBID(pin)) {
- if (~access_map[GPIO_INDEX] & bit)
- goto out;
- access_map[GPIO_INDEX] &= ~bit;
- } else if (GPIO_ISRAM(pin)) {
- if (~access_map[GPIO_INDEX] & bit)
- goto out;
- access_map[GPIO_INDEX] &= ~bit;
- } else if (GPIO_ISMUX(pin)) {
- if (~access_map[MUX_INDEX] & bit)
- goto out;
- access_map[MUX_INDEX] &= ~bit;
- } else if (GPIO_ISOUT(pin)) {
- if (~access_map[OUTP_INDEX] & bit)
- goto out;
- access_map[OUTP_INDEX] &= ~bit;
- } else if (GPIO_ISIN(pin)) {
- if (~access_map[INP_INDEX] & bit)
- goto out;
- access_map[INP_INDEX] &= ~bit;
- } else
- goto out;
- ret = 0;
-
-out:
- gpio_unlock();
- return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_unregister_pin);
-
-unsigned long pnx4008_gpio_read_pin(unsigned short pin)
-{
- unsigned long ret = -EFAULT;
- int gpio = GPIO_BIT_MASK(pin);
- gpio_lock();
- if (GPIO_ISOUT(pin)) {
- ret = gpio_read_bit(PIO_OUTP_STATE, gpio);
- } else if (GPIO_ISRAM(pin)) {
- if (gpio_read_bit(PIO_DRV_STATE, gpio) == 0) {
- ret = gpio_read_bit(PIO_SDINP_STATE, gpio);
- }
- } else if (GPIO_ISBID(pin)) {
- ret = gpio_read_bit(PIO_DRV_STATE, gpio);
- if (ret > 0)
- ret = gpio_read_bit(PIO_OUTP_STATE, gpio);
- else if (ret == 0)
- ret =
- gpio_read_bit(PIO_INP_STATE, gpio_to_inp_map[gpio]);
- } else if (GPIO_ISIN(pin)) {
- ret = gpio_read_bit(PIO_INP_STATE, gpio);
- }
- gpio_unlock();
- return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_read_pin);
-
-/* Write Value to output */
-int pnx4008_gpio_write_pin(unsigned short pin, int output)
-{
- int gpio = GPIO_BIT_MASK(pin);
- int ret = -EFAULT;
-
- gpio_lock();
- if (GPIO_ISOUT(pin)) {
- printk( "writing '%x' to '%x'\n",
- gpio, output ? PIO_OUTP_SET : PIO_OUTP_CLR );
- ret = gpio_set_bit(output ? PIO_OUTP_SET : PIO_OUTP_CLR, gpio);
- } else if (GPIO_ISRAM(pin)) {
- if (gpio_read_bit(PIO_DRV_STATE, gpio) > 0)
- ret = gpio_set_bit(output ? PIO_SDOUTP_SET :
- PIO_SDOUTP_CLR, gpio);
- } else if (GPIO_ISBID(pin)) {
- if (gpio_read_bit(PIO_DRV_STATE, gpio) > 0)
- ret = gpio_set_bit(output ? PIO_OUTP_SET :
- PIO_OUTP_CLR, gpio);
- }
- gpio_unlock();
- return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_write_pin);
-
-/* Value = 1 : Set GPIO pin as output */
-/* Value = 0 : Set GPIO pin as input */
-int pnx4008_gpio_set_pin_direction(unsigned short pin, int output)
-{
- int gpio = GPIO_BIT_MASK(pin);
- int ret = -EFAULT;
-
- gpio_lock();
- if (GPIO_ISBID(pin) || GPIO_ISRAM(pin)) {
- ret = gpio_set_bit(output ? PIO_DRV_SET : PIO_DRV_CLR, gpio);
- }
- gpio_unlock();
- return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_set_pin_direction);
-
-/* Read GPIO pin direction: 0= pin used as input, 1= pin used as output*/
-int pnx4008_gpio_read_pin_direction(unsigned short pin)
-{
- int gpio = GPIO_BIT_MASK(pin);
- int ret = -EFAULT;
-
- gpio_lock();
- if (GPIO_ISBID(pin) || GPIO_ISRAM(pin)) {
- ret = gpio_read_bit(PIO_DRV_STATE, gpio);
- }
- gpio_unlock();
- return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_read_pin_direction);
-
-/* Value = 1 : Set pin to muxed function */
-/* Value = 0 : Set pin as GPIO */
-int pnx4008_gpio_set_pin_mux(unsigned short pin, int output)
-{
- int gpio = GPIO_BIT_MASK(pin);
- int ret = -EFAULT;
-
- gpio_lock();
- if (GPIO_ISBID(pin)) {
- ret =
- gpio_set_bit(output ? PIO_MUX_SET : PIO_MUX_CLR,
- gpio_to_mux_map[gpio]);
- } else if (GPIO_ISOUT(pin)) {
- ret =
- gpio_set_bit(output ? PIO_MUX_SET : PIO_MUX_CLR,
- outp_to_mux_map[gpio]);
- } else if (GPIO_ISMUX(pin)) {
- ret = gpio_set_bit(output ? PIO_MUX_SET : PIO_MUX_CLR, gpio);
- }
- gpio_unlock();
- return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_set_pin_mux);
-
-/* Read pin mux function: 0= pin used as GPIO, 1= pin used for muxed function*/
-int pnx4008_gpio_read_pin_mux(unsigned short pin)
-{
- int gpio = GPIO_BIT_MASK(pin);
- int ret = -EFAULT;
-
- gpio_lock();
- if (GPIO_ISBID(pin)) {
- ret = gpio_read_bit(PIO_MUX_STATE, gpio_to_mux_map[gpio]);
- } else if (GPIO_ISOUT(pin)) {
- ret = gpio_read_bit(PIO_MUX_STATE, outp_to_mux_map[gpio]);
- } else if (GPIO_ISMUX(pin)) {
- ret = gpio_read_bit(PIO_MUX_STATE, gpio);
- }
- gpio_unlock();
- return ret;
-}
-
-EXPORT_SYMBOL(pnx4008_gpio_read_pin_mux);
diff --git a/arch/arm/mach-pnx4008/i2c.c b/arch/arm/mach-pnx4008/i2c.c
deleted file mode 100644
index 550cfc2..0000000
--- a/arch/arm/mach-pnx4008/i2c.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * I2C initialization for PNX4008.
- *
- * Author: Vitaly Wool <vitalywool@gmail.com>
- *
- * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/clk.h>
-#include <linux/i2c.h>
-#include <linux/i2c-pnx.h>
-#include <linux/platform_device.h>
-#include <linux/err.h>
-#include <mach/platform.h>
-#include <mach/irqs.h>
-
-static struct resource i2c0_resources[] = {
- {
- .start = PNX4008_I2C1_BASE,
- .end = PNX4008_I2C1_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = I2C_1_INT,
- .end = I2C_1_INT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct resource i2c1_resources[] = {
- {
- .start = PNX4008_I2C2_BASE,
- .end = PNX4008_I2C2_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = I2C_2_INT,
- .end = I2C_2_INT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct resource i2c2_resources[] = {
- {
- .start = PNX4008_USB_CONFIG_BASE + 0x300,
- .end = PNX4008_USB_CONFIG_BASE + 0x300 + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = USB_I2C_INT,
- .end = USB_I2C_INT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device i2c0_device = {
- .name = "pnx-i2c.0",
- .id = 0,
- .resource = i2c0_resources,
- .num_resources = ARRAY_SIZE(i2c0_resources),
-};
-
-static struct platform_device i2c1_device = {
- .name = "pnx-i2c.1",
- .id = 1,
- .resource = i2c1_resources,
- .num_resources = ARRAY_SIZE(i2c1_resources),
-};
-
-static struct platform_device i2c2_device = {
- .name = "pnx-i2c.2",
- .id = 2,
- .resource = i2c2_resources,
- .num_resources = ARRAY_SIZE(i2c2_resources),
-};
-
-static struct platform_device *devices[] __initdata = {
- &i2c0_device,
- &i2c1_device,
- &i2c2_device,
-};
-
-void __init pnx4008_register_i2c_devices(void)
-{
- platform_add_devices(devices, ARRAY_SIZE(devices));
-}
diff --git a/arch/arm/mach-pnx4008/include/mach/clock.h b/arch/arm/mach-pnx4008/include/mach/clock.h
deleted file mode 100644
index 8d2a5ef..0000000
--- a/arch/arm/mach-pnx4008/include/mach/clock.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/clock.h
- *
- * Clock control driver for PNX4008 - header file
- *
- * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __PNX4008_CLOCK_H__
-#define __PNX4008_CLOCK_H__
-
-struct module;
-struct clk;
-
-#define PWRMAN_VA_BASE IO_ADDRESS(PNX4008_PWRMAN_BASE)
-#define HCLKDIVCTRL_REG (PWRMAN_VA_BASE + 0x40)
-#define PWRCTRL_REG (PWRMAN_VA_BASE + 0x44)
-#define PLLCTRL_REG (PWRMAN_VA_BASE + 0x48)
-#define OSC13CTRL_REG (PWRMAN_VA_BASE + 0x4c)
-#define SYSCLKCTRL_REG (PWRMAN_VA_BASE + 0x50)
-#define HCLKPLLCTRL_REG (PWRMAN_VA_BASE + 0x58)
-#define USBCTRL_REG (PWRMAN_VA_BASE + 0x64)
-#define SDRAMCLKCTRL_REG (PWRMAN_VA_BASE + 0x68)
-#define MSCTRL_REG (PWRMAN_VA_BASE + 0x80)
-#define BTCLKCTRL (PWRMAN_VA_BASE + 0x84)
-#define DUMCLKCTRL_REG (PWRMAN_VA_BASE + 0x90)
-#define I2CCLKCTRL_REG (PWRMAN_VA_BASE + 0xac)
-#define KEYCLKCTRL_REG (PWRMAN_VA_BASE + 0xb0)
-#define TSCLKCTRL_REG (PWRMAN_VA_BASE + 0xb4)
-#define PWMCLKCTRL_REG (PWRMAN_VA_BASE + 0xb8)
-#define TIMCLKCTRL_REG (PWRMAN_VA_BASE + 0xbc)
-#define SPICTRL_REG (PWRMAN_VA_BASE + 0xc4)
-#define FLASHCLKCTRL_REG (PWRMAN_VA_BASE + 0xc8)
-#define UART3CLK_REG (PWRMAN_VA_BASE + 0xd0)
-#define UARTCLKCTRL_REG (PWRMAN_VA_BASE + 0xe4)
-#define DMACLKCTRL_REG (PWRMAN_VA_BASE + 0xe8)
-#define AUTOCLK_CTRL (PWRMAN_VA_BASE + 0xec)
-#define JPEGCLKCTRL_REG (PWRMAN_VA_BASE + 0xfc)
-
-#define AUDIOCONFIG_VA_BASE IO_ADDRESS(PNX4008_AUDIOCONFIG_BASE)
-#define DSPPLLCTRL_REG (AUDIOCONFIG_VA_BASE + 0x60)
-#define DSPCLKCTRL_REG (AUDIOCONFIG_VA_BASE + 0x64)
-#define AUDIOCLKCTRL_REG (AUDIOCONFIG_VA_BASE + 0x68)
-#define AUDIOPLLCTRL_REG (AUDIOCONFIG_VA_BASE + 0x6C)
-
-#define USB_OTG_CLKCTRL_REG IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xff4)
-
-#define VFP9CLKCTRL_REG IO_ADDRESS(PNX4008_DEBUG_BASE)
-
-#define CLK_RATE_13MHZ 13000
-#define CLK_RATE_1MHZ 1000
-#define CLK_RATE_208MHZ 208000
-#define CLK_RATE_48MHZ 48000
-#define CLK_RATE_32KHZ 32
-
-#define PNX4008_UART_CLK CLK_RATE_13MHZ * 1000 /* in MHz */
-
-#endif
diff --git a/arch/arm/mach-pnx4008/include/mach/debug-macro.S b/arch/arm/mach-pnx4008/include/mach/debug-macro.S
deleted file mode 100644
index 469d60d..0000000
--- a/arch/arm/mach-pnx4008/include/mach/debug-macro.S
+++ /dev/null
@@ -1,21 +0,0 @@
-/* arch/arm/mach-pnx4008/include/mach/debug-macro.S
- *
- * Debugging macro include header
- *
- * Copyright (C) 1994-1999 Russell King
- * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
- .macro addruart, rp, rv, tmp
- mov \rp, #0x00090000
- add \rv, \rp, #0xf4000000 @ virtual
- add \rp, \rp, #0x40000000 @ physical
- .endm
-
-#define UART_SHIFT 2
-#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-pnx4008/include/mach/dma.h b/arch/arm/mach-pnx4008/include/mach/dma.h
deleted file mode 100644
index f094bf8..0000000
--- a/arch/arm/mach-pnx4008/include/mach/dma.h
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/dma.h
- *
- * PNX4008 DMA header file
- *
- * Author: Vitaly Wool
- * Copyright: MontaVista Software Inc. (c) 2005
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-
-#include "platform.h"
-
-#define MAX_DMA_CHANNELS 8
-
-#define DMAC_BASE IO_ADDRESS(PNX4008_DMA_CONFIG_BASE)
-#define DMAC_INT_STAT (DMAC_BASE + 0x0000)
-#define DMAC_INT_TC_STAT (DMAC_BASE + 0x0004)
-#define DMAC_INT_TC_CLEAR (DMAC_BASE + 0x0008)
-#define DMAC_INT_ERR_STAT (DMAC_BASE + 0x000c)
-#define DMAC_INT_ERR_CLEAR (DMAC_BASE + 0x0010)
-#define DMAC_SOFT_SREQ (DMAC_BASE + 0x0024)
-#define DMAC_CONFIG (DMAC_BASE + 0x0030)
-#define DMAC_Cx_SRC_ADDR(c) (DMAC_BASE + 0x0100 + (c) * 0x20)
-#define DMAC_Cx_DEST_ADDR(c) (DMAC_BASE + 0x0104 + (c) * 0x20)
-#define DMAC_Cx_LLI(c) (DMAC_BASE + 0x0108 + (c) * 0x20)
-#define DMAC_Cx_CONTROL(c) (DMAC_BASE + 0x010c + (c) * 0x20)
-#define DMAC_Cx_CONFIG(c) (DMAC_BASE + 0x0110 + (c) * 0x20)
-
-enum {
- WIDTH_BYTE = 0,
- WIDTH_HWORD,
- WIDTH_WORD
-};
-
-enum {
- FC_MEM2MEM_DMA,
- FC_MEM2PER_DMA,
- FC_PER2MEM_DMA,
- FC_PER2PER_DMA,
- FC_PER2PER_DPER,
- FC_MEM2PER_PER,
- FC_PER2MEM_PER,
- FC_PER2PER_SPER
-};
-
-enum {
- DMA_INT_UNKNOWN = 0,
- DMA_ERR_INT = 1,
- DMA_TC_INT = 2,
-};
-
-enum {
- DMA_BUFFER_ALLOCATED = 1,
- DMA_HAS_LL = 2,
-};
-
-enum {
- PER_CAM_DMA_1 = 0,
- PER_NDF_FLASH = 1,
- PER_MBX_SLAVE_FIFO = 2,
- PER_SPI2_REC_XMIT = 3,
- PER_MS_SD_RX_XMIT = 4,
- PER_HS_UART_1_XMIT = 5,
- PER_HS_UART_1_RX = 6,
- PER_HS_UART_2_XMIT = 7,
- PER_HS_UART_2_RX = 8,
- PER_HS_UART_7_XMIT = 9,
- PER_HS_UART_7_RX = 10,
- PER_SPI1_REC_XMIT = 11,
- PER_MLC_NDF_SREC = 12,
- PER_CAM_DMA_2 = 13,
- PER_PRNG_INFIFO = 14,
- PER_PRNG_OUTFIFO = 15,
-};
-
-struct pnx4008_dma_ch_ctrl {
- int tc_mask;
- int cacheable;
- int bufferable;
- int priv_mode;
- int di;
- int si;
- int dest_ahb1;
- int src_ahb1;
- int dwidth;
- int swidth;
- int dbsize;
- int sbsize;
- int tr_size;
-};
-
-struct pnx4008_dma_ch_config {
- int halt;
- int active;
- int lock;
- int itc;
- int ie;
- int flow_cntrl;
- int dest_per;
- int src_per;
-};
-
-struct pnx4008_dma_ll {
- unsigned long src_addr;
- unsigned long dest_addr;
- u32 next_dma;
- unsigned long ch_ctrl;
- struct pnx4008_dma_ll *next;
- int flags;
- void *alloc_data;
- int (*free) (void *);
-};
-
-struct pnx4008_dma_config {
- int is_ll;
- unsigned long src_addr;
- unsigned long dest_addr;
- unsigned long ch_ctrl;
- unsigned long ch_cfg;
- struct pnx4008_dma_ll *ll;
- u32 ll_dma;
- int flags;
- void *alloc_data;
- int (*free) (void *);
-};
-
-extern struct pnx4008_dma_ll *pnx4008_alloc_ll_entry(dma_addr_t *);
-extern void pnx4008_free_ll_entry(struct pnx4008_dma_ll *, dma_addr_t);
-extern void pnx4008_free_ll(u32 ll_dma, struct pnx4008_dma_ll *);
-
-extern int pnx4008_request_channel(char *, int,
- void (*)(int, int, void *),
- void *);
-extern void pnx4008_free_channel(int);
-extern int pnx4008_config_dma(int, int, int);
-extern int pnx4008_dma_pack_control(const struct pnx4008_dma_ch_ctrl *,
- unsigned long *);
-extern int pnx4008_dma_parse_control(unsigned long,
- struct pnx4008_dma_ch_ctrl *);
-extern int pnx4008_dma_pack_config(const struct pnx4008_dma_ch_config *,
- unsigned long *);
-extern int pnx4008_dma_parse_config(unsigned long,
- struct pnx4008_dma_ch_config *);
-extern int pnx4008_config_channel(int, struct pnx4008_dma_config *);
-extern int pnx4008_channel_get_config(int, struct pnx4008_dma_config *);
-extern int pnx4008_dma_ch_enable(int);
-extern int pnx4008_dma_ch_disable(int);
-extern int pnx4008_dma_ch_enabled(int);
-extern void pnx4008_dma_split_head_entry(struct pnx4008_dma_config *,
- struct pnx4008_dma_ch_ctrl *);
-extern void pnx4008_dma_split_ll_entry(struct pnx4008_dma_ll *,
- struct pnx4008_dma_ch_ctrl *);
-
-#endif /* _ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-pnx4008/include/mach/entry-macro.S b/arch/arm/mach-pnx4008/include/mach/entry-macro.S
deleted file mode 100644
index 77a5558..0000000
--- a/arch/arm/mach-pnx4008/include/mach/entry-macro.S
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for PNX4008-based platforms
- *
- * 2005-2006 (c) MontaVista Software, Inc.
- * Author: Vitaly Wool <vwool@ru.mvista.com>
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include "platform.h"
-
-#define IO_BASE 0xF0000000
-#define IO_ADDRESS(x) (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE)
-
-#define INTRC_MASK 0x00
-#define INTRC_RAW_STAT 0x04
-#define INTRC_STAT 0x08
-#define INTRC_POLAR 0x0C
-#define INTRC_ACT_TYPE 0x10
-#define INTRC_TYPE 0x14
-
-#define SIC1_BASE_INT 32
-#define SIC2_BASE_INT 64
-
- .macro get_irqnr_preamble, base, tmp
- .endm
-
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
-/* decode the MIC interrupt numbers */
- ldr \base, =IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
- ldr \irqstat, [\base, #INTRC_STAT]
-
- cmp \irqstat,#1<<16
- movhs \irqnr,#16
- movlo \irqnr,#0
- movhs \irqstat,\irqstat,lsr#16
- cmp \irqstat,#1<<8
- addhs \irqnr,\irqnr,#8
- movhs \irqstat,\irqstat,lsr#8
- cmp \irqstat,#1<<4
- addhs \irqnr,\irqnr,#4
- movhs \irqstat,\irqstat,lsr#4
- cmp \irqstat,#1<<2
- addhs \irqnr,\irqnr,#2
- movhs \irqstat,\irqstat,lsr#2
- cmp \irqstat,#1<<1
- addhs \irqnr,\irqnr,#1
-
-/* was there an interrupt ? if not then drop out with EQ status */
- teq \irqstat,#0
- beq 1003f
-
-/* and now check for extended IRQ reasons */
- cmp \irqnr,#1
- bls 1003f
- cmp \irqnr,#30
- blo 1002f
-
-/* IRQ 31,30 : High priority cascade IRQ handle */
-/* read the correct SIC */
-/* decoding status after compare : eq is 30 (SIC1) , ne is 31 (SIC2) */
-/* set the base IRQ number */
- ldreq \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
- moveq \irqnr,#SIC1_BASE_INT
- ldrne \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
- movne \irqnr,#SIC2_BASE_INT
- ldr \irqstat, [\base, #INTRC_STAT]
- ldr \tmp, [\base, #INTRC_TYPE]
-/* and with inverted mask : low priority interrupts */
- and \irqstat,\irqstat,\tmp
- b 1004f
-
-1003:
-/* IRQ 1,0 : Low priority cascade IRQ handle */
-/* read the correct SIC */
-/* decoding status after compare : eq is 1 (SIC2) , ne is 0 (SIC1)*/
-/* read the correct SIC */
-/* set the base IRQ number */
- ldrne \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
- movne \irqnr,#SIC1_BASE_INT
- ldreq \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
- moveq \irqnr,#SIC2_BASE_INT
- ldr \irqstat, [\base, #INTRC_STAT]
- ldr \tmp, [\base, #INTRC_TYPE]
-/* and with inverted mask : low priority interrupts */
- bic \irqstat,\irqstat,\tmp
-
-1004:
-
- cmp \irqstat,#1<<16
- addhs \irqnr,\irqnr,#16
- movhs \irqstat,\irqstat,lsr#16
- cmp \irqstat,#1<<8
- addhs \irqnr,\irqnr,#8
- movhs \irqstat,\irqstat,lsr#8
- cmp \irqstat,#1<<4
- addhs \irqnr,\irqnr,#4
- movhs \irqstat,\irqstat,lsr#4
- cmp \irqstat,#1<<2
- addhs \irqnr,\irqnr,#2
- movhs \irqstat,\irqstat,lsr#2
- cmp \irqstat,#1<<1
- addhs \irqnr,\irqnr,#1
-
-
-/* is irqstat not zero */
-
-1002:
-/* we assert that irqstat is not equal to zero and return ne status if true*/
- teq \irqstat,#0
-1003:
- .endm
-
diff --git a/arch/arm/mach-pnx4008/include/mach/gpio-pnx4008.h b/arch/arm/mach-pnx4008/include/mach/gpio-pnx4008.h
deleted file mode 100644
index 41027dd..0000000
--- a/arch/arm/mach-pnx4008/include/mach/gpio-pnx4008.h
+++ /dev/null
@@ -1,241 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/gpio-pnx4008.h
- *
- * PNX4008 GPIO driver - header file
- *
- * Author: Dmitry Chigirev <source@mvista.com>
- *
- * Based on reference code by Iwo Mergler and Z.Tabaaloute from Philips:
- * Copyright (c) 2005 Koninklijke Philips Electronics N.V.
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef _PNX4008_GPIO_H_
-#define _PNX4008_GPIO_H_
-
-
-/* Block numbers */
-#define GPIO_IN (0)
-#define GPIO_OUT (0x100)
-#define GPIO_BID (0x200)
-#define GPIO_RAM (0x300)
-#define GPIO_MUX (0x400)
-
-#define GPIO_TYPE_MASK(K) ((K) & 0x700)
-
-/* INPUT GPIOs */
-/* GPI */
-#define GPI_00 (GPIO_IN | 0)
-#define GPI_01 (GPIO_IN | 1)
-#define GPI_02 (GPIO_IN | 2)
-#define GPI_03 (GPIO_IN | 3)
-#define GPI_04 (GPIO_IN | 4)
-#define GPI_05 (GPIO_IN | 5)
-#define GPI_06 (GPIO_IN | 6)
-#define GPI_07 (GPIO_IN | 7)
-#define GPI_08 (GPIO_IN | 8)
-#define GPI_09 (GPIO_IN | 9)
-#define U1_RX (GPIO_IN | 15)
-#define U2_HTCS (GPIO_IN | 16)
-#define U2_RX (GPIO_IN | 17)
-#define U3_RX (GPIO_IN | 18)
-#define U4_RX (GPIO_IN | 19)
-#define U5_RX (GPIO_IN | 20)
-#define U6_IRRX (GPIO_IN | 21)
-#define U7_HCTS (GPIO_IN | 22)
-#define U7_RX (GPIO_IN | 23)
-/* MISC IN */
-#define SPI1_DATIN (GPIO_IN | 25)
-#define DISP_SYNC (GPIO_IN | 26)
-#define SPI2_DATIN (GPIO_IN | 27)
-#define GPI_11 (GPIO_IN | 28)
-
-#define GPIO_IN_MASK 0x1eff83ff
-
-/* OUTPUT GPIOs */
-/* GPO */
-#define GPO_00 (GPIO_OUT | 0)
-#define GPO_01 (GPIO_OUT | 1)
-#define GPO_02 (GPIO_OUT | 2)
-#define GPO_03 (GPIO_OUT | 3)
-#define GPO_04 (GPIO_OUT | 4)
-#define GPO_05 (GPIO_OUT | 5)
-#define GPO_06 (GPIO_OUT | 6)
-#define GPO_07 (GPIO_OUT | 7)
-#define GPO_08 (GPIO_OUT | 8)
-#define GPO_09 (GPIO_OUT | 9)
-#define GPO_10 (GPIO_OUT | 10)
-#define GPO_11 (GPIO_OUT | 11)
-#define GPO_12 (GPIO_OUT | 12)
-#define GPO_13 (GPIO_OUT | 13)
-#define GPO_14 (GPIO_OUT | 14)
-#define GPO_15 (GPIO_OUT | 15)
-#define GPO_16 (GPIO_OUT | 16)
-#define GPO_17 (GPIO_OUT | 17)
-#define GPO_18 (GPIO_OUT | 18)
-#define GPO_19 (GPIO_OUT | 19)
-#define GPO_20 (GPIO_OUT | 20)
-#define GPO_21 (GPIO_OUT | 21)
-#define GPO_22 (GPIO_OUT | 22)
-#define GPO_23 (GPIO_OUT | 23)
-
-#define GPIO_OUT_MASK 0xffffff
-
-/* BIDIRECTIONAL GPIOs */
-/* RAM pins */
-#define RAM_D19 (GPIO_RAM | 0)
-#define RAM_D20 (GPIO_RAM | 1)
-#define RAM_D21 (GPIO_RAM | 2)
-#define RAM_D22 (GPIO_RAM | 3)
-#define RAM_D23 (GPIO_RAM | 4)
-#define RAM_D24 (GPIO_RAM | 5)
-#define RAM_D25 (GPIO_RAM | 6)
-#define RAM_D26 (GPIO_RAM | 7)
-#define RAM_D27 (GPIO_RAM | 8)
-#define RAM_D28 (GPIO_RAM | 9)
-#define RAM_D29 (GPIO_RAM | 10)
-#define RAM_D30 (GPIO_RAM | 11)
-#define RAM_D31 (GPIO_RAM | 12)
-
-#define GPIO_RAM_MASK 0x1fff
-
-/* I/O pins */
-#define GPIO_00 (GPIO_BID | 25)
-#define GPIO_01 (GPIO_BID | 26)
-#define GPIO_02 (GPIO_BID | 27)
-#define GPIO_03 (GPIO_BID | 28)
-#define GPIO_04 (GPIO_BID | 29)
-#define GPIO_05 (GPIO_BID | 30)
-
-#define GPIO_BID_MASK 0x7e000000
-
-/* Non-GPIO multiplexed PIOs. For multiplexing with GPIO, please use GPIO macros */
-#define GPIO_SDRAM_SEL (GPIO_MUX | 3)
-
-#define GPIO_MUX_MASK 0x8
-
-/* Extraction/assembly macros */
-#define GPIO_BIT_MASK(K) ((K) & 0x1F)
-#define GPIO_BIT(K) (1 << GPIO_BIT_MASK(K))
-#define GPIO_ISMUX(K) ((GPIO_TYPE_MASK(K) == GPIO_MUX) && (GPIO_BIT(K) & GPIO_MUX_MASK))
-#define GPIO_ISRAM(K) ((GPIO_TYPE_MASK(K) == GPIO_RAM) && (GPIO_BIT(K) & GPIO_RAM_MASK))
-#define GPIO_ISBID(K) ((GPIO_TYPE_MASK(K) == GPIO_BID) && (GPIO_BIT(K) & GPIO_BID_MASK))
-#define GPIO_ISOUT(K) ((GPIO_TYPE_MASK(K) == GPIO_OUT) && (GPIO_BIT(K) & GPIO_OUT_MASK))
-#define GPIO_ISIN(K) ((GPIO_TYPE_MASK(K) == GPIO_IN) && (GPIO_BIT(K) & GPIO_IN_MASK))
-
-/* Start Enable Pin Interrupts - table 58 page 66 */
-
-#define SE_PIN_BASE_INT 32
-
-#define SE_U7_RX_INT 63
-#define SE_U7_HCTS_INT 62
-#define SE_BT_CLKREQ_INT 61
-#define SE_U6_IRRX_INT 60
-/*59 unused*/
-#define SE_U5_RX_INT 58
-#define SE_GPI_11_INT 57
-#define SE_U3_RX_INT 56
-#define SE_U2_HCTS_INT 55
-#define SE_U2_RX_INT 54
-#define SE_U1_RX_INT 53
-#define SE_DISP_SYNC_INT 52
-/*51 unused*/
-#define SE_SDIO_INT_N 50
-#define SE_MSDIO_START_INT 49
-#define SE_GPI_06_INT 48
-#define SE_GPI_05_INT 47
-#define SE_GPI_04_INT 46
-#define SE_GPI_03_INT 45
-#define SE_GPI_02_INT 44
-#define SE_GPI_01_INT 43
-#define SE_GPI_00_INT 42
-#define SE_SYSCLKEN_PIN_INT 41
-#define SE_SPI1_DATAIN_INT 40
-#define SE_GPI_07_INT 39
-#define SE_SPI2_DATAIN_INT 38
-#define SE_GPI_10_INT 37
-#define SE_GPI_09_INT 36
-#define SE_GPI_08_INT 35
-/*34-32 unused*/
-
-/* Start Enable Internal Interrupts - table 57 page 65 */
-
-#define SE_INT_BASE_INT 0
-
-#define SE_TS_IRQ 31
-#define SE_TS_P_INT 30
-#define SE_TS_AUX_INT 29
-/*27-28 unused*/
-#define SE_USB_AHB_NEED_CLK_INT 26
-#define SE_MSTIMER_INT 25
-#define SE_RTC_INT 24
-#define SE_USB_NEED_CLK_INT 23
-#define SE_USB_INT 22
-#define SE_USB_I2C_INT 21
-#define SE_USB_OTG_TIMER_INT 20
-#define SE_USB_OTG_ATX_INT_N 19
-/*18 unused*/
-#define SE_DSP_GPIO4_INT 17
-#define SE_KEY_IRQ 16
-#define SE_DSP_SLAVEPORT_INT 15
-#define SE_DSP_GPIO1_INT 14
-#define SE_DSP_GPIO0_INT 13
-#define SE_DSP_AHB_INT 12
-/*11-6 unused*/
-#define SE_GPIO_05_INT 5
-#define SE_GPIO_04_INT 4
-#define SE_GPIO_03_INT 3
-#define SE_GPIO_02_INT 2
-#define SE_GPIO_01_INT 1
-#define SE_GPIO_00_INT 0
-
-#define START_INT_REG_BIT(irq) (1<<((irq)&0x1F))
-
-#define START_INT_ER_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x20 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_RSR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x24 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_SR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x28 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_APR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x2C + (((irq)&(0x1<<5))>>1)))
-
-extern int pnx4008_gpio_register_pin(unsigned short pin);
-extern int pnx4008_gpio_unregister_pin(unsigned short pin);
-extern unsigned long pnx4008_gpio_read_pin(unsigned short pin);
-extern int pnx4008_gpio_write_pin(unsigned short pin, int output);
-extern int pnx4008_gpio_set_pin_direction(unsigned short pin, int output);
-extern int pnx4008_gpio_read_pin_direction(unsigned short pin);
-extern int pnx4008_gpio_set_pin_mux(unsigned short pin, int output);
-extern int pnx4008_gpio_read_pin_mux(unsigned short pin);
-
-static inline void start_int_umask(u8 irq)
-{
- __raw_writel(__raw_readl(START_INT_ER_REG(irq)) |
- START_INT_REG_BIT(irq), START_INT_ER_REG(irq));
-}
-
-static inline void start_int_mask(u8 irq)
-{
- __raw_writel(__raw_readl(START_INT_ER_REG(irq)) &
- ~START_INT_REG_BIT(irq), START_INT_ER_REG(irq));
-}
-
-static inline void start_int_ack(u8 irq)
-{
- __raw_writel(START_INT_REG_BIT(irq), START_INT_RSR_REG(irq));
-}
-
-static inline void start_int_set_falling_edge(u8 irq)
-{
- __raw_writel(__raw_readl(START_INT_APR_REG(irq)) &
- ~START_INT_REG_BIT(irq), START_INT_APR_REG(irq));
-}
-
-static inline void start_int_set_rising_edge(u8 irq)
-{
- __raw_writel(__raw_readl(START_INT_APR_REG(irq)) |
- START_INT_REG_BIT(irq), START_INT_APR_REG(irq));
-}
-
-#endif /* _PNX4008_GPIO_H_ */
diff --git a/arch/arm/mach-pnx4008/include/mach/hardware.h b/arch/arm/mach-pnx4008/include/mach/hardware.h
deleted file mode 100644
index 7b98b82..0000000
--- a/arch/arm/mach-pnx4008/include/mach/hardware.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/hardware.h
- *
- * Copyright (c) 2005 MontaVista Software, Inc. <source@mvista.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <asm/sizes.h>
-#include <mach/platform.h>
-
-/* Start of virtual addresses for IO devices */
-#define IO_BASE 0xF0000000
-
-/* This macro relies on fact that for all HW i/o addresses bits 20-23 are 0 */
-#define IO_ADDRESS(x) (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE)
-
-#endif
diff --git a/arch/arm/mach-pnx4008/include/mach/irq.h b/arch/arm/mach-pnx4008/include/mach/irq.h
deleted file mode 100644
index 2a690ca..0000000
--- a/arch/arm/mach-pnx4008/include/mach/irq.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/irq.h
- *
- * PNX4008 IRQ controller driver - header file
- * this one is used in entry-arnv.S as well so it cannot contain C code
- *
- * Copyright (c) 2005 Philips Semiconductors
- * Copyright (c) 2005 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-#ifndef __PNX4008_IRQ_H__
-#define __PNX4008_IRQ_H__
-
-#define MIC_VA_BASE IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
-#define SIC1_VA_BASE IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
-#define SIC2_VA_BASE IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
-
-/* Manual: Chapter 20, page 195 */
-
-#define INTC_BIT(irq) (1<< ((irq) & 0x1F))
-
-#define INTC_ER(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x0 + (((irq)&(0x3<<5))<<9)))
-#define INTC_RSR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x4 + (((irq)&(0x3<<5))<<9)))
-#define INTC_SR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x8 + (((irq)&(0x3<<5))<<9)))
-#define INTC_APR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0xC + (((irq)&(0x3<<5))<<9)))
-#define INTC_ATR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x10 + (((irq)&(0x3<<5))<<9)))
-#define INTC_ITR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x14 + (((irq)&(0x3<<5))<<9)))
-
-#define START_INT_REG_BIT(irq) (1<<((irq)&0x1F))
-
-#define START_INT_ER_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x20 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_RSR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x24 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_SR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x28 + (((irq)&(0x1<<5))>>1)))
-#define START_INT_APR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x2C + (((irq)&(0x1<<5))>>1)))
-
-extern void __init pnx4008_init_irq(void);
-
-#endif /* __PNX4008_IRQ_H__ */
diff --git a/arch/arm/mach-pnx4008/include/mach/irqs.h b/arch/arm/mach-pnx4008/include/mach/irqs.h
deleted file mode 100644
index f6b33cf..0000000
--- a/arch/arm/mach-pnx4008/include/mach/irqs.h
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/irqs.h
- *
- * PNX4008 IRQ controller driver - header file
- *
- * Author: Dmitry Chigirev <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef __PNX4008_IRQS_h__
-#define __PNX4008_IRQS_h__
-
-#define NR_IRQS 96
-
-/*Manual: table 259, page 199*/
-
-/*SUB2 Interrupt Routing (SIC2)*/
-
-#define SIC2_BASE_INT 64
-
-#define CLK_SWITCH_ARM_INT 95 /*manual: Clkswitch ARM */
-#define CLK_SWITCH_DSP_INT 94 /*manual: ClkSwitch DSP */
-#define CLK_SWITCH_AUD_INT 93 /*manual: Clkswitch AUD */
-#define GPI_06_INT 92
-#define GPI_05_INT 91
-#define GPI_04_INT 90
-#define GPI_03_INT 89
-#define GPI_02_INT 88
-#define GPI_01_INT 87
-#define GPI_00_INT 86
-#define BT_CLKREQ_INT 85
-#define SPI1_DATIN_INT 84
-#define U5_RX_INT 83
-#define SDIO_INT_N 82
-#define CAM_HS_INT 81
-#define CAM_VS_INT 80
-#define GPI_07_INT 79
-#define DISP_SYNC_INT 78
-#define DSP_INT8 77
-#define U7_HCTS_INT 76
-#define GPI_10_INT 75
-#define GPI_09_INT 74
-#define GPI_08_INT 73
-#define DSP_INT7 72
-#define U2_HCTS_INT 71
-#define SPI2_DATIN_INT 70
-#define GPIO_05_INT 69
-#define GPIO_04_INT 68
-#define GPIO_03_INT 67
-#define GPIO_02_INT 66
-#define GPIO_01_INT 65
-#define GPIO_00_INT 64
-
-/*Manual: table 258, page 198*/
-
-/*SUB1 Interrupt Routing (SIC1)*/
-
-#define SIC1_BASE_INT 32
-
-#define USB_I2C_INT 63
-#define USB_DEV_HP_INT 62
-#define USB_DEV_LP_INT 61
-#define USB_DEV_DMA_INT 60
-#define USB_HOST_INT 59
-#define USB_OTG_ATX_INT_N 58
-#define USB_OTG_TIMER_INT 57
-#define SW_INT 56
-#define SPI1_INT 55
-#define KEY_IRQ 54
-#define DSP_M_INT 53
-#define RTC_INT 52
-#define I2C_1_INT 51
-#define I2C_2_INT 50
-#define PLL1_LOCK_INT 49
-#define PLL2_LOCK_INT 48
-#define PLL3_LOCK_INT 47
-#define PLL4_LOCK_INT 46
-#define PLL5_LOCK_INT 45
-#define SPI2_INT 44
-#define DSP_INT1 43
-#define DSP_INT2 42
-#define DSP_TDM_INT2 41
-#define TS_AUX_INT 40
-#define TS_IRQ 39
-#define TS_P_INT 38
-#define UOUT1_TO_PAD_INT 37
-#define GPI_11_INT 36
-#define DSP_INT4 35
-#define JTAG_COMM_RX_INT 34
-#define JTAG_COMM_TX_INT 33
-#define DSP_INT3 32
-
-/*Manual: table 257, page 197*/
-
-/*MAIN Interrupt Routing*/
-
-#define MAIN_BASE_INT 0
-
-#define SUB2_FIQ_N 31 /*active low */
-#define SUB1_FIQ_N 30 /*active low */
-#define JPEG_INT 29
-#define DMA_INT 28
-#define MSTIMER_INT 27
-#define IIR1_INT 26
-#define IIR2_INT 25
-#define IIR7_INT 24
-#define DSP_TDM_INT0 23
-#define DSP_TDM_INT1 22
-#define DSP_P_INT 21
-#define DSP_INT0 20
-#define DUM_INT 19
-#define UOUT0_TO_PAD_INT 18
-#define MP4_ENC_INT 17
-#define MP4_DEC_INT 16
-#define SD0_INT 15
-#define MBX_INT 14
-#define SD1_INT 13
-#define MS_INT_N 12
-#define FLASH_INT 11 /*NAND*/
-#define IIR6_INT 10
-#define IIR5_INT 9
-#define IIR4_INT 8
-#define IIR3_INT 7
-#define WATCH_INT 6
-#define HSTIMER_INT 5
-#define ARCH_TIMER_IRQ HSTIMER_INT
-#define CAM_INT 4
-#define PRNG_INT 3
-#define CRYPTO_INT 2
-#define SUB2_IRQ_N 1 /*active low */
-#define SUB1_IRQ_N 0 /*active low */
-
-#define PNX4008_IRQ_TYPES \
-{ /*IRQ #'s: */ \
-IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, /* 0, 1, 2, 3 */ \
-IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 4, 5, 6, 7 */ \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 8, 9,10,11 */ \
-IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 12,13,14,15 */ \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 16,17,18,19 */ \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 20,21,22,23 */ \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 24,25,26,27 */ \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, /* 28,29,30,31 */ \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 32,33,34,35 */ \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_EDGE_FALLING, IRQ_TYPE_LEVEL_HIGH, /* 36,37,38,39 */ \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 40,41,42,43 */ \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 44,45,46,47 */ \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_LOW, /* 48,49,50,51 */ \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 52,53,54,55 */ \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_LOW, IRQ_TYPE_LEVEL_HIGH, /* 56,57,58,59 */ \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 60,61,62,63 */ \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 64,65,66,67 */ \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 68,69,70,71 */ \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 72,73,74,75 */ \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 76,77,78,79 */ \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 80,81,82,83 */ \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 84,85,86,87 */ \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 88,89,90,91 */ \
-IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, IRQ_TYPE_LEVEL_HIGH, /* 92,93,94,95 */ \
-}
-
-/* Start Enable Pin Interrupts - table 58 page 66 */
-
-#define SE_PIN_BASE_INT 32
-
-#define SE_U7_RX_INT 63
-#define SE_U7_HCTS_INT 62
-#define SE_BT_CLKREQ_INT 61
-#define SE_U6_IRRX_INT 60
-/*59 unused*/
-#define SE_U5_RX_INT 58
-#define SE_GPI_11_INT 57
-#define SE_U3_RX_INT 56
-#define SE_U2_HCTS_INT 55
-#define SE_U2_RX_INT 54
-#define SE_U1_RX_INT 53
-#define SE_DISP_SYNC_INT 52
-/*51 unused*/
-#define SE_SDIO_INT_N 50
-#define SE_MSDIO_START_INT 49
-#define SE_GPI_06_INT 48
-#define SE_GPI_05_INT 47
-#define SE_GPI_04_INT 46
-#define SE_GPI_03_INT 45
-#define SE_GPI_02_INT 44
-#define SE_GPI_01_INT 43
-#define SE_GPI_00_INT 42
-#define SE_SYSCLKEN_PIN_INT 41
-#define SE_SPI1_DATAIN_INT 40
-#define SE_GPI_07_INT 39
-#define SE_SPI2_DATAIN_INT 38
-#define SE_GPI_10_INT 37
-#define SE_GPI_09_INT 36
-#define SE_GPI_08_INT 35
-/*34-32 unused*/
-
-/* Start Enable Internal Interrupts - table 57 page 65 */
-
-#define SE_INT_BASE_INT 0
-
-#define SE_TS_IRQ 31
-#define SE_TS_P_INT 30
-#define SE_TS_AUX_INT 29
-/*27-28 unused*/
-#define SE_USB_AHB_NEED_CLK_INT 26
-#define SE_MSTIMER_INT 25
-#define SE_RTC_INT 24
-#define SE_USB_NEED_CLK_INT 23
-#define SE_USB_INT 22
-#define SE_USB_I2C_INT 21
-#define SE_USB_OTG_TIMER_INT 20
-
-#endif /* __PNX4008_IRQS_h__ */
diff --git a/arch/arm/mach-pnx4008/include/mach/param.h b/arch/arm/mach-pnx4008/include/mach/param.h
deleted file mode 100644
index 6ea02f2..0000000
--- a/arch/arm/mach-pnx4008/include/mach/param.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/param.h
- *
- * Copyright (C) 1999 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#define HZ 100
diff --git a/arch/arm/mach-pnx4008/include/mach/platform.h b/arch/arm/mach-pnx4008/include/mach/platform.h
deleted file mode 100644
index 368c2c1..0000000
--- a/arch/arm/mach-pnx4008/include/mach/platform.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/platform.h
- *
- * PNX4008 Base addresses - header file
- *
- * Author: Dmitry Chigirev <source@mvista.com>
- *
- * Based on reference code received from Philips:
- * Copyright (C) 2003 Philips Semiconductors
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-
-#ifndef __ASM_ARCH_PLATFORM_H__
-#define __ASM_ARCH_PLATFORM_H__
-
-#define PNX4008_IRAM_BASE 0x08000000
-#define PNX4008_IRAM_SIZE 0x00010000
-#define PNX4008_YUV_SLAVE_BASE 0x10000000
-#define PNX4008_DUM_SLAVE_BASE 0x18000000
-#define PNX4008_NDF_FLASH_BASE 0x20020000
-#define PNX4008_SPI1_BASE 0x20088000
-#define PNX4008_SPI2_BASE 0x20090000
-#define PNX4008_SD_CONFIG_BASE 0x20098000
-#define PNX4008_FLASH_DATA 0x200B0000
-#define PNX4008_MLC_FLASH_BASE 0x200B8000
-#define PNX4008_JPEG_CONFIG_BASE 0x300A0000
-#define PNX4008_DMA_CONFIG_BASE 0x31000000
-#define PNX4008_USB_CONFIG_BASE 0x31020000
-#define PNX4008_SDRAM_CFG_BASE 0x31080000
-#define PNX4008_AHB2FAB_BASE 0x40000000
-#define PNX4008_PWRMAN_BASE 0x40004000
-#define PNX4008_INTCTRLMIC_BASE 0x40008000
-#define PNX4008_INTCTRLSIC1_BASE 0x4000C000
-#define PNX4008_INTCTRLSIC2_BASE 0x40010000
-#define PNX4008_HSUART1_BASE 0x40014000
-#define PNX4008_HSUART2_BASE 0x40018000
-#define PNX4008_HSUART7_BASE 0x4001C000
-#define PNX4008_RTC_BASE 0x40024000
-#define PNX4008_PIO_BASE 0x40028000
-#define PNX4008_MSTIMER_BASE 0x40034000
-#define PNX4008_HSTIMER_BASE 0x40038000
-#define PNX4008_WDOG_BASE 0x4003C000
-#define PNX4008_DEBUG_BASE 0x40040000
-#define PNX4008_TOUCH1_BASE 0x40048000
-#define PNX4008_KEYSCAN_BASE 0x40050000
-#define PNX4008_UARTCTRL_BASE 0x40054000
-#define PNX4008_PWM_BASE 0x4005C000
-#define PNX4008_UART3_BASE 0x40080000
-#define PNX4008_UART4_BASE 0x40088000
-#define PNX4008_UART5_BASE 0x40090000
-#define PNX4008_UART6_BASE 0x40098000
-#define PNX4008_I2C1_BASE 0x400A0000
-#define PNX4008_I2C2_BASE 0x400A8000
-#define PNX4008_MAGICGATE_BASE 0x400B0000
-#define PNX4008_DUMCONF_BASE 0x400B8000
-#define PNX4008_DUM_MAINCFG_BASE 0x400BC000
-#define PNX4008_DSP_BASE 0x400C0000
-#define PNX4008_PROFCOUNTER_BASE 0x400C8000
-#define PNX4008_CRYPTO_BASE 0x400D0000
-#define PNX4008_CAMIFCONF_BASE 0x400D8000
-#define PNX4008_YUV2RGB_BASE 0x400E0000
-#define PNX4008_AUDIOCONFIG_BASE 0x400E8000
-
-#endif
diff --git a/arch/arm/mach-pnx4008/include/mach/pm.h b/arch/arm/mach-pnx4008/include/mach/pm.h
deleted file mode 100644
index 2fa685b..0000000
--- a/arch/arm/mach-pnx4008/include/mach/pm.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/pm.h
- *
- * PNX4008 Power Management Routiness - header file
- *
- * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef __ASM_ARCH_PNX4008_PM_H
-#define __ASM_ARCH_PNX4008_PM_H
-
-#ifndef __ASSEMBLER__
-#include "irq.h"
-#include "irqs.h"
-#include "clock.h"
-
-extern void pnx4008_pm_idle(void);
-extern void pnx4008_pm_suspend(void);
-extern unsigned int pnx4008_cpu_suspend_sz;
-extern void pnx4008_cpu_suspend(void);
-extern unsigned int pnx4008_cpu_standby_sz;
-extern void pnx4008_cpu_standby(void);
-
-extern int pnx4008_startup_pll(struct clk *);
-extern int pnx4008_shutdown_pll(struct clk *);
-
-#endif /* ASSEMBLER */
-#endif /* __ASM_ARCH_PNX4008_PM_H */
diff --git a/arch/arm/mach-pnx4008/include/mach/timex.h b/arch/arm/mach-pnx4008/include/mach/timex.h
deleted file mode 100644
index b383c7d..0000000
--- a/arch/arm/mach-pnx4008/include/mach/timex.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/timex.h
- *
- * PNX4008 timers header file
- *
- * Author: Dmitry Chigirev <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#ifndef __PNX4008_TIMEX_H
-#define __PNX4008_TIMEX_H
-
-#define CLOCK_TICK_RATE 1000000
-
-#endif
diff --git a/arch/arm/mach-pnx4008/include/mach/uncompress.h b/arch/arm/mach-pnx4008/include/mach/uncompress.h
deleted file mode 100644
index bb4751e..0000000
--- a/arch/arm/mach-pnx4008/include/mach/uncompress.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/uncompress.h
- *
- * Copyright (C) 1999 ARM Limited
- * Copyright (C) 2006 MontaVista Software, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#define UART5_BASE 0x40090000
-
-#define UART5_DR (*(volatile unsigned char *) (UART5_BASE))
-#define UART5_FR (*(volatile unsigned char *) (UART5_BASE + 18))
-
-static __inline__ void putc(char c)
-{
- while (UART5_FR & (1 << 5))
- barrier();
-
- UART5_DR = c;
-}
-
-/*
- * This does not append a newline
- */
-static inline void flush(void)
-{
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-pnx4008/irq.c b/arch/arm/mach-pnx4008/irq.c
deleted file mode 100644
index 41e4201..0000000
--- a/arch/arm/mach-pnx4008/irq.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/irq.c
- *
- * PNX4008 IRQ controller driver
- *
- * Author: Dmitry Chigirev <source@mvista.com>
- *
- * Based on reference code received from Philips:
- * Copyright (C) 2003 Philips Semiconductors
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/mm.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/device.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <asm/setup.h>
-#include <asm/pgtable.h>
-#include <asm/page.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/map.h>
-#include <mach/irq.h>
-
-static u8 pnx4008_irq_type[NR_IRQS] = PNX4008_IRQ_TYPES;
-
-static void pnx4008_mask_irq(struct irq_data *d)
-{
- __raw_writel(__raw_readl(INTC_ER(d->irq)) & ~INTC_BIT(d->irq), INTC_ER(d->irq)); /* mask interrupt */
-}
-
-static void pnx4008_unmask_irq(struct irq_data *d)
-{
- __raw_writel(__raw_readl(INTC_ER(d->irq)) | INTC_BIT(d->irq), INTC_ER(d->irq)); /* unmask interrupt */
-}
-
-static void pnx4008_mask_ack_irq(struct irq_data *d)
-{
- __raw_writel(__raw_readl(INTC_ER(d->irq)) & ~INTC_BIT(d->irq), INTC_ER(d->irq)); /* mask interrupt */
- __raw_writel(INTC_BIT(d->irq), INTC_SR(d->irq)); /* clear interrupt status */
-}
-
-static int pnx4008_set_irq_type(struct irq_data *d, unsigned int type)
-{
- switch (type) {
- case IRQ_TYPE_EDGE_RISING:
- __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */
- __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /*rising edge */
- irq_set_handler(d->irq, handle_edge_irq);
- break;
- case IRQ_TYPE_EDGE_FALLING:
- __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */
- __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*falling edge */
- irq_set_handler(d->irq, handle_edge_irq);
- break;
- case IRQ_TYPE_LEVEL_LOW:
- __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */
- __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*low level */
- irq_set_handler(d->irq, handle_level_irq);
- break;
- case IRQ_TYPE_LEVEL_HIGH:
- __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */
- __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /* high level */
- irq_set_handler(d->irq, handle_level_irq);
- break;
-
- /* IRQ_TYPE_EDGE_BOTH is not supported */
- default:
- printk(KERN_ERR "PNX4008 IRQ: Unsupported irq type %d\n", type);
- return -1;
- }
- return 0;
-}
-
-static struct irq_chip pnx4008_irq_chip = {
- .irq_ack = pnx4008_mask_ack_irq,
- .irq_mask = pnx4008_mask_irq,
- .irq_unmask = pnx4008_unmask_irq,
- .irq_set_type = pnx4008_set_irq_type,
-};
-
-void __init pnx4008_init_irq(void)
-{
- unsigned int i;
-
- /* configure IRQ's */
- for (i = 0; i < NR_IRQS; i++) {
- set_irq_flags(i, IRQF_VALID);
- irq_set_chip(i, &pnx4008_irq_chip);
- pnx4008_set_irq_type(irq_get_irq_data(i), pnx4008_irq_type[i]);
- }
-
- /* configure and enable IRQ 0,1,30,31 (cascade interrupts) */
- pnx4008_set_irq_type(irq_get_irq_data(SUB1_IRQ_N),
- pnx4008_irq_type[SUB1_IRQ_N]);
- pnx4008_set_irq_type(irq_get_irq_data(SUB2_IRQ_N),
- pnx4008_irq_type[SUB2_IRQ_N]);
- pnx4008_set_irq_type(irq_get_irq_data(SUB1_FIQ_N),
- pnx4008_irq_type[SUB1_FIQ_N]);
- pnx4008_set_irq_type(irq_get_irq_data(SUB2_FIQ_N),
- pnx4008_irq_type[SUB2_FIQ_N]);
-
- /* mask all others */
- __raw_writel((1 << SUB2_FIQ_N) | (1 << SUB1_FIQ_N) |
- (1 << SUB2_IRQ_N) | (1 << SUB1_IRQ_N),
- INTC_ER(MAIN_BASE_INT));
- __raw_writel(0, INTC_ER(SIC1_BASE_INT));
- __raw_writel(0, INTC_ER(SIC2_BASE_INT));
-}
-
diff --git a/arch/arm/mach-pnx4008/pm.c b/arch/arm/mach-pnx4008/pm.c
deleted file mode 100644
index 26f8d06..0000000
--- a/arch/arm/mach-pnx4008/pm.c
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/pm.c
- *
- * Power Management driver for PNX4008
- *
- * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/pm.h>
-#include <linux/rtc.h>
-#include <linux/sched.h>
-#include <linux/proc_fs.h>
-#include <linux/suspend.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-
-#include <asm/cacheflush.h>
-
-#include <mach/hardware.h>
-#include <mach/pm.h>
-#include <mach/clock.h>
-
-#define SRAM_VA IO_ADDRESS(PNX4008_IRAM_BASE)
-
-static void *saved_sram;
-
-static struct clk *pll4_clk;
-
-static inline void pnx4008_standby(void)
-{
- void (*pnx4008_cpu_standby_ptr) (void);
-
- local_irq_disable();
- local_fiq_disable();
-
- clk_disable(pll4_clk);
-
- /*saving portion of SRAM to be used by suspend function. */
- memcpy(saved_sram, (void *)SRAM_VA, pnx4008_cpu_standby_sz);
-
- /*make sure SRAM copy gets physically written into SDRAM.
- SDRAM will be placed into self-refresh during power down */
- flush_cache_all();
-
- /*copy suspend function into SRAM */
- memcpy((void *)SRAM_VA, pnx4008_cpu_standby, pnx4008_cpu_standby_sz);
-
- /*do suspend */
- pnx4008_cpu_standby_ptr = (void *)SRAM_VA;
- pnx4008_cpu_standby_ptr();
-
- /*restoring portion of SRAM that was used by suspend function */
- memcpy((void *)SRAM_VA, saved_sram, pnx4008_cpu_standby_sz);
-
- clk_enable(pll4_clk);
-
- local_fiq_enable();
- local_irq_enable();
-}
-
-static inline void pnx4008_suspend(void)
-{
- void (*pnx4008_cpu_suspend_ptr) (void);
-
- local_irq_disable();
- local_fiq_disable();
-
- clk_disable(pll4_clk);
-
- __raw_writel(0xffffffff, START_INT_RSR_REG(SE_PIN_BASE_INT));
- __raw_writel(0xffffffff, START_INT_RSR_REG(SE_INT_BASE_INT));
-
- /*saving portion of SRAM to be used by suspend function. */
- memcpy(saved_sram, (void *)SRAM_VA, pnx4008_cpu_suspend_sz);
-
- /*make sure SRAM copy gets physically written into SDRAM.
- SDRAM will be placed into self-refresh during power down */
- flush_cache_all();
-
- /*copy suspend function into SRAM */
- memcpy((void *)SRAM_VA, pnx4008_cpu_suspend, pnx4008_cpu_suspend_sz);
-
- /*do suspend */
- pnx4008_cpu_suspend_ptr = (void *)SRAM_VA;
- pnx4008_cpu_suspend_ptr();
-
- /*restoring portion of SRAM that was used by suspend function */
- memcpy((void *)SRAM_VA, saved_sram, pnx4008_cpu_suspend_sz);
-
- clk_enable(pll4_clk);
-
- local_fiq_enable();
- local_irq_enable();
-}
-
-static int pnx4008_pm_enter(suspend_state_t state)
-{
- switch (state) {
- case PM_SUSPEND_STANDBY:
- pnx4008_standby();
- break;
- case PM_SUSPEND_MEM:
- pnx4008_suspend();
- break;
- }
- return 0;
-}
-
-static int pnx4008_pm_valid(suspend_state_t state)
-{
- return (state == PM_SUSPEND_STANDBY) ||
- (state == PM_SUSPEND_MEM);
-}
-
-static const struct platform_suspend_ops pnx4008_pm_ops = {
- .enter = pnx4008_pm_enter,
- .valid = pnx4008_pm_valid,
-};
-
-int __init pnx4008_pm_init(void)
-{
- u32 sram_size_to_allocate;
-
- pll4_clk = clk_get(0, "ck_pll4");
- if (IS_ERR(pll4_clk)) {
- printk(KERN_ERR
- "PM Suspend cannot acquire ARM(PLL4) clock control\n");
- return PTR_ERR(pll4_clk);
- }
-
- if (pnx4008_cpu_standby_sz > pnx4008_cpu_suspend_sz)
- sram_size_to_allocate = pnx4008_cpu_standby_sz;
- else
- sram_size_to_allocate = pnx4008_cpu_suspend_sz;
-
- saved_sram = kmalloc(sram_size_to_allocate, GFP_ATOMIC);
- if (!saved_sram) {
- printk(KERN_ERR
- "PM Suspend: cannot allocate memory to save portion of SRAM\n");
- clk_put(pll4_clk);
- return -ENOMEM;
- }
-
- suspend_set_ops(&pnx4008_pm_ops);
- return 0;
-}
diff --git a/arch/arm/mach-pnx4008/serial.c b/arch/arm/mach-pnx4008/serial.c
deleted file mode 100644
index 374c138..0000000
--- a/arch/arm/mach-pnx4008/serial.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * linux/arch/arm/mach-pnx4008/serial.c
- *
- * PNX4008 UART initialization
- *
- * Copyright: MontaVista Software Inc. (c) 2005
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/io.h>
-
-#include <mach/platform.h>
-#include <mach/hardware.h>
-
-#include <linux/serial_core.h>
-#include <linux/serial_reg.h>
-
-#include <mach/gpio-pnx4008.h>
-#include <mach/clock.h>
-
-#define UART_3 0
-#define UART_4 1
-#define UART_5 2
-#define UART_6 3
-#define UART_UNKNOWN (-1)
-
-#define UART3_BASE_VA IO_ADDRESS(PNX4008_UART3_BASE)
-#define UART4_BASE_VA IO_ADDRESS(PNX4008_UART4_BASE)
-#define UART5_BASE_VA IO_ADDRESS(PNX4008_UART5_BASE)
-#define UART6_BASE_VA IO_ADDRESS(PNX4008_UART6_BASE)
-
-#define UART_FCR_OFFSET 8
-#define UART_FIFO_SIZE 64
-
-void pnx4008_uart_init(void)
-{
- u32 tmp;
- int i = UART_FIFO_SIZE;
-
- __raw_writel(0xC1, UART5_BASE_VA + UART_FCR_OFFSET);
- __raw_writel(0xC1, UART3_BASE_VA + UART_FCR_OFFSET);
-
- /* Send a NULL to fix the UART HW bug */
- __raw_writel(0x00, UART5_BASE_VA);
- __raw_writel(0x00, UART3_BASE_VA);
-
- while (i--) {
- tmp = __raw_readl(UART5_BASE_VA);
- tmp = __raw_readl(UART3_BASE_VA);
- }
- __raw_writel(0, UART5_BASE_VA + UART_FCR_OFFSET);
- __raw_writel(0, UART3_BASE_VA + UART_FCR_OFFSET);
-
- /* setup wakeup interrupt */
- start_int_set_rising_edge(SE_U3_RX_INT);
- start_int_ack(SE_U3_RX_INT);
- start_int_umask(SE_U3_RX_INT);
-
- start_int_set_rising_edge(SE_U5_RX_INT);
- start_int_ack(SE_U5_RX_INT);
- start_int_umask(SE_U5_RX_INT);
-}
-
diff --git a/arch/arm/mach-pnx4008/sleep.S b/arch/arm/mach-pnx4008/sleep.S
deleted file mode 100644
index f4eed49..0000000
--- a/arch/arm/mach-pnx4008/sleep.S
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * linux/arch/arm/mach-pnx4008/sleep.S
- *
- * PNX4008 support for STOP mode and SDRAM self-refresh
- *
- * Authors: Dmitry Chigirev, Vitaly Wool <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include <mach/hardware.h>
-
-#define PWRMAN_VA_BASE IO_ADDRESS(PNX4008_PWRMAN_BASE)
-#define PWR_CTRL_REG_OFFS 0x44
-
-#define SDRAM_CFG_VA_BASE IO_ADDRESS(PNX4008_SDRAM_CFG_BASE)
-#define MPMC_STATUS_REG_OFFS 0x4
-
- .text
-
-ENTRY(pnx4008_cpu_suspend)
- @this function should be entered in Direct run mode.
-
- @ save registers on stack
- stmfd sp!, {r0 - r6, lr}
-
- @ setup Power Manager base address in r4
- @ and put it's value in r5
- mov r4, #(PWRMAN_VA_BASE & 0xff000000)
- orr r4, r4, #(PWRMAN_VA_BASE & 0x00ff0000)
- orr r4, r4, #(PWRMAN_VA_BASE & 0x0000ff00)
- orr r4, r4, #(PWRMAN_VA_BASE & 0x000000ff)
- ldr r5, [r4, #PWR_CTRL_REG_OFFS]
-
- @ setup SDRAM controller base address in r2
- @ and put it's value in r3
- mov r2, #(SDRAM_CFG_VA_BASE & 0xff000000)
- orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x00ff0000)
- orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x0000ff00)
- orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x000000ff)
- ldr r3, [r2, #MPMC_STATUS_REG_OFFS] @extra read - HW bug workaround
-
- @ clear SDRAM self-refresh bit latch
- and r5, r5, #(~(1 << 8))
- @ clear SDRAM self-refresh bit
- and r5, r5, #(~(1 << 9))
- str r5, [r4, #PWR_CTRL_REG_OFFS]
-
- @ do save current bit settings in r1
- mov r1, r5
-
- @ set SDRAM self-refresh bit
- orr r5, r5, #(1 << 9)
- str r5, [r4, #PWR_CTRL_REG_OFFS]
-
- @ set SDRAM self-refresh bit latch
- orr r5, r5, #(1 << 8)
- str r5, [r4, #PWR_CTRL_REG_OFFS]
-
- @ clear SDRAM self-refresh bit latch
- and r5, r5, #(~(1 << 8))
- str r5, [r4, #PWR_CTRL_REG_OFFS]
-
- @ clear SDRAM self-refresh bit
- and r5, r5, #(~(1 << 9))
- str r5, [r4, #PWR_CTRL_REG_OFFS]
-
- @ wait for SDRAM to get into self-refresh mode
-2: ldr r3, [r2, #MPMC_STATUS_REG_OFFS]
- tst r3, #(1 << 2)
- beq 2b
-
- @ to prepare SDRAM to get out of self-refresh mode after wakeup
- orr r5, r5, #(1 << 7)
- str r5, [r4, #PWR_CTRL_REG_OFFS]
-
- @ do enter stop mode
- orr r5, r5, #(1 << 0)
- str r5, [r4, #PWR_CTRL_REG_OFFS]
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
- nop
-
- @ sleeping now...
-
- @ coming out of STOP mode into Direct Run mode
- @ clear STOP mode and SDRAM self-refresh bits
- str r1, [r4, #PWR_CTRL_REG_OFFS]
-
- @ wait for SDRAM to get out self-refresh mode
-3: ldr r3, [r2, #MPMC_STATUS_REG_OFFS]
- tst r3, #5
- bne 3b
-
- @ restore regs and return
- ldmfd sp!, {r0 - r6, pc}
-
-ENTRY(pnx4008_cpu_suspend_sz)
- .word . - pnx4008_cpu_suspend
-
-ENTRY(pnx4008_cpu_standby)
- @ save registers on stack
- stmfd sp!, {r0 - r6, lr}
-
- @ setup Power Manager base address in r4
- @ and put it's value in r5
- mov r4, #(PWRMAN_VA_BASE & 0xff000000)
- orr r4, r4, #(PWRMAN_VA_BASE & 0x00ff0000)
- orr r4, r4, #(PWRMAN_VA_BASE & 0x0000ff00)
- orr r4, r4, #(PWRMAN_VA_BASE & 0x000000ff)
- ldr r5, [r4, #PWR_CTRL_REG_OFFS]
-
- @ setup SDRAM controller base address in r2
- @ and put it's value in r3
- mov r2, #(SDRAM_CFG_VA_BASE & 0xff000000)
- orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x00ff0000)
- orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x0000ff00)
- orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x000000ff)
- ldr r3, [r2, #MPMC_STATUS_REG_OFFS] @extra read - HW bug workaround
-
- @ clear SDRAM self-refresh bit latch
- and r5, r5, #(~(1 << 8))
- @ clear SDRAM self-refresh bit
- and r5, r5, #(~(1 << 9))
- str r5, [r4, #PWR_CTRL_REG_OFFS]
-
- @ do save current bit settings in r1
- mov r1, r5
-
- @ set SDRAM self-refresh bit
- orr r5, r5, #(1 << 9)
- str r5, [r4, #PWR_CTRL_REG_OFFS]
-
- @ set SDRAM self-refresh bit latch
- orr r5, r5, #(1 << 8)
- str r5, [r4, #PWR_CTRL_REG_OFFS]
-
- @ clear SDRAM self-refresh bit latch
- and r5, r5, #(~(1 << 8))
- str r5, [r4, #PWR_CTRL_REG_OFFS]
-
- @ clear SDRAM self-refresh bit
- and r5, r5, #(~(1 << 9))
- str r5, [r4, #PWR_CTRL_REG_OFFS]
-
- @ wait for SDRAM to get into self-refresh mode
-2: ldr r3, [r2, #MPMC_STATUS_REG_OFFS]
- tst r3, #(1 << 2)
- beq 2b
-
- @ set 'get out of self-refresh mode after wakeup' bit
- orr r5, r5, #(1 << 7)
- str r5, [r4, #PWR_CTRL_REG_OFFS]
-
- mcr p15, 0, r0, c7, c0, 4 @ kinda sleeping now...
-
- @ set SDRAM self-refresh bit latch
- orr r5, r5, #(1 << 8)
- str r5, [r4, #PWR_CTRL_REG_OFFS]
-
- @ clear SDRAM self-refresh bit latch
- and r5, r5, #(~(1 << 8))
- str r5, [r4, #PWR_CTRL_REG_OFFS]
-
- @ wait for SDRAM to get out self-refresh mode
-3: ldr r3, [r2, #MPMC_STATUS_REG_OFFS]
- tst r3, #5
- bne 3b
-
- @ restore regs and return
- ldmfd sp!, {r0 - r6, pc}
-
-ENTRY(pnx4008_cpu_standby_sz)
- .word . - pnx4008_cpu_standby
-
-ENTRY(pnx4008_cache_clean_invalidate)
- stmfd sp!, {r0 - r6, lr}
-#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
- mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
-#else
-1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
- bne 1b
-#endif
- ldmfd sp!, {r0 - r6, pc}
diff --git a/arch/arm/mach-pnx4008/time.c b/arch/arm/mach-pnx4008/time.c
deleted file mode 100644
index 0cfe8af..0000000
--- a/arch/arm/mach-pnx4008/time.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/time.c
- *
- * PNX4008 Timers
- *
- * Authors: Vitaly Wool, Dmitry Chigirev, Grigory Tolstolytkin <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/delay.h>
-#include <linux/interrupt.h>
-#include <linux/sched.h>
-#include <linux/spinlock.h>
-#include <linux/module.h>
-#include <linux/kallsyms.h>
-#include <linux/time.h>
-#include <linux/timex.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/leds.h>
-#include <asm/mach/time.h>
-#include <asm/errno.h>
-
-#include "time.h"
-
-/*! Note: all timers are UPCOUNTING */
-
-/*!
- * Returns number of us since last clock interrupt. Note that interrupts
- * will have been disabled by do_gettimeoffset()
- */
-static unsigned long pnx4008_gettimeoffset(void)
-{
- u32 ticks_to_match =
- __raw_readl(HSTIM_MATCH0) - __raw_readl(HSTIM_COUNTER);
- u32 elapsed = LATCH - ticks_to_match;
- return (elapsed * (tick_nsec / 1000)) / LATCH;
-}
-
-/*!
- * IRQ handler for the timer
- */
-static irqreturn_t pnx4008_timer_interrupt(int irq, void *dev_id)
-{
- if (__raw_readl(HSTIM_INT) & MATCH0_INT) {
-
- do {
- timer_tick();
-
- /*
- * this algorithm takes care of possible delay
- * for this interrupt handling longer than a normal
- * timer period
- */
- __raw_writel(__raw_readl(HSTIM_MATCH0) + LATCH,
- HSTIM_MATCH0);
- __raw_writel(MATCH0_INT, HSTIM_INT); /* clear interrupt */
-
- /*
- * The goal is to keep incrementing HSTIM_MATCH0
- * register until HSTIM_MATCH0 indicates time after
- * what HSTIM_COUNTER indicates.
- */
- } while ((signed)
- (__raw_readl(HSTIM_MATCH0) -
- __raw_readl(HSTIM_COUNTER)) < 0);
- }
-
- return IRQ_HANDLED;
-}
-
-static struct irqaction pnx4008_timer_irq = {
- .name = "PNX4008 Tick Timer",
- .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
- .handler = pnx4008_timer_interrupt
-};
-
-/*!
- * Set up timer and timer interrupt.
- */
-static __init void pnx4008_setup_timer(void)
-{
- __raw_writel(RESET_COUNT, MSTIM_CTRL);
- while (__raw_readl(MSTIM_COUNTER)) ; /* wait for reset to complete. 100% guarantee event */
- __raw_writel(0, MSTIM_CTRL); /* stop the timer */
- __raw_writel(0, MSTIM_MCTRL);
-
- __raw_writel(RESET_COUNT, HSTIM_CTRL);
- while (__raw_readl(HSTIM_COUNTER)) ; /* wait for reset to complete. 100% guarantee event */
- __raw_writel(0, HSTIM_CTRL);
- __raw_writel(0, HSTIM_MCTRL);
- __raw_writel(0, HSTIM_CCR);
- __raw_writel(12, HSTIM_PMATCH); /* scale down to 1 MHZ */
- __raw_writel(LATCH, HSTIM_MATCH0);
- __raw_writel(MR0_INT, HSTIM_MCTRL);
-
- setup_irq(HSTIMER_INT, &pnx4008_timer_irq);
-
- __raw_writel(COUNT_ENAB | DEBUG_EN, HSTIM_CTRL); /*start timer, stop when JTAG active */
-}
-
-/* Timer Clock Control in PM register */
-#define TIMCLK_CTRL_REG IO_ADDRESS((PNX4008_PWRMAN_BASE + 0xBC))
-#define WATCHDOG_CLK_EN 1
-#define TIMER_CLK_EN 2 /* HS and MS timers? */
-
-static u32 timclk_ctrl_reg_save;
-
-void pnx4008_timer_suspend(void)
-{
- timclk_ctrl_reg_save = __raw_readl(TIMCLK_CTRL_REG);
- __raw_writel(0, TIMCLK_CTRL_REG); /* disable timers */
-}
-
-void pnx4008_timer_resume(void)
-{
- __raw_writel(timclk_ctrl_reg_save, TIMCLK_CTRL_REG); /* enable timers */
-}
-
-struct sys_timer pnx4008_timer = {
- .init = pnx4008_setup_timer,
- .offset = pnx4008_gettimeoffset,
- .suspend = pnx4008_timer_suspend,
- .resume = pnx4008_timer_resume,
-};
-
diff --git a/arch/arm/mach-pnx4008/time.h b/arch/arm/mach-pnx4008/time.h
deleted file mode 100644
index 75e88c5..0000000
--- a/arch/arm/mach-pnx4008/time.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * arch/arm/mach-pnx4008/include/mach/timex.h
- *
- * PNX4008 timers header file
- *
- * Author: Dmitry Chigirev <source@mvista.com>
- *
- * 2005 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- */
-#ifndef PNX_TIME_H
-#define PNX_TIME_H
-
-#include <linux/io.h>
-#include <mach/hardware.h>
-
-#define TICKS2USECS(x) (x)
-
-/* MilliSecond Timer - Chapter 21 Page 202 */
-
-#define MSTIM_INT IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x0))
-#define MSTIM_CTRL IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x4))
-#define MSTIM_COUNTER IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x8))
-#define MSTIM_MCTRL IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x14))
-#define MSTIM_MATCH0 IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x18))
-#define MSTIM_MATCH1 IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x1c))
-
-/* High Speed Timer - Chpater 22, Page 205 */
-
-#define HSTIM_INT IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x0))
-#define HSTIM_CTRL IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x4))
-#define HSTIM_COUNTER IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x8))
-#define HSTIM_PMATCH IO_ADDRESS((PNX4008_HSTIMER_BASE + 0xC))
-#define HSTIM_PCOUNT IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x10))
-#define HSTIM_MCTRL IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x14))
-#define HSTIM_MATCH0 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x18))
-#define HSTIM_MATCH1 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x1c))
-#define HSTIM_MATCH2 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x20))
-#define HSTIM_CCR IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x28))
-#define HSTIM_CR0 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x2C))
-#define HSTIM_CR1 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x30))
-
-/* IMPORTANT: both timers are UPCOUNTING */
-
-/* xSTIM_MCTRL bit definitions */
-#define MR0_INT 1
-#define RESET_COUNT0 (1<<1)
-#define STOP_COUNT0 (1<<2)
-#define MR1_INT (1<<3)
-#define RESET_COUNT1 (1<<4)
-#define STOP_COUNT1 (1<<5)
-#define MR2_INT (1<<6)
-#define RESET_COUNT2 (1<<7)
-#define STOP_COUNT2 (1<<8)
-
-/* xSTIM_CTRL bit definitions */
-#define COUNT_ENAB 1
-#define RESET_COUNT (1<<1)
-#define DEBUG_EN (1<<2)
-
-/* xSTIM_INT bit definitions */
-#define MATCH0_INT 1
-#define MATCH1_INT (1<<1)
-#define MATCH2_INT (1<<2)
-#define RTC_TICK0 (1<<4)
-#define RTC_TICK1 (1<<5)
-
-#endif
diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig
new file mode 100644
index 0000000..41fc853
--- /dev/null
+++ b/arch/arm/mach-prima2/Kconfig
@@ -0,0 +1,19 @@
+if ARCH_SIRF
+
+menu "CSR SiRF primaII/Marco/Polo Specific Features"
+
+config ARCH_PRIMA2
+ bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
+ default y
+ select CPU_V7
+ select ZONE_DMA
+ select SIRF_IRQ
+ help
+ Support for CSR SiRFSoC ARM Cortex A9 Platform
+
+endmenu
+
+config SIRF_IRQ
+ bool
+
+endif
diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile
index 13dd160..fc9ce22 100644
--- a/arch/arm/mach-prima2/Makefile
+++ b/arch/arm/mach-prima2/Makefile
@@ -1,9 +1,8 @@
obj-y := timer.o
-obj-y += irq.o
-obj-y += clock.o
obj-y += rstc.o
-obj-y += prima2.o
+obj-y += common.o
obj-y += rtciobrg.o
obj-$(CONFIG_DEBUG_LL) += lluart.o
obj-$(CONFIG_CACHE_L2X0) += l2x0.o
obj-$(CONFIG_SUSPEND) += pm.o sleep.o
+obj-$(CONFIG_SIRF_IRQ) += irq.o
diff --git a/arch/arm/mach-prima2/clock.c b/arch/arm/mach-prima2/clock.c
deleted file mode 100644
index aebad7e..0000000
--- a/arch/arm/mach-prima2/clock.c
+++ /dev/null
@@ -1,510 +0,0 @@
-/*
- * Clock tree for CSR SiRFprimaII
- *
- * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
- *
- * Licensed under GPLv2 or later.
- */
-
-#include <linux/module.h>
-#include <linux/bitops.h>
-#include <linux/err.h>
-#include <linux/errno.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-#include <linux/clk.h>
-#include <linux/spinlock.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <asm/mach/map.h>
-#include <mach/map.h>
-
-#define SIRFSOC_CLKC_CLK_EN0 0x0000
-#define SIRFSOC_CLKC_CLK_EN1 0x0004
-#define SIRFSOC_CLKC_REF_CFG 0x0014
-#define SIRFSOC_CLKC_CPU_CFG 0x0018
-#define SIRFSOC_CLKC_MEM_CFG 0x001c
-#define SIRFSOC_CLKC_SYS_CFG 0x0020
-#define SIRFSOC_CLKC_IO_CFG 0x0024
-#define SIRFSOC_CLKC_DSP_CFG 0x0028
-#define SIRFSOC_CLKC_GFX_CFG 0x002c
-#define SIRFSOC_CLKC_MM_CFG 0x0030
-#define SIRFSOC_LKC_LCD_CFG 0x0034
-#define SIRFSOC_CLKC_MMC_CFG 0x0038
-#define SIRFSOC_CLKC_PLL1_CFG0 0x0040
-#define SIRFSOC_CLKC_PLL2_CFG0 0x0044
-#define SIRFSOC_CLKC_PLL3_CFG0 0x0048
-#define SIRFSOC_CLKC_PLL1_CFG1 0x004c
-#define SIRFSOC_CLKC_PLL2_CFG1 0x0050
-#define SIRFSOC_CLKC_PLL3_CFG1 0x0054
-#define SIRFSOC_CLKC_PLL1_CFG2 0x0058
-#define SIRFSOC_CLKC_PLL2_CFG2 0x005c
-#define SIRFSOC_CLKC_PLL3_CFG2 0x0060
-
-#define SIRFSOC_CLOCK_VA_BASE SIRFSOC_VA(0x005000)
-
-#define KHZ 1000
-#define MHZ (KHZ * KHZ)
-
-struct clk_ops {
- unsigned long (*get_rate)(struct clk *clk);
- long (*round_rate)(struct clk *clk, unsigned long rate);
- int (*set_rate)(struct clk *clk, unsigned long rate);
- int (*enable)(struct clk *clk);
- int (*disable)(struct clk *clk);
- struct clk *(*get_parent)(struct clk *clk);
- int (*set_parent)(struct clk *clk, struct clk *parent);
-};
-
-struct clk {
- struct clk *parent; /* parent clk */
- unsigned long rate; /* clock rate in Hz */
- signed char usage; /* clock enable count */
- signed char enable_bit; /* enable bit: 0 ~ 63 */
- unsigned short regofs; /* register offset */
- struct clk_ops *ops; /* clock operation */
-};
-
-static DEFINE_SPINLOCK(clocks_lock);
-
-static inline unsigned long clkc_readl(unsigned reg)
-{
- return readl(SIRFSOC_CLOCK_VA_BASE + reg);
-}
-
-static inline void clkc_writel(u32 val, unsigned reg)
-{
- writel(val, SIRFSOC_CLOCK_VA_BASE + reg);
-}
-
-/*
- * osc_rtc - real time oscillator - 32.768KHz
- * osc_sys - high speed oscillator - 26MHz
- */
-
-static struct clk clk_rtc = {
- .rate = 32768,
-};
-
-static struct clk clk_osc = {
- .rate = 26 * MHZ,
-};
-
-/*
- * std pll
- */
-static unsigned long std_pll_get_rate(struct clk *clk)
-{
- unsigned long fin = clk_get_rate(clk->parent);
- u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 -
- SIRFSOC_CLKC_PLL1_CFG0;
-
- if (clkc_readl(regcfg2) & BIT(2)) {
- /* pll bypass mode */
- clk->rate = fin;
- } else {
- /* fout = fin * nf / nr / od */
- u32 cfg0 = clkc_readl(clk->regofs);
- u32 nf = (cfg0 & (BIT(13) - 1)) + 1;
- u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1;
- u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1;
- WARN_ON(fin % MHZ);
- clk->rate = fin / MHZ * nf / nr / od * MHZ;
- }
-
- return clk->rate;
-}
-
-static int std_pll_set_rate(struct clk *clk, unsigned long rate)
-{
- unsigned long fin, nf, nr, od, reg;
-
- /*
- * fout = fin * nf / (nr * od);
- * set od = 1, nr = fin/MHz, so fout = nf * MHz
- */
-
- nf = rate / MHZ;
- if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1))
- return -EINVAL;
-
- fin = clk_get_rate(clk->parent);
- BUG_ON(fin < MHZ);
-
- nr = fin / MHZ;
- BUG_ON((fin % MHZ) || nr > BIT(6));
-
- od = 1;
-
- reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19);
- clkc_writel(reg, clk->regofs);
-
- reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0;
- clkc_writel((nf >> 1) - 1, reg);
-
- reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0;
- while (!(clkc_readl(reg) & BIT(6)))
- cpu_relax();
-
- clk->rate = 0; /* set to zero will force recalculation */
- return 0;
-}
-
-static struct clk_ops std_pll_ops = {
- .get_rate = std_pll_get_rate,
- .set_rate = std_pll_set_rate,
-};
-
-static struct clk clk_pll1 = {
- .parent = &clk_osc,
- .regofs = SIRFSOC_CLKC_PLL1_CFG0,
- .ops = &std_pll_ops,
-};
-
-static struct clk clk_pll2 = {
- .parent = &clk_osc,
- .regofs = SIRFSOC_CLKC_PLL2_CFG0,
- .ops = &std_pll_ops,
-};
-
-static struct clk clk_pll3 = {
- .parent = &clk_osc,
- .regofs = SIRFSOC_CLKC_PLL3_CFG0,
- .ops = &std_pll_ops,
-};
-
-/*
- * clock domains - cpu, mem, sys/io
- */
-
-static struct clk clk_mem;
-
-static struct clk *dmn_get_parent(struct clk *clk)
-{
- struct clk *clks[] = {
- &clk_osc, &clk_rtc, &clk_pll1, &clk_pll2, &clk_pll3
- };
- u32 cfg = clkc_readl(clk->regofs);
- WARN_ON((cfg & (BIT(3) - 1)) > 4);
- return clks[cfg & (BIT(3) - 1)];
-}
-
-static int dmn_set_parent(struct clk *clk, struct clk *parent)
-{
- const struct clk *clks[] = {
- &clk_osc, &clk_rtc, &clk_pll1, &clk_pll2, &clk_pll3
- };
- u32 cfg = clkc_readl(clk->regofs);
- int i;
- for (i = 0; i < ARRAY_SIZE(clks); i++) {
- if (clks[i] == parent) {
- cfg &= ~(BIT(3) - 1);
- clkc_writel(cfg | i, clk->regofs);
- /* BIT(3) - switching status: 1 - busy, 0 - done */
- while (clkc_readl(clk->regofs) & BIT(3))
- cpu_relax();
- return 0;
- }
- }
- return -EINVAL;
-}
-
-static unsigned long dmn_get_rate(struct clk *clk)
-{
- unsigned long fin = clk_get_rate(clk->parent);
- u32 cfg = clkc_readl(clk->regofs);
- if (cfg & BIT(24)) {
- /* fcd bypass mode */
- clk->rate = fin;
- } else {
- /*
- * wait count: bit[19:16], hold count: bit[23:20]
- */
- u32 wait = (cfg >> 16) & (BIT(4) - 1);
- u32 hold = (cfg >> 20) & (BIT(4) - 1);
-
- clk->rate = fin / (wait + hold + 2);
- }
-
- return clk->rate;
-}
-
-static int dmn_set_rate(struct clk *clk, unsigned long rate)
-{
- unsigned long fin;
- unsigned ratio, wait, hold, reg;
- unsigned bits = (clk == &clk_mem) ? 3 : 4;
-
- fin = clk_get_rate(clk->parent);
- ratio = fin / rate;
-
- if (unlikely(ratio < 2 || ratio > BIT(bits + 1)))
- return -EINVAL;
-
- WARN_ON(fin % rate);
-
- wait = (ratio >> 1) - 1;
- hold = ratio - wait - 2;
-
- reg = clkc_readl(clk->regofs);
- reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20));
- reg |= (wait << 16) | (hold << 20) | BIT(25);
- clkc_writel(reg, clk->regofs);
-
- /* waiting FCD been effective */
- while (clkc_readl(clk->regofs) & BIT(25))
- cpu_relax();
-
- clk->rate = 0; /* set to zero will force recalculation */
-
- return 0;
-}
-
-/*
- * cpu clock has no FCD register in Prima2, can only change pll
- */
-static int cpu_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret1, ret2;
- struct clk *cur_parent, *tmp_parent;
-
- cur_parent = dmn_get_parent(clk);
- BUG_ON(cur_parent == NULL || cur_parent->usage > 1);
-
- /* switch to tmp pll before setting parent clock's rate */
- tmp_parent = cur_parent == &clk_pll1 ? &clk_pll2 : &clk_pll1;
- ret1 = dmn_set_parent(clk, tmp_parent);
- BUG_ON(ret1);
-
- ret2 = clk_set_rate(cur_parent, rate);
-
- ret1 = dmn_set_parent(clk, cur_parent);
-
- clk->rate = 0; /* set to zero will force recalculation */
-
- return ret2 ? ret2 : ret1;
-}
-
-static struct clk_ops cpu_ops = {
- .get_parent = dmn_get_parent,
- .set_parent = dmn_set_parent,
- .set_rate = cpu_set_rate,
-};
-
-static struct clk clk_cpu = {
- .parent = &clk_pll1,
- .regofs = SIRFSOC_CLKC_CPU_CFG,
- .ops = &cpu_ops,
-};
-
-
-static struct clk_ops msi_ops = {
- .set_rate = dmn_set_rate,
- .get_rate = dmn_get_rate,
- .set_parent = dmn_set_parent,
- .get_parent = dmn_get_parent,
-};
-
-static struct clk clk_mem = {
- .parent = &clk_pll2,
- .regofs = SIRFSOC_CLKC_MEM_CFG,
- .ops = &msi_ops,
-};
-
-static struct clk clk_sys = {
- .parent = &clk_pll3,
- .regofs = SIRFSOC_CLKC_SYS_CFG,
- .ops = &msi_ops,
-};
-
-static struct clk clk_io = {
- .parent = &clk_pll3,
- .regofs = SIRFSOC_CLKC_IO_CFG,
- .ops = &msi_ops,
-};
-
-/*
- * on-chip clock sets
- */
-static struct clk_lookup onchip_clks[] = {
- {
- .dev_id = "rtc",
- .clk = &clk_rtc,
- }, {
- .dev_id = "osc",
- .clk = &clk_osc,
- }, {
- .dev_id = "pll1",
- .clk = &clk_pll1,
- }, {
- .dev_id = "pll2",
- .clk = &clk_pll2,
- }, {
- .dev_id = "pll3",
- .clk = &clk_pll3,
- }, {
- .dev_id = "cpu",
- .clk = &clk_cpu,
- }, {
- .dev_id = "mem",
- .clk = &clk_mem,
- }, {
- .dev_id = "sys",
- .clk = &clk_sys,
- }, {
- .dev_id = "io",
- .clk = &clk_io,
- },
-};
-
-int clk_enable(struct clk *clk)
-{
- unsigned long flags;
-
- if (unlikely(IS_ERR_OR_NULL(clk)))
- return -EINVAL;
-
- if (clk->parent)
- clk_enable(clk->parent);
-
- spin_lock_irqsave(&clocks_lock, flags);
- if (!clk->usage++ && clk->ops && clk->ops->enable)
- clk->ops->enable(clk);
- spin_unlock_irqrestore(&clocks_lock, flags);
- return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *clk)
-{
- unsigned long flags;
-
- if (unlikely(IS_ERR_OR_NULL(clk)))
- return;
-
- WARN_ON(!clk->usage);
-
- spin_lock_irqsave(&clocks_lock, flags);
- if (--clk->usage == 0 && clk->ops && clk->ops->disable)
- clk->ops->disable(clk);
- spin_unlock_irqrestore(&clocks_lock, flags);
-
- if (clk->parent)
- clk_disable(clk->parent);
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
- if (unlikely(IS_ERR_OR_NULL(clk)))
- return 0;
-
- if (clk->rate)
- return clk->rate;
-
- if (clk->ops && clk->ops->get_rate)
- return clk->ops->get_rate(clk);
-
- return clk_get_rate(clk->parent);
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
- if (unlikely(IS_ERR_OR_NULL(clk)))
- return 0;
-
- if (clk->ops && clk->ops->round_rate)
- return clk->ops->round_rate(clk, rate);
-
- return 0;
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
- if (unlikely(IS_ERR_OR_NULL(clk)))
- return -EINVAL;
-
- if (!clk->ops || !clk->ops->set_rate)
- return -EINVAL;
-
- return clk->ops->set_rate(clk, rate);
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
- int ret;
- unsigned long flags;
-
- if (unlikely(IS_ERR_OR_NULL(clk)))
- return -EINVAL;
-
- if (!clk->ops || !clk->ops->set_parent)
- return -EINVAL;
-
- spin_lock_irqsave(&clocks_lock, flags);
- ret = clk->ops->set_parent(clk, parent);
- if (!ret) {
- parent->usage += clk->usage;
- clk->parent->usage -= clk->usage;
- BUG_ON(clk->parent->usage < 0);
- clk->parent = parent;
- }
- spin_unlock_irqrestore(&clocks_lock, flags);
- return ret;
-}
-EXPORT_SYMBOL(clk_set_parent);
-
-struct clk *clk_get_parent(struct clk *clk)
-{
- unsigned long flags;
-
- if (unlikely(IS_ERR_OR_NULL(clk)))
- return NULL;
-
- if (!clk->ops || !clk->ops->get_parent)
- return clk->parent;
-
- spin_lock_irqsave(&clocks_lock, flags);
- clk->parent = clk->ops->get_parent(clk);
- spin_unlock_irqrestore(&clocks_lock, flags);
- return clk->parent;
-}
-EXPORT_SYMBOL(clk_get_parent);
-
-static void __init sirfsoc_clk_init(void)
-{
- clkdev_add_table(onchip_clks, ARRAY_SIZE(onchip_clks));
-}
-
-static struct of_device_id clkc_ids[] = {
- { .compatible = "sirf,prima2-clkc" },
- {},
-};
-
-void __init sirfsoc_of_clk_init(void)
-{
- struct device_node *np;
- struct resource res;
- struct map_desc sirfsoc_clkc_iodesc = {
- .virtual = SIRFSOC_CLOCK_VA_BASE,
- .type = MT_DEVICE,
- };
-
- np = of_find_matching_node(NULL, clkc_ids);
- if (!np)
- panic("unable to find compatible clkc node in dtb\n");
-
- if (of_address_to_resource(np, 0, &res))
- panic("unable to find clkc range in dtb");
- of_node_put(np);
-
- sirfsoc_clkc_iodesc.pfn = __phys_to_pfn(res.start);
- sirfsoc_clkc_iodesc.length = 1 + res.end - res.start;
-
- iotable_init(&sirfsoc_clkc_iodesc, 1);
-
- sirfsoc_clk_init();
-}
diff --git a/arch/arm/mach-prima2/prima2.c b/arch/arm/mach-prima2/common.c
similarity index 80%
rename from arch/arm/mach-prima2/prima2.c
rename to arch/arm/mach-prima2/common.c
index 8f0429d..f25a541 100644
--- a/arch/arm/mach-prima2/prima2.c
+++ b/arch/arm/mach-prima2/common.c
@@ -30,21 +30,21 @@
sirfsoc_pm_init();
}
-static const char *prima2cb_dt_match[] __initdata = {
- "sirf,prima2-cb",
+#ifdef CONFIG_ARCH_PRIMA2
+static const char *prima2_dt_match[] __initdata = {
+ "sirf,prima2",
NULL
};
-MACHINE_START(PRIMA2_EVB, "prima2cb")
+DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)")
/* Maintainer: Barry Song <baohua.song@csr.com> */
- .atag_offset = 0x100,
- .init_early = sirfsoc_of_clk_init,
.map_io = sirfsoc_map_lluart,
.init_irq = sirfsoc_of_irq_init,
.timer = &sirfsoc_timer,
.dma_zone_size = SZ_256M,
.init_machine = sirfsoc_mach_init,
.init_late = sirfsoc_init_late,
- .dt_compat = prima2cb_dt_match,
+ .dt_compat = prima2_dt_match,
.restart = sirfsoc_restart,
MACHINE_END
+#endif
diff --git a/arch/arm/mach-prima2/irq.c b/arch/arm/mach-prima2/irq.c
index a7b9415..7dee917 100644
--- a/arch/arm/mach-prima2/irq.c
+++ b/arch/arm/mach-prima2/irq.c
@@ -63,7 +63,7 @@
np = of_find_matching_node(NULL, intc_ids);
if (!np)
- panic("unable to find compatible intc node in dtb\n");
+ return;
sirfsoc_intc_base = of_iomap(np, 0);
if (!sirfsoc_intc_base)
diff --git a/arch/arm/mach-prima2/timer.c b/arch/arm/mach-prima2/timer.c
index f224107..d95bf252 100644
--- a/arch/arm/mach-prima2/timer.c
+++ b/arch/arm/mach-prima2/timer.c
@@ -21,6 +21,8 @@
#include <asm/sched_clock.h>
#include <asm/mach/time.h>
+#include "common.h"
+
#define SIRFSOC_TIMER_COUNTER_LO 0x0000
#define SIRFSOC_TIMER_COUNTER_HI 0x0004
#define SIRFSOC_TIMER_MATCH_0 0x0008
@@ -188,9 +190,13 @@
static void __init sirfsoc_timer_init(void)
{
unsigned long rate;
+ struct clk *clk;
+
+ /* initialize clocking early, we want to set the OS timer */
+ sirfsoc_of_clk_init();
/* timer's input clock is io clock */
- struct clk *clk = clk_get_sys("io", NULL);
+ clk = clk_get_sys("io", NULL);
BUG_ON(IS_ERR(clk));
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index 166eee5..c1f3b12 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -6,7 +6,6 @@
#include <linux/spi/pxa2xx_spi.h>
#include <linux/i2c/pxa-i2c.h>
-#include <asm/pmu.h>
#include <mach/udc.h>
#include <mach/pxa3xx-u2d.h>
#include <mach/pxafb.h>
@@ -42,7 +41,7 @@
struct platform_device pxa_device_pmu = {
.name = "arm-pmu",
- .id = ARM_PMU_DEVICE_CPU,
+ .id = -1,
.resource = &pxa_resource_pmu,
.num_resources = 1,
};
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index baf382c..d7a6e9c 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -32,7 +32,6 @@
#include <asm/irq.h>
#include <asm/leds.h>
#include <asm/mach-types.h>
-#include <asm/pmu.h>
#include <asm/pgtable.h>
#include <asm/hardware/gic.h>
#include <asm/hardware/cache-l2x0.h>
@@ -297,7 +296,7 @@
static struct platform_device pmu_device = {
.name = "arm-pmu",
- .id = ARM_PMU_DEVICE_CPU,
+ .id = -1,
.num_resources = ARRAY_SIZE(pmu_resources),
.resource = pmu_resources,
};
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index b1d7caf..361f898 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -34,7 +34,6 @@
#include <asm/irq.h>
#include <asm/leds.h>
#include <asm/mach-types.h>
-#include <asm/pmu.h>
#include <asm/pgtable.h>
#include <asm/hardware/gic.h>
#include <asm/hardware/cache-l2x0.h>
@@ -280,7 +279,7 @@
static struct platform_device pmu_device = {
.name = "arm-pmu",
- .id = ARM_PMU_DEVICE_CPU,
+ .id = -1,
.num_resources = 1,
.resource = &pmu_resource,
};
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index a98c536..c56bc8d 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -32,7 +32,6 @@
#include <asm/irq.h>
#include <asm/leds.h>
#include <asm/mach-types.h>
-#include <asm/pmu.h>
#include <asm/pgtable.h>
#include <asm/hardware/gic.h>
#include <asm/hardware/cache-l2x0.h>
@@ -263,7 +262,7 @@
static struct platform_device pmu_device = {
.name = "arm-pmu",
- .id = ARM_PMU_DEVICE_CPU,
+ .id = -1,
.num_resources = ARRAY_SIZE(pmu_resources),
.resource = pmu_resources,
};
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index 5965017..0409375 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -31,7 +31,6 @@
#include <asm/irq.h>
#include <asm/leds.h>
#include <asm/mach-types.h>
-#include <asm/pmu.h>
#include <asm/pgtable.h>
#include <asm/hardware/gic.h>
@@ -241,7 +240,7 @@
static struct platform_device pmu_device = {
.name = "arm-pmu",
- .id = ARM_PMU_DEVICE_CPU,
+ .id = -1,
.num_resources = 1,
.resource = &pmu_resource,
};
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index 3f2f605..97885dc 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -30,7 +30,6 @@
#include <asm/irq.h>
#include <asm/leds.h>
#include <asm/mach-types.h>
-#include <asm/pmu.h>
#include <asm/smp_twd.h>
#include <asm/pgtable.h>
#include <asm/hardware/gic.h>
@@ -280,7 +279,7 @@
static struct platform_device pmu_device = {
.name = "arm-pmu",
- .id = ARM_PMU_DEVICE_CPU,
+ .id = -1,
.num_resources = ARRAY_SIZE(pmu_resources),
.resource = pmu_resources,
};
diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c
index 2704bcd..d35b94e 100644
--- a/arch/arm/mach-shark/core.c
+++ b/arch/arm/mach-shark/core.c
@@ -21,9 +21,6 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
-#define IO_BASE 0xe0000000
-#define IO_SIZE 0x08000000
-#define IO_START 0x40000000
#define ROMCARD_SIZE 0x08000000
#define ROMCARD_START 0x10000000
@@ -104,20 +101,6 @@
extern void shark_init_irq(void);
-static struct map_desc shark_io_desc[] __initdata = {
- {
- .virtual = IO_BASE,
- .pfn = __phys_to_pfn(IO_START),
- .length = IO_SIZE,
- .type = MT_DEVICE
- }
-};
-
-static void __init shark_map_io(void)
-{
- iotable_init(shark_io_desc, ARRAY_SIZE(shark_io_desc));
-}
-
#define IRQ_TIMER 0
#define HZ_TIME ((1193180 + HZ/2) / HZ)
@@ -158,7 +141,6 @@
MACHINE_START(SHARK, "Shark")
/* Maintainer: Alexander Schulz */
.atag_offset = 0x3000,
- .map_io = shark_map_io,
.init_early = shark_init_early,
.init_irq = shark_init_irq,
.timer = &shark_timer,
diff --git a/arch/arm/mach-shark/include/mach/debug-macro.S b/arch/arm/mach-shark/include/mach/debug-macro.S
index 20eb2bf..d129119 100644
--- a/arch/arm/mach-shark/include/mach/debug-macro.S
+++ b/arch/arm/mach-shark/include/mach/debug-macro.S
@@ -12,9 +12,10 @@
*/
.macro addruart, rp, rv, tmp
- mov \rp, #0xe0000000
- orr \rp, \rp, #0x000003f8
- mov \rv, \rp
+ mov \rp, #0x3f8
+ orr \rv, \rp, #0xfe000000
+ orr \rv, \rv, #0x00e00000
+ orr \rp, \rp, #0x40000000
.endm
.macro senduart,rd,rx
diff --git a/arch/arm/mach-shark/include/mach/entry-macro.S b/arch/arm/mach-shark/include/mach/entry-macro.S
index 5901b09..c9e49f0 100644
--- a/arch/arm/mach-shark/include/mach/entry-macro.S
+++ b/arch/arm/mach-shark/include/mach/entry-macro.S
@@ -8,7 +8,8 @@
* warranty of any kind, whether express or implied.
*/
.macro get_irqnr_preamble, base, tmp
- mov \base, #0xe0000000
+ mov \base, #0xfe000000
+ orr \base, \base, #0x00e00000
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
diff --git a/arch/arm/mach-shark/include/mach/io.h b/arch/arm/mach-shark/include/mach/io.h
deleted file mode 100644
index 1a45fc0..0000000
--- a/arch/arm/mach-shark/include/mach/io.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * arch/arm/mach-shark/include/mach/io.h
- *
- * by Alexander Schulz
- *
- * derived from:
- * arch/arm/mach-ebsa110/include/mach/io.h
- * Copyright (C) 1997,1998 Russell King
- */
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-#define __io(a) ((void __iomem *)(0xe0000000 + (a)))
-
-#endif
diff --git a/arch/arm/mach-shark/pci.c b/arch/arm/mach-shark/pci.c
index 9089407..b8b4ab3 100644
--- a/arch/arm/mach-shark/pci.c
+++ b/arch/arm/mach-shark/pci.c
@@ -8,12 +8,15 @@
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
+#include <linux/io.h>
#include <video/vga.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>
#include <asm/mach-types.h>
+#define IO_START 0x40000000
+
static int __init shark_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
if (dev->bus->number == 0)
@@ -44,6 +47,8 @@
pcibios_min_mem = 0x50000000;
vga_base = 0xe8000000;
+ pci_ioremap_io(0, IO_START);
+
pci_common_init(&shark_pci);
return 0;
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index d82c010..cfc3b5c 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -40,7 +40,6 @@
#include <linux/mmc/sh_mobile_sdhi.h>
#include <linux/mfd/tmio.h>
#include <linux/sh_clk.h>
-#include <linux/videodev2.h>
#include <video/sh_mobile_lcdc.h>
#include <video/sh_mipi_dsi.h>
#include <sound/sh_fsi.h>
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 9077aaa..b3226f8 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -34,7 +34,6 @@
select USB_ARCH_HAS_EHCI if USB_SUPPORT
select USB_ULPI if USB
select USB_ULPI_VIEWPORT if USB_SUPPORT
- select USE_OF
select ARM_ERRATA_743622
select ARM_ERRATA_751472
select ARM_ERRATA_754322
@@ -60,25 +59,6 @@
comment "Tegra board type"
-config MACH_HARMONY
- bool "Harmony board"
- depends on ARCH_TEGRA_2x_SOC
- help
- Support for nVidia Harmony development platform
-
-config MACH_PAZ00
- bool "Paz00 board"
- depends on ARCH_TEGRA_2x_SOC
- help
- Support for the Toshiba AC100/Dynabook AZ netbook
-
-config MACH_TRIMSLICE
- bool "TrimSlice board"
- depends on ARCH_TEGRA_2x_SOC
- select TEGRA_PCI
- help
- Support for CompuLab TrimSlice platform
-
choice
prompt "Default low-level debug console UART"
default TEGRA_DEBUG_UART_NONE
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index c3d7303..56065ac 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -26,13 +26,6 @@
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-dt-tegra20.o
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o
-obj-$(CONFIG_MACH_HARMONY) += board-harmony.o
-obj-$(CONFIG_MACH_HARMONY) += board-harmony-pinmux.o
-obj-$(CONFIG_MACH_HARMONY) += board-harmony-pcie.o
-obj-$(CONFIG_MACH_HARMONY) += board-harmony-power.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-harmony-pcie.o
-obj-$(CONFIG_MACH_PAZ00) += board-paz00.o
-obj-$(CONFIG_MACH_PAZ00) += board-paz00-pinmux.o
-
-obj-$(CONFIG_MACH_TRIMSLICE) += board-trimslice.o
-obj-$(CONFIG_MACH_TRIMSLICE) += board-trimslice-pinmux.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-paz00.o
diff --git a/arch/arm/mach-tegra/apbio.c b/arch/arm/mach-tegra/apbio.c
index dc0fe38..643a378 100644
--- a/arch/arm/mach-tegra/apbio.c
+++ b/arch/arm/mach-tegra/apbio.c
@@ -293,12 +293,12 @@
static u32 tegra_apb_readl_direct(unsigned long offset)
{
- return readl(IO_TO_VIRT(offset));
+ return readl(IO_ADDRESS(offset));
}
static void tegra_apb_writel_direct(u32 value, unsigned long offset)
{
- writel(value, IO_TO_VIRT(offset));
+ writel(value, IO_ADDRESS(offset));
}
void tegra_apb_io_init(void)
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index c099963..37007d6 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -42,7 +42,6 @@
#include <mach/irqs.h>
#include "board.h"
-#include "board-harmony.h"
#include "clock.h"
#include "devices.h"
@@ -95,54 +94,40 @@
tegra20_auxdata_lookup, NULL);
}
-#ifdef CONFIG_MACH_TRIMSLICE
static void __init trimslice_init(void)
{
+#ifdef CONFIG_TEGRA_PCI
int ret;
ret = tegra_pcie_init(true, true);
if (ret)
pr_err("tegra_pci_init() failed: %d\n", ret);
-}
#endif
+}
-#ifdef CONFIG_MACH_HARMONY
static void __init harmony_init(void)
{
+#ifdef CONFIG_TEGRA_PCI
int ret;
- ret = harmony_regulator_init();
- if (ret) {
- pr_err("harmony_regulator_init() failed: %d\n", ret);
- return;
- }
-
ret = harmony_pcie_init();
if (ret)
pr_err("harmony_pcie_init() failed: %d\n", ret);
-}
#endif
+}
-#ifdef CONFIG_MACH_PAZ00
static void __init paz00_init(void)
{
tegra_paz00_wifikill_init();
}
-#endif
static struct {
char *machine;
void (*init)(void);
} board_init_funcs[] = {
-#ifdef CONFIG_MACH_TRIMSLICE
{ "compulab,trimslice", trimslice_init },
-#endif
-#ifdef CONFIG_MACH_HARMONY
{ "nvidia,harmony", harmony_init },
-#endif
-#ifdef CONFIG_MACH_PAZ00
{ "compal,paz00", paz00_init },
-#endif
};
static void __init tegra_dt_init_late(void)
diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c
index e8c3fda..3cdc1bb 100644
--- a/arch/arm/mach-tegra/board-harmony-pcie.c
+++ b/arch/arm/mach-tegra/board-harmony-pcie.c
@@ -18,35 +18,57 @@
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <linux/err.h>
+#include <linux/of_gpio.h>
#include <linux/regulator/consumer.h>
#include <asm/mach-types.h>
#include "board.h"
-#include "board-harmony.h"
#ifdef CONFIG_TEGRA_PCI
int __init harmony_pcie_init(void)
{
+ struct device_node *np;
+ int en_vdd_1v05;
struct regulator *regulator = NULL;
int err;
- err = gpio_request(TEGRA_GPIO_EN_VDD_1V05_GPIO, "EN_VDD_1V05");
- if (err)
+ np = of_find_node_by_path("/regulators/regulator@3");
+ if (!np) {
+ pr_err("%s: of_find_node_by_path failed\n", __func__);
+ return -ENODEV;
+ }
+
+ en_vdd_1v05 = of_get_named_gpio(np, "gpio", 0);
+ if (en_vdd_1v05 < 0) {
+ pr_err("%s: of_get_named_gpio failed: %d\n", __func__,
+ en_vdd_1v05);
+ return en_vdd_1v05;
+ }
+
+ err = gpio_request(en_vdd_1v05, "EN_VDD_1V05");
+ if (err) {
+ pr_err("%s: gpio_request failed: %d\n", __func__, err);
return err;
+ }
- gpio_direction_output(TEGRA_GPIO_EN_VDD_1V05_GPIO, 1);
+ gpio_direction_output(en_vdd_1v05, 1);
- regulator = regulator_get(NULL, "pex_clk");
- if (IS_ERR_OR_NULL(regulator))
+ regulator = regulator_get(NULL, "vdd_ldo0,vddio_pex_clk");
+ if (IS_ERR_OR_NULL(regulator)) {
+ pr_err("%s: regulator_get failed: %d\n", __func__,
+ (int)PTR_ERR(regulator));
goto err_reg;
+ }
regulator_enable(regulator);
err = tegra_pcie_init(true, true);
- if (err)
+ if (err) {
+ pr_err("%s: tegra_pcie_init failed: %d\n", __func__, err);
goto err_pcie;
+ }
return 0;
@@ -54,20 +76,9 @@
regulator_disable(regulator);
regulator_put(regulator);
err_reg:
- gpio_free(TEGRA_GPIO_EN_VDD_1V05_GPIO);
+ gpio_free(en_vdd_1v05);
return err;
}
-static int __init harmony_pcie_initcall(void)
-{
- if (!machine_is_harmony())
- return 0;
-
- return harmony_pcie_init();
-}
-
-/* PCI should be initialized after I2C, mfd and regulators */
-subsys_initcall_sync(harmony_pcie_initcall);
-
#endif
diff --git a/arch/arm/mach-tegra/board-harmony-pinmux.c b/arch/arm/mach-tegra/board-harmony-pinmux.c
deleted file mode 100644
index 83d420f..0000000
--- a/arch/arm/mach-tegra/board-harmony-pinmux.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-harmony-pinmux.c
- *
- * Copyright (C) 2010 Google, Inc.
- * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-
-#include "board-harmony.h"
-#include "board-pinmux.h"
-
-static struct pinctrl_map harmony_map[] = {
- TEGRA_MAP_MUXCONF("ata", "ide", none, driven),
- TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven),
- TEGRA_MAP_MUXCONF("atc", "nand", none, driven),
- TEGRA_MAP_MUXCONF("atd", "gmi", none, driven),
- TEGRA_MAP_MUXCONF("ate", "gmi", none, driven),
- TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven),
- TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", down, tristate),
- TEGRA_MAP_MUXCONF("crtp", "crt", none, tristate),
- TEGRA_MAP_MUXCONF("csus", "vi_sensor_clk", down, tristate),
- TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven),
- TEGRA_MAP_MUXCONF("dap2", "dap2", none, tristate),
- TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate),
- TEGRA_MAP_MUXCONF("dap4", "dap4", none, tristate),
- TEGRA_MAP_MUXCONF("ddc", "i2c2", up, driven),
- TEGRA_MAP_MUXCONF("dta", "sdio2", up, driven),
- TEGRA_MAP_MUXCONF("dtb", "rsvd1", none, driven),
- TEGRA_MAP_MUXCONF("dtc", "rsvd1", none, tristate),
- TEGRA_MAP_MUXCONF("dtd", "sdio2", up, driven),
- TEGRA_MAP_MUXCONF("dte", "rsvd1", none, tristate),
- TEGRA_MAP_MUXCONF("dtf", "i2c3", none, tristate),
- TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven),
- TEGRA_MAP_MUXCONF("gmb", "gmi", none, driven),
- TEGRA_MAP_MUXCONF("gmc", "uartd", none, driven),
- TEGRA_MAP_MUXCONF("gmd", "gmi", none, driven),
- TEGRA_MAP_MUXCONF("gme", "sdio4", none, driven),
- TEGRA_MAP_MUXCONF("gpu", "gmi", none, tristate),
- TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven),
- TEGRA_MAP_MUXCONF("gpv", "pcie", none, driven),
- TEGRA_MAP_MUXCONF("hdint", "hdmi", na, tristate),
- TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, driven),
- TEGRA_MAP_MUXCONF("irrx", "uarta", up, tristate),
- TEGRA_MAP_MUXCONF("irtx", "uarta", up, tristate),
- TEGRA_MAP_MUXCONF("kbca", "kbc", up, driven),
- TEGRA_MAP_MUXCONF("kbcb", "kbc", up, driven),
- TEGRA_MAP_MUXCONF("kbcc", "kbc", up, driven),
- TEGRA_MAP_MUXCONF("kbcd", "kbc", up, driven),
- TEGRA_MAP_MUXCONF("kbce", "kbc", up, driven),
- TEGRA_MAP_MUXCONF("kbcf", "kbc", up, driven),
- TEGRA_MAP_MUXCONF("lcsn", "displaya", na, tristate),
- TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ldc", "displaya", na, tristate),
- TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("lhp0", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("lhp1", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("lhp2", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("lm0", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("lm1", "displaya", na, tristate),
- TEGRA_MAP_MUXCONF("lpp", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("lpw0", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("lpw1", "displaya", na, tristate),
- TEGRA_MAP_MUXCONF("lpw2", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("lsc1", "displaya", na, tristate),
- TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate),
- TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate),
- TEGRA_MAP_MUXCONF("lsdi", "displaya", na, tristate),
- TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("lvp0", "displaya", na, tristate),
- TEGRA_MAP_MUXCONF("lvp1", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("owc", "rsvd2", na, tristate),
- TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, driven),
- TEGRA_MAP_MUXCONF("pta", "hdmi", none, driven),
- TEGRA_MAP_MUXCONF("rm", "i2c1", none, driven),
- TEGRA_MAP_MUXCONF("sdb", "pwm", na, tristate),
- TEGRA_MAP_MUXCONF("sdc", "pwm", up, driven),
- TEGRA_MAP_MUXCONF("sdd", "pwm", up, tristate),
- TEGRA_MAP_MUXCONF("sdio1", "sdio1", none, tristate),
- TEGRA_MAP_MUXCONF("slxa", "pcie", none, driven),
- TEGRA_MAP_MUXCONF("slxc", "spdif", none, tristate),
- TEGRA_MAP_MUXCONF("slxd", "spdif", none, tristate),
- TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven),
- TEGRA_MAP_MUXCONF("spdi", "rsvd2", none, tristate),
- TEGRA_MAP_MUXCONF("spdo", "rsvd2", none, tristate),
- TEGRA_MAP_MUXCONF("spia", "gmi", none, driven),
- TEGRA_MAP_MUXCONF("spib", "gmi", none, driven),
- TEGRA_MAP_MUXCONF("spic", "gmi", up, tristate),
- TEGRA_MAP_MUXCONF("spid", "spi1", down, tristate),
- TEGRA_MAP_MUXCONF("spie", "spi1", up, tristate),
- TEGRA_MAP_MUXCONF("spif", "spi1", down, tristate),
- TEGRA_MAP_MUXCONF("spig", "spi2_alt", none, tristate),
- TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate),
- TEGRA_MAP_MUXCONF("uaa", "ulpi", up, tristate),
- TEGRA_MAP_MUXCONF("uab", "ulpi", up, tristate),
- TEGRA_MAP_MUXCONF("uac", "rsvd2", none, tristate),
- TEGRA_MAP_MUXCONF("uad", "irda", up, tristate),
- TEGRA_MAP_MUXCONF("uca", "uartc", up, tristate),
- TEGRA_MAP_MUXCONF("ucb", "uartc", up, tristate),
- TEGRA_MAP_MUXCONF("uda", "ulpi", none, tristate),
- TEGRA_MAP_CONF("ck32", none, na),
- TEGRA_MAP_CONF("ddrc", none, na),
- TEGRA_MAP_CONF("pmca", none, na),
- TEGRA_MAP_CONF("pmcb", none, na),
- TEGRA_MAP_CONF("pmcc", none, na),
- TEGRA_MAP_CONF("pmcd", none, na),
- TEGRA_MAP_CONF("pmce", none, na),
- TEGRA_MAP_CONF("xm2c", none, na),
- TEGRA_MAP_CONF("xm2d", none, na),
- TEGRA_MAP_CONF("ls", up, na),
- TEGRA_MAP_CONF("lc", up, na),
- TEGRA_MAP_CONF("ld17_0", down, na),
- TEGRA_MAP_CONF("ld19_18", down, na),
- TEGRA_MAP_CONF("ld21_20", down, na),
- TEGRA_MAP_CONF("ld23_22", down, na),
-};
-
-static struct tegra_board_pinmux_conf conf = {
- .maps = harmony_map,
- .map_count = ARRAY_SIZE(harmony_map),
-};
-
-void harmony_pinmux_init(void)
-{
- tegra_board_pinmux_init(&conf, NULL);
-}
diff --git a/arch/arm/mach-tegra/board-harmony-power.c b/arch/arm/mach-tegra/board-harmony-power.c
deleted file mode 100644
index b7344be..0000000
--- a/arch/arm/mach-tegra/board-harmony-power.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * Copyright (C) 2010 NVIDIA, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
- * 02111-1307, USA
- */
-#include <linux/i2c.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/regulator/machine.h>
-#include <linux/regulator/fixed.h>
-#include <linux/mfd/tps6586x.h>
-#include <linux/of.h>
-#include <linux/of_i2c.h>
-
-#include <asm/mach-types.h>
-
-#include <mach/irqs.h>
-
-#include "board-harmony.h"
-
-static struct regulator_consumer_supply tps658621_ldo0_supply[] = {
- REGULATOR_SUPPLY("pex_clk", NULL),
-};
-
-static struct regulator_init_data ldo0_data = {
- .supply_regulator = "vdd_sm2",
- .constraints = {
- .name = "vdd_ldo0",
- .min_uV = 3300 * 1000,
- .max_uV = 3300 * 1000,
- .valid_modes_mask = (REGULATOR_MODE_NORMAL |
- REGULATOR_MODE_STANDBY),
- .valid_ops_mask = (REGULATOR_CHANGE_MODE |
- REGULATOR_CHANGE_STATUS |
- REGULATOR_CHANGE_VOLTAGE),
- .apply_uV = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(tps658621_ldo0_supply),
- .consumer_supplies = tps658621_ldo0_supply,
-};
-
-#define HARMONY_REGULATOR_INIT(_id, _name, _supply, _minmv, _maxmv, _on)\
- static struct regulator_init_data _id##_data = { \
- .supply_regulator = _supply, \
- .constraints = { \
- .name = _name, \
- .min_uV = (_minmv)*1000, \
- .max_uV = (_maxmv)*1000, \
- .valid_modes_mask = (REGULATOR_MODE_NORMAL | \
- REGULATOR_MODE_STANDBY), \
- .valid_ops_mask = (REGULATOR_CHANGE_MODE | \
- REGULATOR_CHANGE_STATUS | \
- REGULATOR_CHANGE_VOLTAGE), \
- .always_on = _on, \
- }, \
- }
-
-HARMONY_REGULATOR_INIT(sm0, "vdd_sm0", "vdd_sys", 725, 1500, 1);
-HARMONY_REGULATOR_INIT(sm1, "vdd_sm1", "vdd_sys", 725, 1500, 1);
-HARMONY_REGULATOR_INIT(sm2, "vdd_sm2", "vdd_sys", 3000, 4550, 1);
-HARMONY_REGULATOR_INIT(ldo1, "vdd_ldo1", "vdd_sm2", 725, 1500, 1);
-HARMONY_REGULATOR_INIT(ldo2, "vdd_ldo2", "vdd_sm2", 725, 1500, 0);
-HARMONY_REGULATOR_INIT(ldo3, "vdd_ldo3", "vdd_sm2", 1250, 3300, 1);
-HARMONY_REGULATOR_INIT(ldo4, "vdd_ldo4", "vdd_sm2", 1700, 2475, 1);
-HARMONY_REGULATOR_INIT(ldo5, "vdd_ldo5", NULL, 1250, 3300, 1);
-HARMONY_REGULATOR_INIT(ldo6, "vdd_ldo6", "vdd_sm2", 1250, 3300, 0);
-HARMONY_REGULATOR_INIT(ldo7, "vdd_ldo7", "vdd_sm2", 1250, 3300, 0);
-HARMONY_REGULATOR_INIT(ldo8, "vdd_ldo8", "vdd_sm2", 1250, 3300, 0);
-HARMONY_REGULATOR_INIT(ldo9, "vdd_ldo9", "vdd_sm2", 1250, 3300, 1);
-
-#define TPS_REG(_id, _data) \
- { \
- .id = TPS6586X_ID_##_id, \
- .name = "tps6586x-regulator", \
- .platform_data = _data, \
- }
-
-static struct tps6586x_subdev_info tps_devs[] = {
- TPS_REG(SM_0, &sm0_data),
- TPS_REG(SM_1, &sm1_data),
- TPS_REG(SM_2, &sm2_data),
- TPS_REG(LDO_0, &ldo0_data),
- TPS_REG(LDO_1, &ldo1_data),
- TPS_REG(LDO_2, &ldo2_data),
- TPS_REG(LDO_3, &ldo3_data),
- TPS_REG(LDO_4, &ldo4_data),
- TPS_REG(LDO_5, &ldo5_data),
- TPS_REG(LDO_6, &ldo6_data),
- TPS_REG(LDO_7, &ldo7_data),
- TPS_REG(LDO_8, &ldo8_data),
- TPS_REG(LDO_9, &ldo9_data),
-};
-
-static struct tps6586x_platform_data tps_platform = {
- .irq_base = TEGRA_NR_IRQS,
- .num_subdevs = ARRAY_SIZE(tps_devs),
- .subdevs = tps_devs,
- .gpio_base = HARMONY_GPIO_TPS6586X(0),
-};
-
-static struct i2c_board_info __initdata harmony_regulators[] = {
- {
- I2C_BOARD_INFO("tps6586x", 0x34),
- .irq = INT_EXTERNAL_PMU,
- .platform_data = &tps_platform,
- },
-};
-
-int __init harmony_regulator_init(void)
-{
- regulator_register_always_on(0, "vdd_sys",
- NULL, 0, 5000000);
-
- if (machine_is_harmony()) {
- i2c_register_board_info(3, harmony_regulators, 1);
- } else { /* Harmony, booted using device tree */
- struct device_node *np;
- struct i2c_adapter *adapter;
-
- np = of_find_node_by_path("/i2c@7000d000");
- if (np == NULL) {
- pr_err("Could not find device_node for DVC I2C\n");
- return -ENODEV;
- }
-
- adapter = of_find_i2c_adapter_by_node(np);
- if (!adapter) {
- pr_err("Could not find i2c_adapter for DVC I2C\n");
- return -ENODEV;
- }
-
- i2c_new_device(adapter, harmony_regulators);
- }
-
- return 0;
-}
diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c
deleted file mode 100644
index e65e837f..0000000
--- a/arch/arm/mach-tegra/board-harmony.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-harmony.c
- *
- * Copyright (C) 2010 Google, Inc.
- * Copyright (C) 2011 NVIDIA, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/serial_8250.h>
-#include <linux/of_serial.h>
-#include <linux/clk.h>
-#include <linux/dma-mapping.h>
-#include <linux/pda_power.h>
-#include <linux/io.h>
-#include <linux/gpio.h>
-#include <linux/i2c.h>
-
-#include <sound/wm8903.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/hardware/gic.h>
-#include <asm/setup.h>
-
-#include <mach/tegra_wm8903_pdata.h>
-#include <mach/iomap.h>
-#include <mach/irqs.h>
-#include <mach/sdhci.h>
-
-#include "board.h"
-#include "board-harmony.h"
-#include "clock.h"
-#include "devices.h"
-#include "gpio-names.h"
-
-static struct plat_serial8250_port debug_uart_platform_data[] = {
- {
- .membase = IO_ADDRESS(TEGRA_UARTD_BASE),
- .mapbase = TEGRA_UARTD_BASE,
- .irq = INT_UARTD,
- .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
- .type = PORT_TEGRA,
- .handle_break = tegra_serial_handle_break,
- .iotype = UPIO_MEM,
- .regshift = 2,
- .uartclk = 216000000,
- }, {
- .flags = 0
- }
-};
-
-static struct platform_device debug_uart = {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM,
- .dev = {
- .platform_data = debug_uart_platform_data,
- },
-};
-
-static struct tegra_wm8903_platform_data harmony_audio_pdata = {
- .gpio_spkr_en = TEGRA_GPIO_SPKR_EN,
- .gpio_hp_det = TEGRA_GPIO_HP_DET,
- .gpio_hp_mute = -1,
- .gpio_int_mic_en = TEGRA_GPIO_INT_MIC_EN,
- .gpio_ext_mic_en = TEGRA_GPIO_EXT_MIC_EN,
-};
-
-static struct platform_device harmony_audio_device = {
- .name = "tegra-snd-wm8903",
- .id = 0,
- .dev = {
- .platform_data = &harmony_audio_pdata,
- },
-};
-
-static struct wm8903_platform_data harmony_wm8903_pdata = {
- .irq_active_low = 0,
- .micdet_cfg = 0,
- .micdet_delay = 100,
- .gpio_base = HARMONY_GPIO_WM8903(0),
- .gpio_cfg = {
- 0,
- 0,
- WM8903_GPIO_CONFIG_ZERO,
- 0,
- 0,
- },
-};
-
-static struct i2c_board_info __initdata wm8903_board_info = {
- I2C_BOARD_INFO("wm8903", 0x1a),
- .platform_data = &harmony_wm8903_pdata,
-};
-
-static void __init harmony_i2c_init(void)
-{
- platform_device_register(&tegra_i2c_device1);
- platform_device_register(&tegra_i2c_device2);
- platform_device_register(&tegra_i2c_device3);
- platform_device_register(&tegra_i2c_device4);
-
- wm8903_board_info.irq = gpio_to_irq(TEGRA_GPIO_CDC_IRQ);
- i2c_register_board_info(0, &wm8903_board_info, 1);
-}
-
-static struct platform_device *harmony_devices[] __initdata = {
- &debug_uart,
- &tegra_sdhci_device1,
- &tegra_sdhci_device2,
- &tegra_sdhci_device4,
- &tegra_ehci3_device,
- &tegra_i2s_device1,
- &tegra_das_device,
- &harmony_audio_device,
-};
-
-static void __init tegra_harmony_fixup(struct tag *tags, char **cmdline,
- struct meminfo *mi)
-{
- mi->nr_banks = 2;
- mi->bank[0].start = PHYS_OFFSET;
- mi->bank[0].size = 448 * SZ_1M;
- mi->bank[1].start = SZ_512M;
- mi->bank[1].size = SZ_512M;
-}
-
-static __initdata struct tegra_clk_init_table harmony_clk_init_table[] = {
- /* name parent rate enabled */
- { "uartd", "pll_p", 216000000, true },
- { "pll_a", "pll_p_out1", 56448000, true },
- { "pll_a_out0", "pll_a", 11289600, true },
- { "cdev1", NULL, 0, true },
- { "i2s1", "pll_a_out0", 11289600, false},
- { "usb3", "clk_m", 12000000, true },
- { NULL, NULL, 0, 0},
-};
-
-
-static struct tegra_sdhci_platform_data sdhci_pdata1 = {
- .cd_gpio = -1,
- .wp_gpio = -1,
- .power_gpio = -1,
-};
-
-static struct tegra_sdhci_platform_data sdhci_pdata2 = {
- .cd_gpio = TEGRA_GPIO_SD2_CD,
- .wp_gpio = TEGRA_GPIO_SD2_WP,
- .power_gpio = TEGRA_GPIO_SD2_POWER,
-};
-
-static struct tegra_sdhci_platform_data sdhci_pdata4 = {
- .cd_gpio = TEGRA_GPIO_SD4_CD,
- .wp_gpio = TEGRA_GPIO_SD4_WP,
- .power_gpio = TEGRA_GPIO_SD4_POWER,
- .is_8bit = 1,
-};
-
-static void __init tegra_harmony_init(void)
-{
- tegra_clk_init_from_table(harmony_clk_init_table);
-
- harmony_pinmux_init();
-
- tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1;
- tegra_sdhci_device2.dev.platform_data = &sdhci_pdata2;
- tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4;
-
- platform_add_devices(harmony_devices, ARRAY_SIZE(harmony_devices));
- harmony_i2c_init();
- harmony_regulator_init();
-}
-
-MACHINE_START(HARMONY, "harmony")
- .atag_offset = 0x100,
- .fixup = tegra_harmony_fixup,
- .map_io = tegra_map_common_io,
- .init_early = tegra20_init_early,
- .init_irq = tegra_init_irq,
- .handle_irq = gic_handle_irq,
- .timer = &tegra_timer,
- .init_machine = tegra_harmony_init,
- .init_late = tegra_init_late,
- .restart = tegra_assert_system_reset,
-MACHINE_END
diff --git a/arch/arm/mach-tegra/board-harmony.h b/arch/arm/mach-tegra/board-harmony.h
deleted file mode 100644
index 139d96c9..0000000
--- a/arch/arm/mach-tegra/board-harmony.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-harmony.h
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _MACH_TEGRA_BOARD_HARMONY_H
-#define _MACH_TEGRA_BOARD_HARMONY_H
-
-#include <mach/gpio-tegra.h>
-
-#define HARMONY_GPIO_TPS6586X(_x_) (TEGRA_NR_GPIOS + (_x_))
-#define HARMONY_GPIO_WM8903(_x_) (HARMONY_GPIO_TPS6586X(4) + (_x_))
-
-#define TEGRA_GPIO_SD2_CD TEGRA_GPIO_PI5
-#define TEGRA_GPIO_SD2_WP TEGRA_GPIO_PH1
-#define TEGRA_GPIO_SD2_POWER TEGRA_GPIO_PT3
-#define TEGRA_GPIO_SD4_CD TEGRA_GPIO_PH2
-#define TEGRA_GPIO_SD4_WP TEGRA_GPIO_PH3
-#define TEGRA_GPIO_SD4_POWER TEGRA_GPIO_PI6
-#define TEGRA_GPIO_CDC_IRQ TEGRA_GPIO_PX3
-#define TEGRA_GPIO_SPKR_EN HARMONY_GPIO_WM8903(2)
-#define TEGRA_GPIO_HP_DET TEGRA_GPIO_PW2
-#define TEGRA_GPIO_INT_MIC_EN TEGRA_GPIO_PX0
-#define TEGRA_GPIO_EXT_MIC_EN TEGRA_GPIO_PX1
-#define TEGRA_GPIO_EN_VDD_1V05_GPIO HARMONY_GPIO_TPS6586X(2)
-
-void harmony_pinmux_init(void);
-int harmony_regulator_init(void);
-
-#endif
diff --git a/arch/arm/mach-tegra/board-paz00-pinmux.c b/arch/arm/mach-tegra/board-paz00-pinmux.c
deleted file mode 100644
index 6f1111b..0000000
--- a/arch/arm/mach-tegra/board-paz00-pinmux.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-paz00-pinmux.c
- *
- * Copyright (C) 2010 Marc Dietrich <marvin24@gmx.de>
- * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-
-#include "board-paz00.h"
-#include "board-pinmux.h"
-
-static struct pinctrl_map paz00_map[] = {
- TEGRA_MAP_MUXCONF("ata", "gmi", none, driven),
- TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven),
- TEGRA_MAP_MUXCONF("atc", "gmi", none, driven),
- TEGRA_MAP_MUXCONF("atd", "gmi", none, driven),
- TEGRA_MAP_MUXCONF("ate", "gmi", none, driven),
- TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven),
- TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", down, driven),
- TEGRA_MAP_MUXCONF("crtp", "crt", none, tristate),
- TEGRA_MAP_MUXCONF("csus", "pllc_out1", down, tristate),
- TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven),
- TEGRA_MAP_MUXCONF("dap2", "gmi", none, driven),
- TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate),
- TEGRA_MAP_MUXCONF("dap4", "dap4", none, tristate),
- TEGRA_MAP_MUXCONF("ddc", "i2c2", up, driven),
- TEGRA_MAP_MUXCONF("dta", "rsvd1", up, tristate),
- TEGRA_MAP_MUXCONF("dtb", "rsvd1", none, tristate),
- TEGRA_MAP_MUXCONF("dtc", "rsvd1", none, tristate),
- TEGRA_MAP_MUXCONF("dtd", "rsvd1", up, tristate),
- TEGRA_MAP_MUXCONF("dte", "rsvd1", none, tristate),
- TEGRA_MAP_MUXCONF("dtf", "i2c3", none, driven),
- TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven),
- TEGRA_MAP_MUXCONF("gmb", "gmi", none, driven),
- TEGRA_MAP_MUXCONF("gmc", "gmi", none, driven),
- TEGRA_MAP_MUXCONF("gmd", "gmi", none, driven),
- TEGRA_MAP_MUXCONF("gme", "sdio4", none, driven),
- TEGRA_MAP_MUXCONF("gpu", "pwm", none, driven),
- TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven),
- TEGRA_MAP_MUXCONF("gpv", "pcie", none, driven),
- TEGRA_MAP_MUXCONF("hdint", "hdmi", na, driven),
- TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, driven),
- TEGRA_MAP_MUXCONF("irrx", "uarta", up, driven),
- TEGRA_MAP_MUXCONF("irtx", "uarta", up, driven),
- TEGRA_MAP_MUXCONF("kbca", "kbc", up, driven),
- TEGRA_MAP_MUXCONF("kbcb", "sdio2", up, driven),
- TEGRA_MAP_MUXCONF("kbcc", "kbc", up, driven),
- TEGRA_MAP_MUXCONF("kbcd", "sdio2", up, driven),
- TEGRA_MAP_MUXCONF("kbce", "kbc", up, driven),
- TEGRA_MAP_MUXCONF("kbcf", "kbc", up, driven),
- TEGRA_MAP_MUXCONF("lcsn", "displaya", na, tristate),
- TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ldc", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("lhp0", "displaya", na, tristate),
- TEGRA_MAP_MUXCONF("lhp1", "displaya", na, tristate),
- TEGRA_MAP_MUXCONF("lhp2", "displaya", na, tristate),
- TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("lm0", "displaya", na, tristate),
- TEGRA_MAP_MUXCONF("lm1", "displaya", na, tristate),
- TEGRA_MAP_MUXCONF("lpp", "displaya", na, tristate),
- TEGRA_MAP_MUXCONF("lpw0", "displaya", na, tristate),
- TEGRA_MAP_MUXCONF("lpw1", "displaya", na, tristate),
- TEGRA_MAP_MUXCONF("lpw2", "displaya", na, tristate),
- TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("lsc1", "displaya", na, tristate),
- TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate),
- TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate),
- TEGRA_MAP_MUXCONF("lsdi", "displaya", na, tristate),
- TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("lvp0", "displaya", na, tristate),
- TEGRA_MAP_MUXCONF("lvp1", "displaya", na, tristate),
- TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("owc", "owr", up, tristate),
- TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, driven),
- TEGRA_MAP_MUXCONF("pta", "hdmi", none, driven),
- TEGRA_MAP_MUXCONF("rm", "i2c1", none, driven),
- TEGRA_MAP_MUXCONF("sdb", "pwm", na, tristate),
- TEGRA_MAP_MUXCONF("sdc", "twc", up, tristate),
- TEGRA_MAP_MUXCONF("sdd", "pwm", up, tristate),
- TEGRA_MAP_MUXCONF("sdio1", "sdio1", none, driven),
- TEGRA_MAP_MUXCONF("slxa", "pcie", none, tristate),
- TEGRA_MAP_MUXCONF("slxc", "spi4", none, tristate),
- TEGRA_MAP_MUXCONF("slxd", "spi4", none, tristate),
- TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven),
- TEGRA_MAP_MUXCONF("spdi", "rsvd2", none, tristate),
- TEGRA_MAP_MUXCONF("spdo", "rsvd2", none, driven),
- TEGRA_MAP_MUXCONF("spia", "gmi", down, tristate),
- TEGRA_MAP_MUXCONF("spib", "gmi", down, tristate),
- TEGRA_MAP_MUXCONF("spic", "gmi", up, driven),
- TEGRA_MAP_MUXCONF("spid", "gmi", down, tristate),
- TEGRA_MAP_MUXCONF("spie", "gmi", up, tristate),
- TEGRA_MAP_MUXCONF("spif", "rsvd4", down, tristate),
- TEGRA_MAP_MUXCONF("spig", "spi2_alt", up, driven),
- TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate),
- TEGRA_MAP_MUXCONF("uaa", "ulpi", up, driven),
- TEGRA_MAP_MUXCONF("uab", "ulpi", up, driven),
- TEGRA_MAP_MUXCONF("uac", "rsvd4", none, driven),
- TEGRA_MAP_MUXCONF("uad", "spdif", up, tristate),
- TEGRA_MAP_MUXCONF("uca", "uartc", up, tristate),
- TEGRA_MAP_MUXCONF("ucb", "uartc", up, tristate),
- TEGRA_MAP_MUXCONF("uda", "ulpi", none, driven),
- TEGRA_MAP_CONF("ck32", none, na),
- TEGRA_MAP_CONF("ddrc", none, na),
- TEGRA_MAP_CONF("pmca", none, na),
- TEGRA_MAP_CONF("pmcb", none, na),
- TEGRA_MAP_CONF("pmcc", none, na),
- TEGRA_MAP_CONF("pmcd", none, na),
- TEGRA_MAP_CONF("pmce", none, na),
- TEGRA_MAP_CONF("xm2c", none, na),
- TEGRA_MAP_CONF("xm2d", none, na),
- TEGRA_MAP_CONF("ls", up, na),
- TEGRA_MAP_CONF("lc", up, na),
- TEGRA_MAP_CONF("ld17_0", down, na),
- TEGRA_MAP_CONF("ld19_18", down, na),
- TEGRA_MAP_CONF("ld21_20", down, na),
- TEGRA_MAP_CONF("ld23_22", down, na),
-};
-
-static struct tegra_board_pinmux_conf conf = {
- .maps = paz00_map,
- .map_count = ARRAY_SIZE(paz00_map),
-};
-
-void paz00_pinmux_init(void)
-{
- tegra_board_pinmux_init(&conf, NULL);
-}
diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
index 4b64af5..5930551 100644
--- a/arch/arm/mach-tegra/board-paz00.c
+++ b/arch/arm/mach-tegra/board-paz00.c
@@ -17,72 +17,10 @@
*
*/
-#include <linux/kernel.h>
-#include <linux/init.h>
#include <linux/platform_device.h>
-#include <linux/serial_8250.h>
-#include <linux/of_serial.h>
-#include <linux/clk.h>
-#include <linux/dma-mapping.h>
-#include <linux/gpio_keys.h>
-#include <linux/pda_power.h>
-#include <linux/io.h>
-#include <linux/input.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
#include <linux/rfkill-gpio.h>
-#include <asm/hardware/gic.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/setup.h>
-
-#include <mach/iomap.h>
-#include <mach/irqs.h>
-#include <mach/sdhci.h>
-
-#include "board.h"
#include "board-paz00.h"
-#include "clock.h"
-#include "devices.h"
-#include "gpio-names.h"
-
-static struct plat_serial8250_port debug_uart_platform_data[] = {
- {
- /* serial port on JP1 */
- .membase = IO_ADDRESS(TEGRA_UARTA_BASE),
- .mapbase = TEGRA_UARTA_BASE,
- .irq = INT_UARTA,
- .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
- .type = PORT_TEGRA,
- .handle_break = tegra_serial_handle_break,
- .iotype = UPIO_MEM,
- .regshift = 2,
- .uartclk = 216000000,
- }, {
- /* serial port on mini-pcie */
- .membase = IO_ADDRESS(TEGRA_UARTC_BASE),
- .mapbase = TEGRA_UARTC_BASE,
- .irq = INT_UARTC,
- .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
- .type = PORT_TEGRA,
- .handle_break = tegra_serial_handle_break,
- .iotype = UPIO_MEM,
- .regshift = 2,
- .uartclk = 216000000,
- }, {
- .flags = 0
- }
-};
-
-static struct platform_device debug_uart = {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM,
- .dev = {
- .platform_data = debug_uart_platform_data,
- },
-};
static struct rfkill_gpio_platform_data wifi_rfkill_platform_data = {
.name = "wifi_rfkill",
@@ -99,137 +37,7 @@
},
};
-static struct gpio_led gpio_leds[] = {
- {
- .name = "wifi-led",
- .default_trigger = "rfkill0",
- .gpio = TEGRA_WIFI_LED,
- },
-};
-
-static struct gpio_led_platform_data gpio_led_info = {
- .leds = gpio_leds,
- .num_leds = ARRAY_SIZE(gpio_leds),
-};
-
-static struct platform_device leds_gpio = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &gpio_led_info,
- },
-};
-
-static struct gpio_keys_button paz00_gpio_keys_buttons[] = {
- {
- .code = KEY_POWER,
- .gpio = TEGRA_GPIO_POWERKEY,
- .active_low = 1,
- .desc = "Power",
- .type = EV_KEY,
- .wakeup = 1,
- },
-};
-
-static struct gpio_keys_platform_data paz00_gpio_keys = {
- .buttons = paz00_gpio_keys_buttons,
- .nbuttons = ARRAY_SIZE(paz00_gpio_keys_buttons),
-};
-
-static struct platform_device gpio_keys_device = {
- .name = "gpio-keys",
- .id = -1,
- .dev = {
- .platform_data = &paz00_gpio_keys,
- },
-};
-
-static struct platform_device *paz00_devices[] __initdata = {
- &debug_uart,
- &tegra_sdhci_device4,
- &tegra_sdhci_device1,
- &leds_gpio,
- &gpio_keys_device,
-};
-
-static void paz00_i2c_init(void)
-{
- platform_device_register(&tegra_i2c_device1);
- platform_device_register(&tegra_i2c_device2);
- platform_device_register(&tegra_i2c_device4);
-}
-
-static void paz00_usb_init(void)
-{
- tegra_ehci2_ulpi_phy_config.reset_gpio = TEGRA_ULPI_RST;
-
- platform_device_register(&tegra_ehci2_device);
- platform_device_register(&tegra_ehci3_device);
-}
-
-static void __init tegra_paz00_fixup(struct tag *tags, char **cmdline,
- struct meminfo *mi)
-{
- mi->nr_banks = 1;
- mi->bank[0].start = PHYS_OFFSET;
- mi->bank[0].size = 448 * SZ_1M;
-}
-
-static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = {
- /* name parent rate enabled */
- { "uarta", "pll_p", 216000000, true },
- { "uartc", "pll_p", 216000000, true },
-
- { "usbd", "clk_m", 12000000, false },
- { "usb2", "clk_m", 12000000, false },
- { "usb3", "clk_m", 12000000, false },
-
- { NULL, NULL, 0, 0},
-};
-
-static struct tegra_sdhci_platform_data sdhci_pdata1 = {
- .cd_gpio = TEGRA_GPIO_SD1_CD,
- .wp_gpio = TEGRA_GPIO_SD1_WP,
- .power_gpio = TEGRA_GPIO_SD1_POWER,
-};
-
-static struct tegra_sdhci_platform_data sdhci_pdata4 = {
- .cd_gpio = -1,
- .wp_gpio = -1,
- .power_gpio = -1,
- .is_8bit = 1,
-};
-
void __init tegra_paz00_wifikill_init(void)
{
platform_device_register(&wifi_rfkill_device);
}
-
-static void __init tegra_paz00_init(void)
-{
- tegra_clk_init_from_table(paz00_clk_init_table);
-
- paz00_pinmux_init();
-
- tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1;
- tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4;
-
- platform_add_devices(paz00_devices, ARRAY_SIZE(paz00_devices));
- tegra_paz00_wifikill_init();
-
- paz00_i2c_init();
- paz00_usb_init();
-}
-
-MACHINE_START(PAZ00, "Toshiba AC100 / Dynabook AZ")
- .atag_offset = 0x100,
- .fixup = tegra_paz00_fixup,
- .map_io = tegra_map_common_io,
- .init_early = tegra20_init_early,
- .init_irq = tegra_init_irq,
- .handle_irq = gic_handle_irq,
- .timer = &tegra_timer,
- .init_machine = tegra_paz00_init,
- .init_late = tegra_init_late,
- .restart = tegra_assert_system_reset,
-MACHINE_END
diff --git a/arch/arm/mach-tegra/board-paz00.h b/arch/arm/mach-tegra/board-paz00.h
index 3c9f8da..25c08ec 100644
--- a/arch/arm/mach-tegra/board-paz00.h
+++ b/arch/arm/mach-tegra/board-paz00.h
@@ -17,24 +17,9 @@
#ifndef _MACH_TEGRA_BOARD_PAZ00_H
#define _MACH_TEGRA_BOARD_PAZ00_H
-#include <mach/gpio-tegra.h>
+#include "gpio-names.h"
-/* SDCARD */
-#define TEGRA_GPIO_SD1_CD TEGRA_GPIO_PV5
-#define TEGRA_GPIO_SD1_WP TEGRA_GPIO_PH1
-#define TEGRA_GPIO_SD1_POWER TEGRA_GPIO_PV1
-
-/* ULPI */
-#define TEGRA_ULPI_RST TEGRA_GPIO_PV0
-
-/* WIFI */
#define TEGRA_WIFI_PWRN TEGRA_GPIO_PK5
#define TEGRA_WIFI_RST TEGRA_GPIO_PD1
-#define TEGRA_WIFI_LED TEGRA_GPIO_PD0
-
-/* WakeUp */
-#define TEGRA_GPIO_POWERKEY TEGRA_GPIO_PJ7
-
-void paz00_pinmux_init(void);
#endif
diff --git a/arch/arm/mach-tegra/board-trimslice-pinmux.c b/arch/arm/mach-tegra/board-trimslice-pinmux.c
deleted file mode 100644
index 7b39511..0000000
--- a/arch/arm/mach-tegra/board-trimslice-pinmux.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-trimslice-pinmux.c
- *
- * Copyright (C) 2011 CompuLab, Ltd.
- * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-#include <linux/kernel.h>
-
-#include "board-trimslice.h"
-#include "board-pinmux.h"
-
-static struct pinctrl_map trimslice_map[] = {
- TEGRA_MAP_MUXCONF("ata", "ide", none, tristate),
- TEGRA_MAP_MUXCONF("atb", "sdio4", none, driven),
- TEGRA_MAP_MUXCONF("atc", "nand", none, tristate),
- TEGRA_MAP_MUXCONF("atd", "gmi", none, tristate),
- TEGRA_MAP_MUXCONF("ate", "gmi", none, tristate),
- TEGRA_MAP_MUXCONF("cdev1", "plla_out", none, driven),
- TEGRA_MAP_MUXCONF("cdev2", "pllp_out4", down, tristate),
- TEGRA_MAP_MUXCONF("crtp", "crt", none, tristate),
- TEGRA_MAP_MUXCONF("csus", "vi_sensor_clk", down, tristate),
- TEGRA_MAP_MUXCONF("dap1", "dap1", none, driven),
- TEGRA_MAP_MUXCONF("dap2", "dap2", none, tristate),
- TEGRA_MAP_MUXCONF("dap3", "dap3", none, tristate),
- TEGRA_MAP_MUXCONF("dap4", "dap4", none, tristate),
- TEGRA_MAP_MUXCONF("ddc", "i2c2", up, driven),
- TEGRA_MAP_MUXCONF("dta", "vi", none, tristate),
- TEGRA_MAP_MUXCONF("dtb", "vi", none, tristate),
- TEGRA_MAP_MUXCONF("dtc", "vi", none, tristate),
- TEGRA_MAP_MUXCONF("dtd", "vi", none, tristate),
- TEGRA_MAP_MUXCONF("dte", "vi", none, tristate),
- TEGRA_MAP_MUXCONF("dtf", "i2c3", up, driven),
- TEGRA_MAP_MUXCONF("gma", "sdio4", none, driven),
- TEGRA_MAP_MUXCONF("gmb", "nand", none, tristate),
- TEGRA_MAP_MUXCONF("gmc", "sflash", none, driven),
- TEGRA_MAP_MUXCONF("gmd", "sflash", none, driven),
- TEGRA_MAP_MUXCONF("gme", "gmi", none, tristate),
- TEGRA_MAP_MUXCONF("gpu", "uarta", none, driven),
- TEGRA_MAP_MUXCONF("gpu7", "rtck", none, driven),
- TEGRA_MAP_MUXCONF("gpv", "pcie", none, driven),
- TEGRA_MAP_MUXCONF("hdint", "hdmi", na, tristate),
- TEGRA_MAP_MUXCONF("i2cp", "i2cp", none, tristate),
- TEGRA_MAP_MUXCONF("irrx", "uartb", up, tristate),
- TEGRA_MAP_MUXCONF("irtx", "uartb", up, tristate),
- TEGRA_MAP_MUXCONF("kbca", "kbc", up, tristate),
- TEGRA_MAP_MUXCONF("kbcb", "kbc", up, tristate),
- TEGRA_MAP_MUXCONF("kbcc", "kbc", up, tristate),
- TEGRA_MAP_MUXCONF("kbcd", "kbc", up, tristate),
- TEGRA_MAP_MUXCONF("kbce", "kbc", up, tristate),
- TEGRA_MAP_MUXCONF("kbcf", "kbc", up, tristate),
- TEGRA_MAP_MUXCONF("lcsn", "displaya", na, tristate),
- TEGRA_MAP_MUXCONF("ld0", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld1", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld10", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld11", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld12", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld13", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld14", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld15", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld16", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld17", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld2", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld3", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld4", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld5", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld6", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld7", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld8", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ld9", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("ldc", "displaya", na, tristate),
- TEGRA_MAP_MUXCONF("ldi", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("lhp0", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("lhp1", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("lhp2", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("lhs", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("lm0", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("lm1", "displaya", na, tristate),
- TEGRA_MAP_MUXCONF("lpp", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("lpw0", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("lpw1", "displaya", na, tristate),
- TEGRA_MAP_MUXCONF("lpw2", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("lsc0", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("lsc1", "displaya", na, tristate),
- TEGRA_MAP_MUXCONF("lsck", "displaya", na, tristate),
- TEGRA_MAP_MUXCONF("lsda", "displaya", na, tristate),
- TEGRA_MAP_MUXCONF("lsdi", "displaya", na, tristate),
- TEGRA_MAP_MUXCONF("lspi", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("lvp0", "displaya", na, tristate),
- TEGRA_MAP_MUXCONF("lvp1", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("lvs", "displaya", na, driven),
- TEGRA_MAP_MUXCONF("owc", "rsvd2", up, tristate),
- TEGRA_MAP_MUXCONF("pmc", "pwr_on", na, tristate),
- TEGRA_MAP_MUXCONF("pta", "gmi", none, tristate),
- TEGRA_MAP_MUXCONF("rm", "i2c1", up, driven),
- TEGRA_MAP_MUXCONF("sdb", "pwm", na, driven),
- TEGRA_MAP_MUXCONF("sdc", "pwm", up, driven),
- TEGRA_MAP_MUXCONF("sdd", "pwm", up, driven),
- TEGRA_MAP_MUXCONF("sdio1", "sdio1", none, driven),
- TEGRA_MAP_MUXCONF("slxa", "pcie", none, driven),
- TEGRA_MAP_MUXCONF("slxc", "sdio3", none, tristate),
- TEGRA_MAP_MUXCONF("slxd", "sdio3", none, tristate),
- TEGRA_MAP_MUXCONF("slxk", "pcie", none, driven),
- TEGRA_MAP_MUXCONF("spdi", "spdif", none, tristate),
- TEGRA_MAP_MUXCONF("spdo", "spdif", none, tristate),
- TEGRA_MAP_MUXCONF("spia", "spi2", down, tristate),
- TEGRA_MAP_MUXCONF("spib", "spi2", down, tristate),
- TEGRA_MAP_MUXCONF("spic", "spi2", up, tristate),
- TEGRA_MAP_MUXCONF("spid", "spi1", down, tristate),
- TEGRA_MAP_MUXCONF("spie", "spi1", up, tristate),
- TEGRA_MAP_MUXCONF("spif", "spi1", down, tristate),
- TEGRA_MAP_MUXCONF("spig", "spi2_alt", up, tristate),
- TEGRA_MAP_MUXCONF("spih", "spi2_alt", up, tristate),
- TEGRA_MAP_MUXCONF("uaa", "ulpi", up, tristate),
- TEGRA_MAP_MUXCONF("uab", "ulpi", up, tristate),
- TEGRA_MAP_MUXCONF("uac", "rsvd2", none, driven),
- TEGRA_MAP_MUXCONF("uad", "irda", up, tristate),
- TEGRA_MAP_MUXCONF("uca", "uartc", up, tristate),
- TEGRA_MAP_MUXCONF("ucb", "uartc", up, tristate),
- TEGRA_MAP_MUXCONF("uda", "ulpi", none, tristate),
- TEGRA_MAP_CONF("ck32", none, na),
- TEGRA_MAP_CONF("ddrc", none, na),
- TEGRA_MAP_CONF("pmca", none, na),
- TEGRA_MAP_CONF("pmcb", none, na),
- TEGRA_MAP_CONF("pmcc", none, na),
- TEGRA_MAP_CONF("pmcd", none, na),
- TEGRA_MAP_CONF("pmce", none, na),
- TEGRA_MAP_CONF("xm2c", none, na),
- TEGRA_MAP_CONF("xm2d", none, na),
- TEGRA_MAP_CONF("ls", up, na),
- TEGRA_MAP_CONF("lc", up, na),
- TEGRA_MAP_CONF("ld17_0", down, na),
- TEGRA_MAP_CONF("ld19_18", down, na),
- TEGRA_MAP_CONF("ld21_20", down, na),
- TEGRA_MAP_CONF("ld23_22", down, na),
-};
-
-static struct tegra_board_pinmux_conf conf = {
- .maps = trimslice_map,
- .map_count = ARRAY_SIZE(trimslice_map),
-};
-
-void trimslice_pinmux_init(void)
-{
- tegra_board_pinmux_init(&conf, NULL);
-}
diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c
deleted file mode 100644
index 776aa95..0000000
--- a/arch/arm/mach-tegra/board-trimslice.c
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-trimslice.c
- *
- * Copyright (C) 2011 CompuLab, Ltd.
- * Author: Mike Rapoport <mike@compulab.co.il>
- *
- * Based on board-harmony.c
- * Copyright (C) 2010 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/serial_8250.h>
-#include <linux/of_serial.h>
-#include <linux/io.h>
-#include <linux/i2c.h>
-#include <linux/gpio.h>
-#include <linux/platform_data/tegra_usb.h>
-
-#include <asm/hardware/gic.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/setup.h>
-
-#include <mach/iomap.h>
-#include <mach/sdhci.h>
-
-#include "board.h"
-#include "clock.h"
-#include "devices.h"
-#include "gpio-names.h"
-
-#include "board-trimslice.h"
-
-static struct plat_serial8250_port debug_uart_platform_data[] = {
- {
- .membase = IO_ADDRESS(TEGRA_UARTA_BASE),
- .mapbase = TEGRA_UARTA_BASE,
- .irq = INT_UARTA,
- .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
- .type = PORT_TEGRA,
- .handle_break = tegra_serial_handle_break,
- .iotype = UPIO_MEM,
- .regshift = 2,
- .uartclk = 216000000,
- }, {
- .flags = 0
- }
-};
-
-static struct platform_device debug_uart = {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM,
- .dev = {
- .platform_data = debug_uart_platform_data,
- },
-};
-static struct tegra_sdhci_platform_data sdhci_pdata1 = {
- .cd_gpio = -1,
- .wp_gpio = -1,
- .power_gpio = -1,
-};
-
-static struct tegra_sdhci_platform_data sdhci_pdata4 = {
- .cd_gpio = TRIMSLICE_GPIO_SD4_CD,
- .wp_gpio = TRIMSLICE_GPIO_SD4_WP,
- .power_gpio = -1,
-};
-
-static struct platform_device trimslice_audio_device = {
- .name = "tegra-snd-trimslice",
- .id = 0,
-};
-
-static struct platform_device *trimslice_devices[] __initdata = {
- &debug_uart,
- &tegra_sdhci_device1,
- &tegra_sdhci_device4,
- &tegra_i2s_device1,
- &tegra_das_device,
- &trimslice_audio_device,
-};
-
-static struct i2c_board_info trimslice_i2c3_board_info[] = {
- {
- I2C_BOARD_INFO("tlv320aic23", 0x1a),
- },
- {
- I2C_BOARD_INFO("em3027", 0x56),
- },
-};
-
-static void trimslice_i2c_init(void)
-{
- platform_device_register(&tegra_i2c_device1);
- platform_device_register(&tegra_i2c_device2);
- platform_device_register(&tegra_i2c_device3);
-
- i2c_register_board_info(2, trimslice_i2c3_board_info,
- ARRAY_SIZE(trimslice_i2c3_board_info));
-}
-
-static void trimslice_usb_init(void)
-{
- struct tegra_ehci_platform_data *pdata;
-
- pdata = tegra_ehci1_device.dev.platform_data;
- pdata->vbus_gpio = TRIMSLICE_GPIO_USB1_MODE;
-
- tegra_ehci2_ulpi_phy_config.reset_gpio = TEGRA_GPIO_PV0;
-
- platform_device_register(&tegra_ehci3_device);
- platform_device_register(&tegra_ehci2_device);
- platform_device_register(&tegra_ehci1_device);
-}
-
-static void __init tegra_trimslice_fixup(struct tag *tags, char **cmdline,
- struct meminfo *mi)
-{
- mi->nr_banks = 2;
- mi->bank[0].start = PHYS_OFFSET;
- mi->bank[0].size = 448 * SZ_1M;
- mi->bank[1].start = SZ_512M;
- mi->bank[1].size = SZ_512M;
-}
-
-static __initdata struct tegra_clk_init_table trimslice_clk_init_table[] = {
- /* name parent rate enabled */
- { "uarta", "pll_p", 216000000, true },
- { "pll_a", "pll_p_out1", 56448000, true },
- { "pll_a_out0", "pll_a", 11289600, true },
- { "cdev1", NULL, 0, true },
- { "i2s1", "pll_a_out0", 11289600, false},
- { NULL, NULL, 0, 0},
-};
-
-static int __init tegra_trimslice_pci_init(void)
-{
- if (!machine_is_trimslice())
- return 0;
-
- return tegra_pcie_init(true, true);
-}
-subsys_initcall(tegra_trimslice_pci_init);
-
-static void __init tegra_trimslice_init(void)
-{
- tegra_clk_init_from_table(trimslice_clk_init_table);
-
- trimslice_pinmux_init();
-
- tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1;
- tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4;
-
- platform_add_devices(trimslice_devices, ARRAY_SIZE(trimslice_devices));
-
- trimslice_i2c_init();
- trimslice_usb_init();
-}
-
-MACHINE_START(TRIMSLICE, "trimslice")
- .atag_offset = 0x100,
- .fixup = tegra_trimslice_fixup,
- .map_io = tegra_map_common_io,
- .init_early = tegra20_init_early,
- .init_irq = tegra_init_irq,
- .handle_irq = gic_handle_irq,
- .timer = &tegra_timer,
- .init_machine = tegra_trimslice_init,
- .init_late = tegra_init_late,
- .restart = tegra_assert_system_reset,
-MACHINE_END
diff --git a/arch/arm/mach-tegra/board-trimslice.h b/arch/arm/mach-tegra/board-trimslice.h
deleted file mode 100644
index 50f128d..0000000
--- a/arch/arm/mach-tegra/board-trimslice.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-trimslice.h
- *
- * Copyright (C) 2011 CompuLab, Ltd.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _MACH_TEGRA_BOARD_TRIMSLICE_H
-#define _MACH_TEGRA_BOARD_TRIMSLICE_H
-
-#include <mach/gpio-tegra.h>
-
-#define TRIMSLICE_GPIO_SD4_CD TEGRA_GPIO_PP1 /* mmc4 cd */
-#define TRIMSLICE_GPIO_SD4_WP TEGRA_GPIO_PP2 /* mmc4 wp */
-
-#define TRIMSLICE_GPIO_USB1_MODE TEGRA_GPIO_PV2 /* USB1 mode */
-#define TRIMSLICE_GPIO_USB2_RST TEGRA_GPIO_PV0 /* USB2 PHY reset */
-
-void trimslice_pinmux_init(void);
-
-#endif
diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c
index c70e65f..61e9603 100644
--- a/arch/arm/mach-tegra/devices.c
+++ b/arch/arm/mach-tegra/devices.c
@@ -23,7 +23,6 @@
#include <linux/fsl_devices.h>
#include <linux/serial_8250.h>
#include <linux/i2c-tegra.h>
-#include <asm/pmu.h>
#include <mach/irqs.h>
#include <mach/iomap.h>
#include <mach/dma.h>
@@ -516,7 +515,7 @@
struct platform_device tegra_pmu_device = {
.name = "arm-pmu",
- .id = ARM_PMU_DEVICE_CPU,
+ .id = -1,
.num_resources = ARRAY_SIZE(tegra_pmu_resources),
.resource = tegra_pmu_resources,
};
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c
index f946d12..0b7db17 100644
--- a/arch/arm/mach-tegra/fuse.c
+++ b/arch/arm/mach-tegra/fuse.c
@@ -93,9 +93,9 @@
{
u32 id;
- u32 reg = readl(IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
+ u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
reg |= 1 << 28;
- writel(reg, IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
+ writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48));
reg = tegra_fuse_readl(FUSE_SKU_INFO);
tegra_sku_id = reg & 0xFF;
diff --git a/arch/arm/mach-tegra/include/mach/io.h b/arch/arm/mach-tegra/include/mach/io.h
deleted file mode 100644
index fe700f9..0000000
--- a/arch/arm/mach-tegra/include/mach/io.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * arch/arm/mach-tegra/include/mach/io.h
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * Author:
- * Colin Cross <ccross@google.com>
- * Erik Gilling <konkers@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __MACH_TEGRA_IO_H
-#define __MACH_TEGRA_IO_H
-
-#define IO_SPACE_LIMIT 0xffff
-
-#ifndef __ASSEMBLER__
-
-#ifdef CONFIG_TEGRA_PCI
-extern void __iomem *tegra_pcie_io_base;
-
-static inline void __iomem *__io(unsigned long addr)
-{
- return tegra_pcie_io_base + (addr & IO_SPACE_LIMIT);
-}
-#else
-static inline void __iomem *__io(unsigned long addr)
-{
- return (void __iomem *)addr;
-}
-#endif
-
-#define __io(a) __io(a)
-
-#endif
-
-#endif
diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
index 7e76da7..fee3a94 100644
--- a/arch/arm/mach-tegra/include/mach/iomap.h
+++ b/arch/arm/mach-tegra/include/mach/iomap.h
@@ -303,6 +303,9 @@
#define IO_APB_VIRT IOMEM(0xFE300000)
#define IO_APB_SIZE SZ_1M
+#define TEGRA_PCIE_BASE 0x80000000
+#define TEGRA_PCIE_IO_BASE (TEGRA_PCIE_BASE + SZ_4M)
+
#define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz)))
#define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst)))
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index d3ad515..3463fb5 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -171,8 +171,6 @@
* 0x90000000 - 0x9fffffff - non-prefetchable memory
* 0xa0000000 - 0xbfffffff - prefetchable memory
*/
-#define TEGRA_PCIE_BASE 0x80000000
-
#define PCIE_REGS_SZ SZ_16K
#define PCIE_CFG_OFF PCIE_REGS_SZ
#define PCIE_CFG_SZ SZ_1M
@@ -180,8 +178,6 @@
#define PCIE_EXT_CFG_SZ SZ_1M
#define PCIE_IOMAP_SZ (PCIE_REGS_SZ + PCIE_CFG_SZ + PCIE_EXT_CFG_SZ)
-#define MMIO_BASE (TEGRA_PCIE_BASE + SZ_4M)
-#define MMIO_SIZE SZ_64K
#define MEM_BASE_0 (TEGRA_PCIE_BASE + SZ_256M)
#define MEM_SIZE_0 SZ_128M
#define MEM_BASE_1 (MEM_BASE_0 + MEM_SIZE_0)
@@ -204,10 +200,9 @@
bool link_up;
- char io_space_name[16];
char mem_space_name[16];
char prefetch_space_name[20];
- struct resource res[3];
+ struct resource res[2];
};
struct tegra_pcie_info {
@@ -223,17 +218,7 @@
struct clk *pll_e;
};
-static struct tegra_pcie_info tegra_pcie = {
- .res_mmio = {
- .name = "PCI IO",
- .start = MMIO_BASE,
- .end = MMIO_BASE + MMIO_SIZE - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-void __iomem *tegra_pcie_io_base;
-EXPORT_SYMBOL(tegra_pcie_io_base);
+static struct tegra_pcie_info tegra_pcie;
static inline void afi_writel(u32 value, unsigned long offset)
{
@@ -391,24 +376,7 @@
pp = tegra_pcie.port + nr;
pp->root_bus_nr = sys->busnr;
- /*
- * IORESOURCE_IO
- */
- snprintf(pp->io_space_name, sizeof(pp->io_space_name),
- "PCIe %d I/O", pp->index);
- pp->io_space_name[sizeof(pp->io_space_name) - 1] = 0;
- pp->res[0].name = pp->io_space_name;
- if (pp->index == 0) {
- pp->res[0].start = PCIBIOS_MIN_IO;
- pp->res[0].end = pp->res[0].start + SZ_32K - 1;
- } else {
- pp->res[0].start = PCIBIOS_MIN_IO + SZ_32K;
- pp->res[0].end = IO_SPACE_LIMIT;
- }
- pp->res[0].flags = IORESOURCE_IO;
- if (request_resource(&ioport_resource, &pp->res[0]))
- panic("Request PCIe IO resource failed\n");
- pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
+ pci_ioremap_io(nr * SZ_64K, TEGRA_PCIE_IO_BASE);
/*
* IORESOURCE_MEM
@@ -416,18 +384,18 @@
snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
"PCIe %d MEM", pp->index);
pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
- pp->res[1].name = pp->mem_space_name;
+ pp->res[0].name = pp->mem_space_name;
if (pp->index == 0) {
- pp->res[1].start = MEM_BASE_0;
- pp->res[1].end = pp->res[1].start + MEM_SIZE_0 - 1;
+ pp->res[0].start = MEM_BASE_0;
+ pp->res[0].end = pp->res[0].start + MEM_SIZE_0 - 1;
} else {
- pp->res[1].start = MEM_BASE_1;
- pp->res[1].end = pp->res[1].start + MEM_SIZE_1 - 1;
+ pp->res[0].start = MEM_BASE_1;
+ pp->res[0].end = pp->res[0].start + MEM_SIZE_1 - 1;
}
- pp->res[1].flags = IORESOURCE_MEM;
- if (request_resource(&iomem_resource, &pp->res[1]))
+ pp->res[0].flags = IORESOURCE_MEM;
+ if (request_resource(&iomem_resource, &pp->res[0]))
panic("Request PCIe Memory resource failed\n");
- pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
+ pci_add_resource_offset(&sys->resources, &pp->res[0], sys->mem_offset);
/*
* IORESOURCE_MEM | IORESOURCE_PREFETCH
@@ -435,18 +403,18 @@
snprintf(pp->prefetch_space_name, sizeof(pp->prefetch_space_name),
"PCIe %d PREFETCH MEM", pp->index);
pp->prefetch_space_name[sizeof(pp->prefetch_space_name) - 1] = 0;
- pp->res[2].name = pp->prefetch_space_name;
+ pp->res[1].name = pp->prefetch_space_name;
if (pp->index == 0) {
- pp->res[2].start = PREFETCH_MEM_BASE_0;
- pp->res[2].end = pp->res[2].start + PREFETCH_MEM_SIZE_0 - 1;
+ pp->res[1].start = PREFETCH_MEM_BASE_0;
+ pp->res[1].end = pp->res[1].start + PREFETCH_MEM_SIZE_0 - 1;
} else {
- pp->res[2].start = PREFETCH_MEM_BASE_1;
- pp->res[2].end = pp->res[2].start + PREFETCH_MEM_SIZE_1 - 1;
+ pp->res[1].start = PREFETCH_MEM_BASE_1;
+ pp->res[1].end = pp->res[1].start + PREFETCH_MEM_SIZE_1 - 1;
}
- pp->res[2].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
- if (request_resource(&iomem_resource, &pp->res[2]))
+ pp->res[1].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
+ if (request_resource(&iomem_resource, &pp->res[1]))
panic("Request PCIe Prefetch Memory resource failed\n");
- pci_add_resource_offset(&sys->resources, &pp->res[2], sys->mem_offset);
+ pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
return 1;
}
@@ -541,8 +509,8 @@
/* Bar 2: downstream IO bar */
fpci_bar = ((__u32)0xfdfc << 16);
- size = MMIO_SIZE;
- axi_address = MMIO_BASE;
+ size = SZ_128K;
+ axi_address = TEGRA_PCIE_IO_BASE;
afi_writel(axi_address, AFI_AXI_BAR2_START);
afi_writel(size >> 12, AFI_AXI_BAR2_SZ);
afi_writel(fpci_bar, AFI_FPCI_BAR2);
@@ -776,7 +744,6 @@
static int __init tegra_pcie_get_resources(void)
{
- struct resource *res_mmio = &tegra_pcie.res_mmio;
int err;
err = tegra_pcie_clocks_get();
@@ -798,34 +765,16 @@
goto err_map_reg;
}
- err = request_resource(&iomem_resource, res_mmio);
- if (err) {
- pr_err("PCIE: Failed to request resources: %d\n", err);
- goto err_req_io;
- }
-
- tegra_pcie_io_base = ioremap_nocache(res_mmio->start,
- resource_size(res_mmio));
- if (tegra_pcie_io_base == NULL) {
- pr_err("PCIE: Failed to map IO\n");
- err = -ENOMEM;
- goto err_map_io;
- }
-
err = request_irq(INT_PCIE_INTR, tegra_pcie_isr,
IRQF_SHARED, "PCIE", &tegra_pcie);
if (err) {
pr_err("PCIE: Failed to register IRQ: %d\n", err);
- goto err_irq;
+ goto err_req_io;
}
set_irq_flags(INT_PCIE_INTR, IRQF_VALID);
return 0;
-err_irq:
- iounmap(tegra_pcie_io_base);
-err_map_io:
- release_resource(&tegra_pcie.res_mmio);
err_req_io:
iounmap(tegra_pcie.regs);
err_map_reg:
diff --git a/arch/arm/mach-u300/Kconfig b/arch/arm/mach-u300/Kconfig
index 54d8f34..f7e12ed 100644
--- a/arch/arm/mach-u300/Kconfig
+++ b/arch/arm/mach-u300/Kconfig
@@ -1,6 +1,6 @@
if ARCH_U300
-menu "ST-Ericsson AB U300/U330/U335/U365 Platform"
+menu "ST-Ericsson AB U300/U335 Platform"
comment "ST-Ericsson Mobile Platform Products"
@@ -10,46 +10,7 @@
select PINCTRL_U300
select PINCTRL_COH901
-comment "ST-Ericsson U300/U330/U335/U365 Feature Selections"
-
-choice
- prompt "U300/U330/U335/U365 system type"
- default MACH_U300_BS2X
- ---help---
- You need to select the target system, i.e. the
- U300/U330/U335/U365 board that you want to compile your kernel
- for.
-
-config MACH_U300_BS2X
- bool "S26/S26/B25/B26 Test Products"
- depends on MACH_U300
- help
- Select this if you're developing on the
- S26/S25 test products. (Also works on
- B26/B25 big boards.)
-
-config MACH_U300_BS330
- bool "S330/B330 Test Products"
- depends on MACH_U300
- help
- Select this if you're developing on the
- S330/B330 test products.
-
-config MACH_U300_BS335
- bool "S335/B335 Test Products"
- depends on MACH_U300
- help
- Select this if you're developing on the
- S335/B335 test products.
-
-config MACH_U300_BS365
- bool "S365/B365 Test Products"
- depends on MACH_U300
- help
- Select this if you're developing on the
- S365/B365 test products.
-
-endchoice
+comment "ST-Ericsson U300/U335 Feature Selections"
config U300_DEBUG
bool "Debug support for U300"
diff --git a/arch/arm/mach-u300/Makefile b/arch/arm/mach-u300/Makefile
index 7e47d37..5a86c58 100644
--- a/arch/arm/mach-u300/Makefile
+++ b/arch/arm/mach-u300/Makefile
@@ -7,7 +7,6 @@
obj-n :=
obj- :=
-obj-$(CONFIG_ARCH_U300) += u300.o
obj-$(CONFIG_SPI_PL022) += spi.o
obj-$(CONFIG_MACH_U300_SPIDUMMY) += dummyspichip.o
obj-$(CONFIG_I2C_STU300) += i2c.o
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 03acf18..ef6f602 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -3,7 +3,7 @@
* arch/arm/mach-u300/core.c
*
*
- * Copyright (C) 2007-2010 ST-Ericsson SA
+ * Copyright (C) 2007-2012 ST-Ericsson SA
* License terms: GNU General Public License (GPL) version 2
* Core platform support, IRQ handling and device definitions.
* Author: Linus Walleij <linus.walleij@stericsson.com>
@@ -31,23 +31,26 @@
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/dma-mapping.h>
#include <linux/platform_data/clk-u300.h>
+#include <linux/platform_data/pinctrl-coh901.h>
#include <asm/types.h>
#include <asm/setup.h>
#include <asm/memory.h>
#include <asm/hardware/vic.h>
#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
#include <mach/coh901318.h>
#include <mach/hardware.h>
#include <mach/syscon.h>
-#include <mach/dma_channels.h>
-#include <mach/gpio-u300.h>
+#include <mach/irqs.h>
+#include "timer.h"
#include "spi.h"
#include "i2c.h"
#include "u300-gpio.h"
+#include "dma_channels.h"
/*
* Static I/O mappings that are needed for booting the U300 platforms. The
@@ -76,7 +79,7 @@
},
};
-void __init u300_map_io(void)
+static void __init u300_map_io(void)
{
iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
/* We enable a real big DMA buffer if need be. */
@@ -101,7 +104,6 @@
{ IRQ_U300_UART0 }, &uart0_plat_data);
/* The U335 have an additional UART1 on the APP CPU */
-#ifdef CONFIG_MACH_U300_BS335
static struct amba_pl011_data uart1_plat_data = {
#ifdef CONFIG_COH901318
.dma_filter = coh901318_filter_id,
@@ -113,7 +115,6 @@
/* Fast device at 0x7000 offset */
static AMBA_APB_DEVICE(uart1, "uart1", 0, U300_UART1_BASE,
{ IRQ_U300_UART1 }, &uart1_plat_data);
-#endif
/* AHB device at 0x4000 offset */
static AMBA_APB_DEVICE(pl172, "pl172", 0, U300_EMIF_CFG_BASE, { }, NULL);
@@ -152,9 +153,7 @@
*/
static struct amba_device *amba_devs[] __initdata = {
&uart0_device,
-#ifdef CONFIG_MACH_U300_BS335
&uart1_device,
-#endif
&pl022_device,
&pl172_device,
&mmcsd_device,
@@ -188,7 +187,6 @@
.end = IRQ_U300_GPIO_PORT2,
.flags = IORESOURCE_IRQ,
},
-#if defined(CONFIG_MACH_U300_BS365) || defined(CONFIG_MACH_U300_BS335)
{
.name = "gpio3",
.start = IRQ_U300_GPIO_PORT3,
@@ -201,8 +199,6 @@
.end = IRQ_U300_GPIO_PORT4,
.flags = IORESOURCE_IRQ,
},
-#endif
-#ifdef CONFIG_MACH_U300_BS335
{
.name = "gpio5",
.start = IRQ_U300_GPIO_PORT5,
@@ -215,7 +211,6 @@
.end = IRQ_U300_GPIO_PORT6,
.flags = IORESOURCE_IRQ,
},
-#endif /* CONFIG_MACH_U300_BS335 */
};
static struct resource keypad_resources[] = {
@@ -323,7 +318,6 @@
}
};
-#ifdef CONFIG_MACH_U300_BS335
/* points out all dma slave channels.
* Syntax is [A1, B1, A2, B2, .... ,-1,-1]
* Select all channels from A to B, end of list is marked with -1,-1
@@ -336,14 +330,6 @@
static int dma_memcpy_channels[] = {
U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
-#else /* CONFIG_MACH_U300_BS335 */
-
-static int dma_slave_channels[] = {U300_DMA_MSL_TX_0, U300_DMA_SPI_RX, -1, -1};
-static int dma_memcpy_channels[] = {
- U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_10, -1, -1};
-
-#endif
-
/** register dma for memory access
*
* active 1 means dma intends to access memory
@@ -1395,7 +1381,6 @@
.param.ctrl_lli = flags_memcpy_lli,
.param.ctrl_lli_last = flags_memcpy_lli_last,
},
-#ifdef CONFIG_MACH_U300_BS335
{
.number = U300_DMA_UART1_TX,
.name = "UART1 TX",
@@ -1406,28 +1391,6 @@
.name = "UART1 RX",
.priority_high = 0,
}
-#else
- {
- .number = U300_DMA_GENERAL_PURPOSE_9,
- .name = "GENERAL 09",
- .priority_high = 0,
-
- .param.config = flags_memcpy_config,
- .param.ctrl_lli_chained = flags_memcpy_lli_chained,
- .param.ctrl_lli = flags_memcpy_lli,
- .param.ctrl_lli_last = flags_memcpy_lli_last,
- },
- {
- .number = U300_DMA_GENERAL_PURPOSE_10,
- .name = "GENERAL 10",
- .priority_high = 0,
-
- .param.config = flags_memcpy_config,
- .param.ctrl_lli_chained = flags_memcpy_lli_chained,
- .param.ctrl_lli = flags_memcpy_lli,
- .param.ctrl_lli_last = flags_memcpy_lli_last,
- }
-#endif
};
@@ -1480,18 +1443,7 @@
* GPIO block, with different number of ports.
*/
static struct u300_gpio_platform u300_gpio_plat = {
-#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
- .variant = U300_GPIO_COH901335,
- .ports = 3,
-#endif
-#ifdef CONFIG_MACH_U300_BS335
- .variant = U300_GPIO_COH901571_3_BS335,
.ports = 7,
-#endif
-#ifdef CONFIG_MACH_U300_BS365
- .variant = U300_GPIO_COH901571_3_BS365,
- .ports = 5,
-#endif
.gpio_base = 0,
.gpio_irq_base = IRQ_U300_GPIO_BASE,
.pinctrl_device = &pinctrl_device,
@@ -1651,7 +1603,7 @@
* together so some interrupts are connected to the first one and some
* to the second one.
*/
-void __init u300_init_irq(void)
+static void __init u300_init_irq(void)
{
u32 mask[2] = {0, 0};
struct clk *clk;
@@ -1756,29 +1708,11 @@
printk(KERN_INFO "Initializing U300 system on %s baseband chip " \
"(chip ID 0x%04x)\n", chipname, val);
-#ifdef CONFIG_MACH_U300_BS330
- if ((val & 0xFF00U) != 0xd800) {
- printk(KERN_ERR "Platform configured for BS330 " \
- "with DB3200 but %s detected, expect problems!",
- chipname);
- }
-#endif
-#ifdef CONFIG_MACH_U300_BS335
if ((val & 0xFF00U) != 0xf000 && (val & 0xFF00U) != 0xf100) {
printk(KERN_ERR "Platform configured for BS335 " \
" with DB3350 but %s detected, expect problems!",
chipname);
}
-#endif
-#ifdef CONFIG_MACH_U300_BS365
- if ((val & 0xFF00U) != 0xe800) {
- printk(KERN_ERR "Platform configured for BS365 " \
- "with DB3210 but %s detected, expect problems!",
- chipname);
- }
-#endif
-
-
}
/*
@@ -1811,7 +1745,7 @@
}
}
-void __init u300_init_devices(void)
+static void __init u300_init_machine(void)
{
int i;
u16 val;
@@ -1852,7 +1786,7 @@
/* Forward declare this function from the watchdog */
void coh901327_watchdog_reset(void);
-void u300_restart(char mode, const char *cmd)
+static void u300_restart(char mode, const char *cmd)
{
switch (mode) {
case 's':
@@ -1868,3 +1802,15 @@
/* Wait for system do die/reset. */
while (1);
}
+
+MACHINE_START(U300, "Ericsson AB U335 S335/B335 Prototype Board")
+ /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
+ .atag_offset = 0x100,
+ .map_io = u300_map_io,
+ .nr_irqs = NR_IRQS_U300,
+ .init_irq = u300_init_irq,
+ .handle_irq = vic_handle_irq,
+ .timer = &u300_timer,
+ .init_machine = u300_init_machine,
+ .restart = u300_restart,
+MACHINE_END
diff --git a/arch/arm/mach-u300/include/mach/dma_channels.h b/arch/arm/mach-u300/dma_channels.h
similarity index 88%
rename from arch/arm/mach-u300/include/mach/dma_channels.h
rename to arch/arm/mach-u300/dma_channels.h
index b239149..4e8a88f 100644
--- a/arch/arm/mach-u300/include/mach/dma_channels.h
+++ b/arch/arm/mach-u300/dma_channels.h
@@ -3,7 +3,7 @@
* arch/arm/mach-u300/include/mach/dma_channels.h
*
*
- * Copyright (C) 2007-2009 ST-Ericsson
+ * Copyright (C) 2007-2012 ST-Ericsson
* License terms: GNU General Public License (GPL) version 2
* Map file for the U300 dma driver.
* Author: Per Friden <per.friden@stericsson.com>
@@ -50,19 +50,10 @@
#define U300_DMA_GENERAL_PURPOSE_6 35
#define U300_DMA_GENERAL_PURPOSE_7 36
#define U300_DMA_GENERAL_PURPOSE_8 37
-#ifdef CONFIG_MACH_U300_BS335
#define U300_DMA_UART1_TX 38
#define U300_DMA_UART1_RX 39
-#else
-#define U300_DMA_GENERAL_PURPOSE_9 38
-#define U300_DMA_GENERAL_PURPOSE_10 39
-#endif
-#ifdef CONFIG_MACH_U300_BS335
#define U300_DMA_DEVICE_CHANNELS 32
-#else
-#define U300_DMA_DEVICE_CHANNELS 30
-#endif
#define U300_DMA_CHANNELS 40
diff --git a/arch/arm/mach-u300/i2c.c b/arch/arm/mach-u300/i2c.c
index cb04bd6..0d4620e 100644
--- a/arch/arm/mach-u300/i2c.c
+++ b/arch/arm/mach-u300/i2c.c
@@ -1,7 +1,7 @@
/*
* arch/arm/mach-u300/i2c.c
*
- * Copyright (C) 2009 ST-Ericsson AB
+ * Copyright (C) 2009-2012 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
*
* Register board i2c devices
@@ -261,7 +261,6 @@
};
static struct i2c_board_info __initdata bus1_i2c_board_info[] = {
-#ifdef CONFIG_MACH_U300_BS335
{
.type = "fwcam",
.addr = 0x10,
@@ -270,9 +269,6 @@
.type = "fwcam",
.addr = 0x5d,
},
-#else
- { },
-#endif
};
void __init u300_i2c_register_board_devices(void)
diff --git a/arch/arm/mach-u300/include/mach/clkdev.h b/arch/arm/mach-u300/include/mach/clkdev.h
deleted file mode 100644
index 92e3cc8..0000000
--- a/arch/arm/mach-u300/include/mach/clkdev.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __MACH_CLKDEV_H
-#define __MACH_CLKDEV_H
-
-int __clk_get(struct clk *clk);
-void __clk_put(struct clk *clk);
-
-#endif
diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h
index ec09c1e..e27425a 100644
--- a/arch/arm/mach-u300/include/mach/irqs.h
+++ b/arch/arm/mach-u300/include/mach/irqs.h
@@ -3,7 +3,7 @@
* arch/arm/mach-u300/include/mach/irqs.h
*
*
- * Copyright (C) 2006-2009 ST-Ericsson AB
+ * Copyright (C) 2006-2012 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
* IRQ channel definitions for the U300 platforms.
* Author: Linus Walleij <linus.walleij@stericsson.com>
@@ -31,10 +31,6 @@
#define IRQ_U300_XGAM_GAMCON 14
#define IRQ_U300_XGAM_CDI 15
#define IRQ_U300_XGAM_CDICON 16
-#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
-/* MMIACC not used on the DB3210 or DB3350 chips */
-#define IRQ_U300_XGAM_MMIACC 17
-#endif
#define IRQ_U300_XGAM_PDI 18
#define IRQ_U300_XGAM_PDICON 19
#define IRQ_U300_XGAM_GAMEACC 20
@@ -55,8 +51,6 @@
#define IRQ_U300_GPIO_PORT1 34
#define IRQ_U300_GPIO_PORT2 35
-#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) || \
- defined(CONFIG_MACH_U300_BS335)
/* These are for DB3150, DB3200 and DB3350 */
#define IRQ_U300_WDOG 36
#define IRQ_U300_EVHIST 37
@@ -68,15 +62,8 @@
#define IRQ_U300_RTC 43
#define IRQ_U300_NFIF 44
#define IRQ_U300_NFIF2 45
-#endif
-
-/* DB3150 and DB3200 have only 45 IRQs */
-#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
-#define U300_VIC_IRQS_END 46
-#endif
/* The DB3350-specific interrupt lines */
-#ifdef CONFIG_MACH_U300_BS335
#define IRQ_U300_ISP_F0 46
#define IRQ_U300_ISP_F1 47
#define IRQ_U300_ISP_F2 48
@@ -89,25 +76,6 @@
#define IRQ_U300_GPIO_PORT5 55
#define IRQ_U300_GPIO_PORT6 56
#define U300_VIC_IRQS_END 57
-#endif
-
-/* The DB3210-specific interrupt lines */
-#ifdef CONFIG_MACH_U300_BS365
-#define IRQ_U300_GPIO_PORT3 36
-#define IRQ_U300_GPIO_PORT4 37
-#define IRQ_U300_WDOG 38
-#define IRQ_U300_EVHIST 39
-#define IRQ_U300_MSPRO 40
-#define IRQ_U300_MMCSD_MCIINTR0 41
-#define IRQ_U300_MMCSD_MCIINTR1 42
-#define IRQ_U300_I2C0 43
-#define IRQ_U300_I2C1 44
-#define IRQ_U300_RTC 45
-#define IRQ_U300_NFIF 46
-#define IRQ_U300_NFIF2 47
-#define IRQ_U300_SYSCON_PLL_LOCK 48
-#define U300_VIC_IRQS_END 49
-#endif
/* Maximum 8*7 GPIO lines */
#ifdef CONFIG_PINCTRL_COH901
@@ -117,6 +85,6 @@
#define IRQ_U300_GPIO_END (U300_VIC_IRQS_END)
#endif
-#define NR_IRQS (IRQ_U300_GPIO_END - IRQ_U300_INTCON0_START)
+#define NR_IRQS_U300 (IRQ_U300_GPIO_END - IRQ_U300_INTCON0_START)
#endif
diff --git a/arch/arm/mach-u300/include/mach/platform.h b/arch/arm/mach-u300/include/mach/platform.h
deleted file mode 100644
index 096333f..0000000
--- a/arch/arm/mach-u300/include/mach/platform.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/include/mach/platform.h
- *
- *
- * Copyright (C) 2006-2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * Basic platform init and mapping functions.
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-
-#ifndef __ASSEMBLY__
-
-void u300_map_io(void);
-void u300_init_irq(void);
-void u300_init_devices(void);
-void u300_restart(char, const char *);
-extern struct sys_timer u300_timer;
-
-#endif
diff --git a/arch/arm/mach-u300/include/mach/syscon.h b/arch/arm/mach-u300/include/mach/syscon.h
index 6e84f07..10bdd0b 100644
--- a/arch/arm/mach-u300/include/mach/syscon.h
+++ b/arch/arm/mach-u300/include/mach/syscon.h
@@ -3,7 +3,7 @@
* arch/arm/mach-u300/include/mach/syscon.h
*
*
- * Copyright (C) 2008 ST-Ericsson AB
+ * Copyright (C) 2008-2012 ST-Ericsson AB
*
* Author: Rickard Andersson <rickard.andersson@stericsson.com>
*/
@@ -36,9 +36,7 @@
#define U300_SYSCON_CSR_PLL13_LOCK_IND (0x0001)
/* Reset lines for SLOW devices 16bit (R/W) */
#define U300_SYSCON_RSR (0x0014)
-#ifdef CONFIG_MACH_U300_BS335
#define U300_SYSCON_RSR_PPM_RESET_EN (0x0200)
-#endif
#define U300_SYSCON_RSR_ACC_TMR_RESET_EN (0x0100)
#define U300_SYSCON_RSR_APP_TMR_RESET_EN (0x0080)
#define U300_SYSCON_RSR_RTC_RESET_EN (0x0040)
@@ -50,9 +48,7 @@
#define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN (0x0001)
/* Reset lines for FAST devices 16bit (R/W) */
#define U300_SYSCON_RFR (0x0018)
-#ifdef CONFIG_MACH_U300_BS335
#define U300_SYSCON_RFR_UART1_RESET_ENABLE (0x0080)
-#endif
#define U300_SYSCON_RFR_SPI_RESET_ENABLE (0x0040)
#define U300_SYSCON_RFR_MMC_RESET_ENABLE (0x0020)
#define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE (0x0010)
@@ -62,10 +58,8 @@
#define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE (0x0001)
/* Reset lines for the rest of the peripherals 16bit (R/W) */
#define U300_SYSCON_RRR (0x001c)
-#ifdef CONFIG_MACH_U300_BS335
#define U300_SYSCON_RRR_CDS_RESET_EN (0x4000)
#define U300_SYSCON_RRR_ISP_RESET_EN (0x2000)
-#endif
#define U300_SYSCON_RRR_INTCON_RESET_EN (0x1000)
#define U300_SYSCON_RRR_MSPRO_RESET_EN (0x0800)
#define U300_SYSCON_RRR_XGAM_RESET_EN (0x0100)
@@ -79,9 +73,7 @@
#define U300_SYSCON_RRR_AAIF_RESET_EN (0x0001)
/* Clock enable for SLOW peripherals 16bit (R/W) */
#define U300_SYSCON_CESR (0x0020)
-#ifdef CONFIG_MACH_U300_BS335
#define U300_SYSCON_CESR_PPM_CLK_EN (0x0200)
-#endif
#define U300_SYSCON_CESR_ACC_TMR_CLK_EN (0x0100)
#define U300_SYSCON_CESR_APP_TMR_CLK_EN (0x0080)
#define U300_SYSCON_CESR_KEYPAD_CLK_EN (0x0040)
@@ -92,24 +84,20 @@
#define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN (0x0001)
/* Clock enable for FAST peripherals 16bit (R/W) */
#define U300_SYSCON_CEFR (0x0024)
-#ifdef CONFIG_MACH_U300_BS335
#define U300_SYSCON_CEFR_UART1_CLK_EN (0x0200)
-#endif
#define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN (0x0100)
#define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN (0x0080)
#define U300_SYSCON_CEFR_SPI_CLK_EN (0x0040)
#define U300_SYSCON_CEFR_MMC_CLK_EN (0x0020)
-#define U300_SYSCON_CEFR_I2S1_CLK_EN (0x0010)
-#define U300_SYSCON_CEFR_I2S0_CLK_EN (0x0008)
-#define U300_SYSCON_CEFR_I2C1_CLK_EN (0x0004)
-#define U300_SYSCON_CEFR_I2C0_CLK_EN (0x0002)
+#define U300_SYSCON_CEFR_I2S1_CLK_EN (0x0010)
+#define U300_SYSCON_CEFR_I2S0_CLK_EN (0x0008)
+#define U300_SYSCON_CEFR_I2C1_CLK_EN (0x0004)
+#define U300_SYSCON_CEFR_I2C0_CLK_EN (0x0002)
#define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN (0x0001)
/* Clock enable for the rest of the peripherals 16bit (R/W) */
#define U300_SYSCON_CERR (0x0028)
-#ifdef CONFIG_MACH_U300_BS335
#define U300_SYSCON_CERR_CDS_CLK_EN (0x2000)
#define U300_SYSCON_CERR_ISP_CLK_EN (0x1000)
-#endif
#define U300_SYSCON_CERR_MSPRO_CLK_EN (0x0800)
#define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN (0x0400)
#define U300_SYSCON_CERR_SEMI_CLK_EN (0x0200)
@@ -124,9 +112,7 @@
#define U300_SYSCON_CERR_AAIF_CLK_EN (0x0001)
/* Single block clock enable 16bit (-/W) */
#define U300_SYSCON_SBCER (0x002c)
-#ifdef CONFIG_MACH_U300_BS335
#define U300_SYSCON_SBCER_PPM_CLK_EN (0x0009)
-#endif
#define U300_SYSCON_SBCER_ACC_TMR_CLK_EN (0x0008)
#define U300_SYSCON_SBCER_APP_TMR_CLK_EN (0x0007)
#define U300_SYSCON_SBCER_KEYPAD_CLK_EN (0x0006)
@@ -135,9 +121,7 @@
#define U300_SYSCON_SBCER_BTR_CLK_EN (0x0002)
#define U300_SYSCON_SBCER_UART_CLK_EN (0x0001)
#define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN (0x0000)
-#ifdef CONFIG_MACH_U300_BS335
#define U300_SYSCON_SBCER_UART1_CLK_EN (0x0019)
-#endif
#define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN (0x0018)
#define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN (0x0017)
#define U300_SYSCON_SBCER_SPI_CLK_EN (0x0016)
@@ -147,10 +131,8 @@
#define U300_SYSCON_SBCER_I2C1_CLK_EN (0x0012)
#define U300_SYSCON_SBCER_I2C0_CLK_EN (0x0011)
#define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN (0x0010)
-#ifdef CONFIG_MACH_U300_BS335
#define U300_SYSCON_SBCER_CDS_CLK_EN (0x002D)
#define U300_SYSCON_SBCER_ISP_CLK_EN (0x002C)
-#endif
#define U300_SYSCON_SBCER_MSPRO_CLK_EN (0x002B)
#define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN (0x002A)
#define U300_SYSCON_SBCER_SEMI_CLK_EN (0x0029)
@@ -168,9 +150,7 @@
/* Same values as above for SBCER */
/* Clock force SLOW peripherals 16bit (R/W) */
#define U300_SYSCON_CFSR (0x003c)
-#ifdef CONFIG_MACH_U300_BS335
#define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN (0x0200)
-#endif
#define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN (0x0100)
#define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN (0x0080)
#define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN (0x0020)
@@ -184,10 +164,8 @@
/* Values not defined. Define if you want to use them. */
/* Clock force the rest of the peripherals 16bit (R/W) */
#define U300_SYSCON_CFRR (0x44)
-#ifdef CONFIG_MACH_U300_BS335
#define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN (0x2000)
#define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN (0x1000)
-#endif
#define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN (0x0800)
#define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN (0x0400)
#define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN (0x0200)
diff --git a/arch/arm/mach-u300/include/mach/u300-regs.h b/arch/arm/mach-u300/include/mach/u300-regs.h
index 65f87c5..1e49d90 100644
--- a/arch/arm/mach-u300/include/mach/u300-regs.h
+++ b/arch/arm/mach-u300/include/mach/u300-regs.h
@@ -28,7 +28,6 @@
#define PLAT_NAND_CLE (1 << 16)
#define PLAT_NAND_ALE (1 << 17)
-
/* AHB Peripherals */
#define U300_AHB_PER_PHYS_BASE 0xa0000000
#define U300_AHB_PER_VIRT_BASE 0xff010000
@@ -46,11 +45,7 @@
#define U300_BOOTROM_VIRT_BASE 0xffff0000
/* SEMI config base */
-#ifdef CONFIG_MACH_U300_BS335
#define U300_SEMI_CONFIG_BASE 0x2FFE0000
-#else
-#define U300_SEMI_CONFIG_BASE 0x30000000
-#endif
/*
* AHB peripherals
@@ -99,10 +94,8 @@
/* SPI controller */
#define U300_SPI_BASE (U300_FAST_PER_PHYS_BASE+0x6000)
-#ifdef CONFIG_MACH_U300_BS335
/* Fast UART1 on U335 only */
#define U300_UART1_BASE (U300_SLOW_PER_PHYS_BASE+0x7000)
-#endif
/*
* SLOW peripherals
@@ -151,10 +144,8 @@
* REST peripherals
*/
-/* ISP (image signal processor) is only available in U335 */
-#ifdef CONFIG_MACH_U300_BS335
+/* ISP (image signal processor) */
#define U300_ISP_BASE (0xA0008000)
-#endif
/* DMA Controller base */
#define U300_DMAC_BASE (0xC0020000)
@@ -166,17 +157,9 @@
#define U300_APEX_BASE (0xc0030000)
/* Video Encoder Base */
-#ifdef CONFIG_MACH_U300_BS335
#define U300_VIDEOENC_BASE (0xc0080000)
-#else
-#define U300_VIDEOENC_BASE (0xc0040000)
-#endif
/* XGAM Base */
#define U300_XGAM_BASE (0xd0000000)
-/*
- * Virtual accessor macros for static devices
- */
-
#endif
diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c
index a1affac..02e6659 100644
--- a/arch/arm/mach-u300/spi.c
+++ b/arch/arm/mach-u300/spi.c
@@ -12,7 +12,7 @@
#include <linux/amba/pl022.h>
#include <linux/err.h>
#include <mach/coh901318.h>
-#include <mach/dma_channels.h>
+#include "dma_channels.h"
/*
* The following is for the actual devices on the SSP/SPI bus
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index 56ac06d..1da10e2 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -17,14 +17,17 @@
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/err.h>
+#include <linux/irq.h>
#include <mach/hardware.h>
+#include <mach/irqs.h>
/* Generic stuff */
#include <asm/sched_clock.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
-#include <asm/mach/irq.h>
+
+#include "timer.h"
/*
* APP side special timer registers
diff --git a/arch/arm/mach-u300/timer.h b/arch/arm/mach-u300/timer.h
new file mode 100644
index 0000000..b5e9791
--- /dev/null
+++ b/arch/arm/mach-u300/timer.h
@@ -0,0 +1 @@
+extern struct sys_timer u300_timer;
diff --git a/arch/arm/mach-u300/u300-gpio.h b/arch/arm/mach-u300/u300-gpio.h
index 847dc25..83f50772 100644
--- a/arch/arm/mach-u300/u300-gpio.h
+++ b/arch/arm/mach-u300/u300-gpio.h
@@ -1,50 +1,11 @@
/*
- * Individual pin assignments for the B26/S26. Notice that the
- * actual usage of these pins depends on the PAD MUX settings, that
- * is why the same number can potentially appear several times.
- * In the reference design each pin is only used for one purpose.
- * These were determined by inspecting the B26/S26 schematic:
- * 2/1911-ROA 128 1603
- */
-#ifdef CONFIG_MACH_U300_BS2X
-#define U300_GPIO_PIN_UART_RX 0
-#define U300_GPIO_PIN_UART_TX 1
-#define U300_GPIO_PIN_GPIO02 2 /* Unrouted */
-#define U300_GPIO_PIN_GPIO03 3 /* Unrouted */
-#define U300_GPIO_PIN_CAM_SLEEP 4
-#define U300_GPIO_PIN_CAM_REG_EN 5
-#define U300_GPIO_PIN_GPIO06 6 /* Unrouted */
-#define U300_GPIO_PIN_GPIO07 7 /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO08 8 /* Service point SP2321 */
-#define U300_GPIO_PIN_GPIO09 9 /* Service point SP2322 */
-#define U300_GPIO_PIN_PHFSENSE 10 /* Headphone jack sensing */
-#define U300_GPIO_PIN_MMC_CLKRET 11 /* Clock return from MMC/SD card */
-#define U300_GPIO_PIN_MMC_CD 12 /* MMC Card insertion detection */
-#define U300_GPIO_PIN_FLIPSENSE 13 /* Mechanical flip sensing */
-#define U300_GPIO_PIN_GPIO14 14 /* DSP JTAG Port RTCK */
-#define U300_GPIO_PIN_GPIO15 15 /* Unrouted */
-
-#define U300_GPIO_PIN_GPIO16 16 /* Unrouted */
-#define U300_GPIO_PIN_GPIO17 17 /* Unrouted */
-#define U300_GPIO_PIN_GPIO18 18 /* Unrouted */
-#define U300_GPIO_PIN_GPIO19 19 /* Unrouted */
-#define U300_GPIO_PIN_GPIO20 20 /* Unrouted */
-#define U300_GPIO_PIN_GPIO21 21 /* Unrouted */
-#define U300_GPIO_PIN_GPIO22 22 /* Unrouted */
-#define U300_GPIO_PIN_GPIO23 23 /* Unrouted */
-#endif
-
-/*
- * Individual pin assignments for the B330/S330 and B365/S365.
+ * Individual pin assignments for the B335/S335.
* Notice that the actual usage of these pins depends on the
* PAD MUX settings, that is why the same number can potentially
* appear several times. In the reference design each pin is only
* used for one purpose. These were determined by inspecting the
* S365 schematic.
*/
-#if defined(CONFIG_MACH_U300_BS330) || defined(CONFIG_MACH_U300_BS365) || \
- defined(CONFIG_MACH_U300_BS335)
#define U300_GPIO_PIN_UART_RX 0
#define U300_GPIO_PIN_UART_TX 1
#define U300_GPIO_PIN_UART_CTS 2
@@ -90,8 +51,6 @@
#define U300_GPIO_PIN_GPIO38 38 /* Unrouted */
#define U300_GPIO_PIN_GPIO39 39 /* Unrouted */
-#ifdef CONFIG_MACH_U300_BS335
-
#define U300_GPIO_PIN_GPIO40 40 /* Unrouted */
#define U300_GPIO_PIN_GPIO41 41 /* Unrouted */
#define U300_GPIO_PIN_GPIO42 42 /* Unrouted */
@@ -109,6 +68,3 @@
#define U300_GPIO_PIN_GPIO53 53 /* Unrouted */
#define U300_GPIO_PIN_GPIO54 54 /* Unrouted */
#define U300_GPIO_PIN_GPIO55 55 /* Unrouted */
-#endif
-
-#endif
diff --git a/arch/arm/mach-u300/u300.c b/arch/arm/mach-u300/u300.c
deleted file mode 100644
index f30c69d..0000000
--- a/arch/arm/mach-u300/u300.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- *
- * arch/arm/mach-u300/u300.c
- *
- *
- * Copyright (C) 2006-2009 ST-Ericsson AB
- * License terms: GNU General Public License (GPL) version 2
- * Platform machine definition.
- * Author: Linus Walleij <linus.walleij@stericsson.com>
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/memblock.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/platform.h>
-#include <asm/hardware/vic.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/memory.h>
-
-static void __init u300_init_machine(void)
-{
- u300_init_devices();
-}
-
-#ifdef CONFIG_MACH_U300_BS2X
-#define MACH_U300_STRING "Ericsson AB U300 S25/S26/B25/B26 Prototype Board"
-#endif
-
-#ifdef CONFIG_MACH_U300_BS330
-#define MACH_U300_STRING "Ericsson AB U330 S330/B330 Prototype Board"
-#endif
-
-#ifdef CONFIG_MACH_U300_BS335
-#define MACH_U300_STRING "Ericsson AB U335 S335/B335 Prototype Board"
-#endif
-
-#ifdef CONFIG_MACH_U300_BS365
-#define MACH_U300_STRING "Ericsson AB U365 S365/B365 Prototype Board"
-#endif
-
-MACHINE_START(U300, MACH_U300_STRING)
- /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
- .atag_offset = 0x100,
- .map_io = u300_map_io,
- .init_irq = u300_init_irq,
- .handle_irq = vic_handle_irq,
- .timer = &u300_timer,
- .init_machine = u300_init_machine,
- .restart = u300_restart,
-MACHINE_END
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index db3c52d..3ee761d 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -19,7 +19,6 @@
#include <linux/mfd/abx500/ab8500.h>
#include <asm/mach/map.h>
-#include <asm/pmu.h>
#include <plat/gpio-nomadik.h>
#include <mach/hardware.h>
#include <mach/setup.h>
@@ -122,7 +121,7 @@
static struct platform_device db8500_pmu_device = {
.name = "arm-pmu",
- .id = ARM_PMU_DEVICE_CPU,
+ .id = -1,
.num_resources = ARRAY_SIZE(db8500_pmu_resources),
.resource = db8500_pmu_resources,
.dev.platform_data = &db8500_pmu_platdata,
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index cd8ea35..ca7902c 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -169,11 +169,6 @@
.pfn = __phys_to_pfn(VERSATILE_PCI_CFG_BASE),
.length = VERSATILE_PCI_CFG_BASE_SIZE,
.type = MT_DEVICE
- }, {
- .virtual = (unsigned long)VERSATILE_PCI_VIRT_MEM_BASE0,
- .pfn = __phys_to_pfn(VERSATILE_PCI_MEM_BASE0),
- .length = IO_SPACE_LIMIT,
- .type = MT_DEVICE
},
#endif
};
diff --git a/arch/arm/mach-versatile/include/mach/hardware.h b/arch/arm/mach-versatile/include/mach/hardware.h
index 408e58d..3e5d425 100644
--- a/arch/arm/mach-versatile/include/mach/hardware.h
+++ b/arch/arm/mach-versatile/include/mach/hardware.h
@@ -29,7 +29,6 @@
*/
#define VERSATILE_PCI_VIRT_BASE (void __iomem *)0xe8000000ul
#define VERSATILE_PCI_CFG_VIRT_BASE (void __iomem *)0xe9000000ul
-#define VERSATILE_PCI_VIRT_MEM_BASE0 (void __iomem *)PCIO_BASE
/* macro to get at MMIO space when running virtually */
#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
diff --git a/arch/arm/mach-versatile/include/mach/io.h b/arch/arm/mach-versatile/include/mach/io.h
deleted file mode 100644
index 0406513..0000000
--- a/arch/arm/mach-versatile/include/mach/io.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * arch/arm/mach-versatile/include/mach/io.h
- *
- * Copyright (C) 2003 ARM Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define PCIO_BASE 0xeb000000ul
-
-#define __io(a) ((a) + PCIO_BASE)
-
-#endif
diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c
index e95bf84..2f84f40 100644
--- a/arch/arm/mach-versatile/pci.c
+++ b/arch/arm/mach-versatile/pci.c
@@ -169,13 +169,6 @@
.write = versatile_write_config,
};
-static struct resource io_port = {
- .name = "PCI",
- .start = 0,
- .end = IO_SPACE_LIMIT,
- .flags = IORESOURCE_IO,
-};
-
static struct resource io_mem = {
.name = "PCI I/O space",
.start = VERSATILE_PCI_MEM_BASE0,
@@ -207,12 +200,6 @@
"memory region (%d)\n", ret);
goto out;
}
- ret = request_resource(&ioport_resource, &io_port);
- if (ret) {
- printk(KERN_ERR "PCI: unable to allocate I/O "
- "port region (%d)\n", ret);
- goto out;
- }
ret = request_resource(&iomem_resource, &non_mem);
if (ret) {
printk(KERN_ERR "PCI: unable to allocate non-prefetchable "
@@ -227,11 +214,9 @@
}
/*
- * the IO resource for this bus
* the mem resource for this bus
* the prefetch mem resource for this bus
*/
- pci_add_resource_offset(&sys->resources, &io_port, sys->io_offset);
pci_add_resource_offset(&sys->resources, &non_mem, sys->mem_offset);
pci_add_resource_offset(&sys->resources, &pre_mem, sys->mem_offset);
@@ -260,9 +245,11 @@
goto out;
}
+ ret = pci_ioremap_io(0, VERSATILE_PCI_MEM_BASE0);
+ if (ret)
+ goto out;
+
if (nr == 0) {
- sys->mem_offset = 0;
- sys->io_offset = 0;
ret = pci_versatile_setup_resources(sys);
if (ret < 0) {
printk("pci_versatile_setup: resources... oops?\n");
@@ -319,7 +306,6 @@
void __init pci_versatile_preinit(void)
{
- pcibios_min_io = 0x44000000;
pcibios_min_mem = 0x50000000;
__raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28, PCI_IMAP0);
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index 61c4924..e4073a60 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -13,7 +13,6 @@
#include <asm/hardware/arm_timer.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/hardware/gic.h>
-#include <asm/pmu.h>
#include <asm/smp_scu.h>
#include <asm/smp_twd.h>
@@ -144,7 +143,7 @@
static struct platform_device pmu_device = {
.name = "arm-pmu",
- .id = ARM_PMU_DEVICE_CPU,
+ .id = -1,
.num_resources = ARRAY_SIZE(pmu_resources),
.resource = pmu_resources,
};
diff --git a/arch/arm/mm/ioremap.c b/arch/arm/mm/ioremap.c
index 566750f..9d869f9 100644
--- a/arch/arm/mm/ioremap.c
+++ b/arch/arm/mm/ioremap.c
@@ -36,6 +36,7 @@
#include <asm/system_info.h>
#include <asm/mach/map.h>
+#include <asm/mach/pci.h>
#include "mm.h"
int ioremap_page(unsigned long virt, unsigned long phys,
@@ -383,3 +384,16 @@
arch_iounmap(io_addr);
}
EXPORT_SYMBOL(__arm_iounmap);
+
+#ifdef CONFIG_PCI
+int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr)
+{
+ BUG_ON(offset + SZ_64K > IO_SPACE_LIMIT);
+
+ return ioremap_page_range(PCI_IO_VIRT_BASE + offset,
+ PCI_IO_VIRT_BASE + offset + SZ_64K,
+ phys_addr,
+ __pgprot(get_mem_type(MT_DEVICE)->prot_pte));
+}
+EXPORT_SYMBOL_GPL(pci_ioremap_io);
+#endif
diff --git a/arch/arm/mm/mm.h b/arch/arm/mm/mm.h
index 6776160..a8ee92d 100644
--- a/arch/arm/mm/mm.h
+++ b/arch/arm/mm/mm.h
@@ -55,6 +55,9 @@
/* permanent static mappings from iotable_init() */
#define VM_ARM_STATIC_MAPPING 0x40000000
+/* empty mapping */
+#define VM_ARM_EMPTY_MAPPING 0x20000000
+
/* mapping type (attributes) for permanent static mappings */
#define VM_ARM_MTYPE(mt) ((mt) << 20)
#define VM_ARM_MTYPE_MASK (0x1f << 20)
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 4c2d045..a7a9e41 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -31,6 +31,7 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
+#include <asm/mach/pci.h>
#include "mm.h"
@@ -216,7 +217,7 @@
.prot_l1 = PMD_TYPE_TABLE,
.prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
.domain = DOMAIN_IO,
- },
+ },
[MT_DEVICE_WC] = { /* ioremap_wc */
.prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
.prot_l1 = PMD_TYPE_TABLE,
@@ -777,14 +778,27 @@
create_mapping(md);
vm->addr = (void *)(md->virtual & PAGE_MASK);
vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
- vm->phys_addr = __pfn_to_phys(md->pfn);
- vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
+ vm->phys_addr = __pfn_to_phys(md->pfn);
+ vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
vm->flags |= VM_ARM_MTYPE(md->type);
vm->caller = iotable_init;
vm_area_add_early(vm++);
}
}
+void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
+ void *caller)
+{
+ struct vm_struct *vm;
+
+ vm = early_alloc_aligned(sizeof(*vm), __alignof__(*vm));
+ vm->addr = (void *)addr;
+ vm->size = size;
+ vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
+ vm->caller = caller;
+ vm_area_add_early(vm);
+}
+
#ifndef CONFIG_ARM_LPAE
/*
@@ -802,14 +816,7 @@
static void __init pmd_empty_section_gap(unsigned long addr)
{
- struct vm_struct *vm;
-
- vm = early_alloc_aligned(sizeof(*vm), __alignof__(*vm));
- vm->addr = (void *)addr;
- vm->size = SECTION_SIZE;
- vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
- vm->caller = pmd_empty_section_gap;
- vm_area_add_early(vm);
+ vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
}
static void __init fill_pmd_gaps(void)
@@ -820,7 +827,7 @@
/* we're still single threaded hence no lock needed here */
for (vm = vmlist; vm; vm = vm->next) {
- if (!(vm->flags & VM_ARM_STATIC_MAPPING))
+ if (!(vm->flags & (VM_ARM_STATIC_MAPPING | VM_ARM_EMPTY_MAPPING)))
continue;
addr = (unsigned long)vm->addr;
if (addr < next)
@@ -858,6 +865,28 @@
#define fill_pmd_gaps() do { } while (0)
#endif
+#if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
+static void __init pci_reserve_io(void)
+{
+ struct vm_struct *vm;
+ unsigned long addr;
+
+ /* we're still single threaded hence no lock needed here */
+ for (vm = vmlist; vm; vm = vm->next) {
+ if (!(vm->flags & VM_ARM_STATIC_MAPPING))
+ continue;
+ addr = (unsigned long)vm->addr;
+ addr &= ~(SZ_2M - 1);
+ if (addr == PCI_IO_VIRT_BASE)
+ return;
+
+ }
+ vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
+}
+#else
+#define pci_reserve_io() do { } while (0)
+#endif
+
static void * __initdata vmalloc_min =
(void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
@@ -1141,6 +1170,9 @@
mdesc->map_io();
fill_pmd_gaps();
+ /* Reserve fixed i/o space in VMALLOC region */
+ pci_reserve_io();
+
/*
* Finally flush the caches and tlb to ensure that we're in a
* consistent state wrt the writebuffer. This also ensures that
diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c
index 8daae9b..362474b 100644
--- a/arch/arm/plat-iop/pci.c
+++ b/arch/arm/plat-iop/pci.c
@@ -192,30 +192,24 @@
if (nr != 0)
return 0;
- res = kzalloc(2 * sizeof(struct resource), GFP_KERNEL);
+ res = kzalloc(sizeof(struct resource), GFP_KERNEL);
if (!res)
panic("PCI: unable to alloc resources");
- res[0].start = IOP3XX_PCI_LOWER_IO_PA;
- res[0].end = IOP3XX_PCI_LOWER_IO_PA + IOP3XX_PCI_IO_WINDOW_SIZE - 1;
- res[0].name = "IOP3XX PCI I/O Space";
- res[0].flags = IORESOURCE_IO;
- request_resource(&ioport_resource, &res[0]);
-
- res[1].start = IOP3XX_PCI_LOWER_MEM_PA;
- res[1].end = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE - 1;
- res[1].name = "IOP3XX PCI Memory Space";
- res[1].flags = IORESOURCE_MEM;
- request_resource(&iomem_resource, &res[1]);
+ res->start = IOP3XX_PCI_LOWER_MEM_PA;
+ res->end = IOP3XX_PCI_LOWER_MEM_PA + IOP3XX_PCI_MEM_WINDOW_SIZE - 1;
+ res->name = "IOP3XX PCI Memory Space";
+ res->flags = IORESOURCE_MEM;
+ request_resource(&iomem_resource, res);
/*
* Use whatever translation is already setup.
*/
sys->mem_offset = IOP3XX_PCI_LOWER_MEM_PA - *IOP3XX_OMWTVR0;
- sys->io_offset = IOP3XX_PCI_LOWER_IO_PA - *IOP3XX_OIOWTVR;
- pci_add_resource_offset(&sys->resources, &res[0], sys->io_offset);
- pci_add_resource_offset(&sys->resources, &res[1], sys->mem_offset);
+ pci_add_resource_offset(&sys->resources, res, sys->mem_offset);
+
+ pci_ioremap_io(0, IOP3XX_PCI_LOWER_IO_PA);
return 1;
}
@@ -367,7 +361,6 @@
void __init iop3xx_pci_preinit(void)
{
- pcibios_min_io = 0;
pcibios_min_mem = 0;
iop3xx_atu_disable();
diff --git a/arch/arm/plat-iop/pmu.c b/arch/arm/plat-iop/pmu.c
index a2024b8..ad9f974 100644
--- a/arch/arm/plat-iop/pmu.c
+++ b/arch/arm/plat-iop/pmu.c
@@ -9,7 +9,6 @@
*/
#include <linux/platform_device.h>
-#include <asm/pmu.h>
#include <mach/irqs.h>
static struct resource pmu_resource = {
@@ -26,7 +25,7 @@
static struct platform_device pmu_device = {
.name = "arm-pmu",
- .id = ARM_PMU_DEVICE_CPU,
+ .id = -1,
.resource = &pmu_resource,
.num_resources = 1,
};
diff --git a/arch/arm/plat-iop/setup.c b/arch/arm/plat-iop/setup.c
index bade586..5b217f4 100644
--- a/arch/arm/plat-iop/setup.c
+++ b/arch/arm/plat-iop/setup.c
@@ -25,11 +25,6 @@
.pfn = __phys_to_pfn(IOP3XX_PERIPHERAL_PHYS_BASE),
.length = IOP3XX_PERIPHERAL_SIZE,
.type = MT_UNCACHED,
- }, { /* PCI IO space */
- .virtual = IOP3XX_PCI_LOWER_IO_VA,
- .pfn = __phys_to_pfn(IOP3XX_PCI_LOWER_IO_PA),
- .length = IOP3XX_PCI_IO_WINDOW_SIZE,
- .type = MT_DEVICE,
},
};
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 6ac7200..149237e2 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -3,7 +3,7 @@
#
# Common support
-obj-y := clock.o time.o devices.o cpu.o system.o irq-common.o
+obj-y := time.o devices.o cpu.o system.o irq-common.o
obj-$(CONFIG_MXC_TZIC) += tzic.o
obj-$(CONFIG_MXC_AVIC) += avic.o
diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
deleted file mode 100644
index 5079787..0000000
--- a/arch/arm/plat-mxc/clock.c
+++ /dev/null
@@ -1,257 +0,0 @@
-/*
- * Based on arch/arm/plat-omap/clock.c
- *
- * Copyright (C) 2004 - 2005 Nokia corporation
- * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
- * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
- * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-/* #define DEBUG */
-
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <linux/list.h>
-#include <linux/module.h>
-#include <linux/mutex.h>
-#include <linux/platform_device.h>
-#include <linux/proc_fs.h>
-#include <linux/semaphore.h>
-#include <linux/string.h>
-
-#include <mach/clock.h>
-#include <mach/hardware.h>
-
-#ifndef CONFIG_COMMON_CLK
-static LIST_HEAD(clocks);
-static DEFINE_MUTEX(clocks_mutex);
-
-/*-------------------------------------------------------------------------
- * Standard clock functions defined in include/linux/clk.h
- *-------------------------------------------------------------------------*/
-
-static void __clk_disable(struct clk *clk)
-{
- if (clk == NULL || IS_ERR(clk))
- return;
- WARN_ON(!clk->usecount);
-
- if (!(--clk->usecount)) {
- if (clk->disable)
- clk->disable(clk);
- __clk_disable(clk->parent);
- __clk_disable(clk->secondary);
- }
-}
-
-static int __clk_enable(struct clk *clk)
-{
- if (clk == NULL || IS_ERR(clk))
- return -EINVAL;
-
- if (clk->usecount++ == 0) {
- __clk_enable(clk->parent);
- __clk_enable(clk->secondary);
-
- if (clk->enable)
- clk->enable(clk);
- }
- return 0;
-}
-
-/* This function increments the reference count on the clock and enables the
- * clock if not already enabled. The parent clock tree is recursively enabled
- */
-int clk_enable(struct clk *clk)
-{
- int ret = 0;
-
- if (clk == NULL || IS_ERR(clk))
- return -EINVAL;
-
- mutex_lock(&clocks_mutex);
- ret = __clk_enable(clk);
- mutex_unlock(&clocks_mutex);
-
- return ret;
-}
-EXPORT_SYMBOL(clk_enable);
-
-/* This function decrements the reference count on the clock and disables
- * the clock when reference count is 0. The parent clock tree is
- * recursively disabled
- */
-void clk_disable(struct clk *clk)
-{
- if (clk == NULL || IS_ERR(clk))
- return;
-
- mutex_lock(&clocks_mutex);
- __clk_disable(clk);
- mutex_unlock(&clocks_mutex);
-}
-EXPORT_SYMBOL(clk_disable);
-
-/* Retrieve the *current* clock rate. If the clock itself
- * does not provide a special calculation routine, ask
- * its parent and so on, until one is able to return
- * a valid clock rate
- */
-unsigned long clk_get_rate(struct clk *clk)
-{
- if (clk == NULL || IS_ERR(clk))
- return 0UL;
-
- if (clk->get_rate)
- return clk->get_rate(clk);
-
- return clk_get_rate(clk->parent);
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-/* Round the requested clock rate to the nearest supported
- * rate that is less than or equal to the requested rate.
- * This is dependent on the clock's current parent.
- */
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
- if (clk == NULL || IS_ERR(clk) || !clk->round_rate)
- return 0;
-
- return clk->round_rate(clk, rate);
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-/* Set the clock to the requested clock rate. The rate must
- * match a supported rate exactly based on what clk_round_rate returns
- */
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret = -EINVAL;
-
- if (clk == NULL || IS_ERR(clk) || clk->set_rate == NULL || rate == 0)
- return ret;
-
- mutex_lock(&clocks_mutex);
- ret = clk->set_rate(clk, rate);
- mutex_unlock(&clocks_mutex);
-
- return ret;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-/* Set the clock's parent to another clock source */
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
- int ret = -EINVAL;
- struct clk *old;
-
- if (clk == NULL || IS_ERR(clk) || parent == NULL ||
- IS_ERR(parent) || clk->set_parent == NULL)
- return ret;
-
- if (clk->usecount)
- clk_enable(parent);
-
- mutex_lock(&clocks_mutex);
- ret = clk->set_parent(clk, parent);
- if (ret == 0) {
- old = clk->parent;
- clk->parent = parent;
- } else {
- old = parent;
- }
- mutex_unlock(&clocks_mutex);
-
- if (clk->usecount)
- clk_disable(old);
-
- return ret;
-}
-EXPORT_SYMBOL(clk_set_parent);
-
-/* Retrieve the clock's parent clock source */
-struct clk *clk_get_parent(struct clk *clk)
-{
- struct clk *ret = NULL;
-
- if (clk == NULL || IS_ERR(clk))
- return ret;
-
- return clk->parent;
-}
-EXPORT_SYMBOL(clk_get_parent);
-
-#else
-
-/*
- * Lock to protect the clock module (ccm) registers. Used
- * on all i.MXs
- */
-DEFINE_SPINLOCK(imx_ccm_lock);
-
-#endif /* CONFIG_COMMON_CLK */
-
-/*
- * Get the resulting clock rate from a PLL register value and the input
- * frequency. PLLs with this register layout can at least be found on
- * MX1, MX21, MX27 and MX31
- *
- * mfi + mfn / (mfd + 1)
- * f = 2 * f_ref * --------------------
- * pd + 1
- */
-unsigned long mxc_decode_pll(unsigned int reg_val, u32 freq)
-{
- long long ll;
- int mfn_abs;
- unsigned int mfi, mfn, mfd, pd;
-
- mfi = (reg_val >> 10) & 0xf;
- mfn = reg_val & 0x3ff;
- mfd = (reg_val >> 16) & 0x3ff;
- pd = (reg_val >> 26) & 0xf;
-
- mfi = mfi <= 5 ? 5 : mfi;
-
- mfn_abs = mfn;
-
- /* On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
- * 2's complements number
- */
- if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
- mfn_abs = 0x400 - mfn;
-
- freq *= 2;
- freq /= pd + 1;
-
- ll = (unsigned long long)freq * mfn_abs;
-
- do_div(ll, mfd + 1);
-
- if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
- ll = -ll;
-
- ll = (freq * mfi) + ll;
-
- return ll;
-}
diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c
index 73db34b..b5b6f80 100644
--- a/arch/arm/plat-mxc/cpufreq.c
+++ b/arch/arm/plat-mxc/cpufreq.c
@@ -23,7 +23,6 @@
#include <linux/err.h>
#include <linux/slab.h>
#include <mach/hardware.h>
-#include <mach/clock.h>
#define CLK32_FREQ 32768
#define NANOSECOND (1000 * 1000 * 1000)
diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c
index 2020d84..d390f00 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-uart.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c
@@ -87,7 +87,7 @@
#ifdef CONFIG_SOC_IMX35
const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = {
#define imx35_imx_uart_data_entry(_id, _hwid) \
- imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_16K)
+ imx_imx_uart_1irq_data_entry(MX35, _id, _hwid, SZ_16K)
imx35_imx_uart_data_entry(0, 1),
imx35_imx_uart_data_entry(1, 2),
imx35_imx_uart_data_entry(2, 3),
diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h
deleted file mode 100644
index bd940c7..0000000
--- a/arch/arm/plat-mxc/include/mach/clock.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#ifndef __ASM_ARCH_MXC_CLOCK_H__
-#define __ASM_ARCH_MXC_CLOCK_H__
-
-#ifndef __ASSEMBLY__
-#include <linux/list.h>
-
-#ifndef CONFIG_COMMON_CLK
-struct module;
-
-struct clk {
- int id;
- /* Source clock this clk depends on */
- struct clk *parent;
- /* Secondary clock to enable/disable with this clock */
- struct clk *secondary;
- /* Reference count of clock enable/disable */
- __s8 usecount;
- /* Register bit position for clock's enable/disable control. */
- u8 enable_shift;
- /* Register address for clock's enable/disable control. */
- void __iomem *enable_reg;
- u32 flags;
- /* get the current clock rate (always a fresh value) */
- unsigned long (*get_rate) (struct clk *);
- /* Function ptr to set the clock to a new rate. The rate must match a
- supported rate returned from round_rate. Leave blank if clock is not
- programmable */
- int (*set_rate) (struct clk *, unsigned long);
- /* Function ptr to round the requested clock rate to the nearest
- supported rate that is less than or equal to the requested rate. */
- unsigned long (*round_rate) (struct clk *, unsigned long);
- /* Function ptr to enable the clock. Leave blank if clock can not
- be gated. */
- int (*enable) (struct clk *);
- /* Function ptr to disable the clock. Leave blank if clock can not
- be gated. */
- void (*disable) (struct clk *);
- /* Function ptr to set the parent clock of the clock. */
- int (*set_parent) (struct clk *, struct clk *);
-};
-
-int clk_register(struct clk *clk);
-void clk_unregister(struct clk *clk);
-#endif /* CONFIG_COMMON_CLK */
-
-extern spinlock_t imx_ccm_lock;
-
-unsigned long mxc_decode_pll(unsigned int pll, u32 f_ref);
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ASM_ARCH_MXC_CLOCK_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx2_cam.h b/arch/arm/plat-mxc/include/mach/mx2_cam.h
index 3c080a3..7ded6f1 100644
--- a/arch/arm/plat-mxc/include/mach/mx2_cam.h
+++ b/arch/arm/plat-mxc/include/mach/mx2_cam.h
@@ -23,7 +23,6 @@
#ifndef __MACH_MX2_CAM_H_
#define __MACH_MX2_CAM_H_
-#define MX2_CAMERA_SWAP16 (1 << 0)
#define MX2_CAMERA_EXT_VSYNC (1 << 1)
#define MX2_CAMERA_CCIR (1 << 2)
#define MX2_CAMERA_CCIR_INTERLACE (1 << 3)
@@ -31,7 +30,6 @@
#define MX2_CAMERA_GATED_CLOCK (1 << 5)
#define MX2_CAMERA_INV_DATA (1 << 6)
#define MX2_CAMERA_PCLK_SAMPLE_RISING (1 << 7)
-#define MX2_CAMERA_PACK_DIR_MSB (1 << 8)
/**
* struct mx2_camera_platform_data - optional platform data for mx2_camera
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index 1996c3e..3da78cf 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -21,7 +21,6 @@
#include <linux/io.h>
#include <linux/err.h>
#include <linux/delay.h>
-#include <linux/module.h>
#include <mach/hardware.h>
#include <mach/common.h>
@@ -29,9 +28,6 @@
#include <asm/proc-fns.h>
#include <asm/mach-types.h>
-void __iomem *(*imx_ioremap)(unsigned long, size_t, unsigned int) = NULL;
-EXPORT_SYMBOL_GPL(imx_ioremap);
-
static void __iomem *wdog_base;
/*
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index 6dcad58..c76ed8b 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -968,8 +968,7 @@
l = p->dma_read(CCR, lch);
}
if (i >= 100)
- printk(KERN_ERR "DMA drain did not complete on "
- "lch %d\n", lch);
+ pr_err("DMA drain did not complete on lch %d\n", lch);
/* Restore OCP_SYSCONFIG */
p->dma_write(sys_cf, OCP_SYSCONFIG, lch);
} else {
@@ -1153,8 +1152,7 @@
if ((dma_chan[lch_head].dev_id == -1) ||
(dma_chan[lch_queue].dev_id == -1)) {
- printk(KERN_ERR "omap_dma: trying to link "
- "non requested channels\n");
+ pr_err("omap_dma: trying to link non requested channels\n");
dump_stack();
}
@@ -1180,15 +1178,13 @@
if (dma_chan[lch_head].next_lch != lch_queue ||
dma_chan[lch_head].next_lch == -1) {
- printk(KERN_ERR "omap_dma: trying to unlink "
- "non linked channels\n");
+ pr_err("omap_dma: trying to unlink non linked channels\n");
dump_stack();
}
if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
(dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
- printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
- "before unlinking\n");
+ pr_err("omap_dma: You need to stop the DMA channels before unlinking\n");
dump_stack();
}
@@ -1830,16 +1826,15 @@
if ((csr & 0x3f) == 0)
return 0;
if (unlikely(dma_chan[ch].dev_id == -1)) {
- printk(KERN_WARNING "Spurious interrupt from DMA channel "
- "%d (CSR %04x)\n", ch, csr);
+ pr_warn("Spurious interrupt from DMA channel %d (CSR %04x)\n",
+ ch, csr);
return 0;
}
if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
- printk(KERN_WARNING "DMA timeout with device %d\n",
- dma_chan[ch].dev_id);
+ pr_warn("DMA timeout with device %d\n", dma_chan[ch].dev_id);
if (unlikely(csr & OMAP_DMA_DROP_IRQ))
- printk(KERN_WARNING "DMA synchronization event drop occurred "
- "with device %d\n", dma_chan[ch].dev_id);
+ pr_warn("DMA synchronization event drop occurred with device %d\n",
+ dma_chan[ch].dev_id);
if (likely(csr & OMAP_DMA_BLOCK_IRQ))
dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
if (likely(dma_chan[ch].callback != NULL))
@@ -1879,21 +1874,19 @@
if (!status) {
if (printk_ratelimit())
- printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
- ch);
+ pr_warn("Spurious DMA IRQ for lch %d\n", ch);
p->dma_write(1 << ch, IRQSTATUS_L0, ch);
return 0;
}
if (unlikely(dma_chan[ch].dev_id == -1)) {
if (printk_ratelimit())
- printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
- "channel %d\n", status, ch);
+ pr_warn("IRQ %04x for non-allocated DMA channel %d\n",
+ status, ch);
return 0;
}
if (unlikely(status & OMAP_DMA_DROP_IRQ))
- printk(KERN_INFO
- "DMA synchronization event drop occurred with device "
- "%d\n", dma_chan[ch].dev_id);
+ pr_info("DMA synchronization event drop occurred with device %d\n",
+ dma_chan[ch].dev_id);
if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
printk(KERN_INFO "DMA transaction error with device %d\n",
dma_chan[ch].dev_id);
@@ -2013,8 +2006,9 @@
p = pdev->dev.platform_data;
if (!p) {
- dev_err(&pdev->dev, "%s: System DMA initialized without"
- "platform data\n", __func__);
+ dev_err(&pdev->dev,
+ "%s: System DMA initialized without platform data\n",
+ __func__);
return -EINVAL;
}
@@ -2089,8 +2083,8 @@
}
ret = setup_irq(dma_irq, &omap24xx_dma_irq);
if (ret) {
- dev_err(&pdev->dev, "set_up failed for IRQ %d"
- "for DMA (error %d)\n", dma_irq, ret);
+ dev_err(&pdev->dev, "set_up failed for IRQ %d for DMA (error %d)\n",
+ dma_irq, ret);
goto exit_dma_lch_fail;
}
}
@@ -2098,8 +2092,7 @@
/* reserve dma channels 0 and 1 in high security devices */
if (cpu_is_omap34xx() &&
(omap_type() != OMAP2_DEVICE_TYPE_GP)) {
- printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
- "HS ROM code\n");
+ pr_info("Reserving DMA channels 0 and 1 for HS ROM code\n");
dma_chan[0].dev_id = 0;
dma_chan[1].dev_id = 1;
}
@@ -2107,8 +2100,8 @@
return 0;
exit_dma_irq_fail:
- dev_err(&pdev->dev, "unable to request IRQ %d"
- "for DMA (error %d)\n", dma_irq, ret);
+ dev_err(&pdev->dev, "unable to request IRQ %d for DMA (error %d)\n",
+ dma_irq, ret);
for (irq_rel = 0; irq_rel < ch; irq_rel++) {
dma_irq = platform_get_irq(pdev, irq_rel);
free_irq(dma_irq, (void *)(irq_rel + 1));
diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c
index cff8712..fd0d3aa 100644
--- a/arch/arm/plat-omap/mux.c
+++ b/arch/arm/plat-omap/mux.c
@@ -76,7 +76,7 @@
return -ENODEV;
}
- reg = (struct pin_config *)&mux_cfg->pins[index];
+ reg = &mux_cfg->pins[index];
if (!mux_cfg->cfg_reg)
return -ENODEV;
diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/plat-omap/omap-pm-noop.c
index 5a97b4d..9f641332 100644
--- a/arch/arm/plat-omap/omap-pm-noop.c
+++ b/arch/arm/plat-omap/omap-pm-noop.c
@@ -41,11 +41,11 @@
};
if (t == -1)
- pr_debug("OMAP PM: remove max MPU wakeup latency constraint: "
- "dev %s\n", dev_name(dev));
+ pr_debug("OMAP PM: remove max MPU wakeup latency constraint: dev %s\n",
+ dev_name(dev));
else
- pr_debug("OMAP PM: add max MPU wakeup latency constraint: "
- "dev %s, t = %ld usec\n", dev_name(dev), t);
+ pr_debug("OMAP PM: add max MPU wakeup latency constraint: dev %s, t = %ld usec\n",
+ dev_name(dev), t);
/*
* For current Linux, this needs to map the MPU to a
@@ -70,11 +70,10 @@
};
if (r == 0)
- pr_debug("OMAP PM: remove min bus tput constraint: "
- "dev %s for agent_id %d\n", dev_name(dev), agent_id);
+ pr_debug("OMAP PM: remove min bus tput constraint: dev %s for agent_id %d\n",
+ dev_name(dev), agent_id);
else
- pr_debug("OMAP PM: add min bus tput constraint: "
- "dev %s for agent_id %d: rate %ld KiB\n",
+ pr_debug("OMAP PM: add min bus tput constraint: dev %s for agent_id %d: rate %ld KiB\n",
dev_name(dev), agent_id, r);
/*
@@ -97,11 +96,11 @@
};
if (t == -1)
- pr_debug("OMAP PM: remove max device latency constraint: "
- "dev %s\n", dev_name(dev));
+ pr_debug("OMAP PM: remove max device latency constraint: dev %s\n",
+ dev_name(dev));
else
- pr_debug("OMAP PM: add max device latency constraint: "
- "dev %s, t = %ld usec\n", dev_name(dev), t);
+ pr_debug("OMAP PM: add max device latency constraint: dev %s, t = %ld usec\n",
+ dev_name(dev), t);
/*
* For current Linux, this needs to map the device to a
@@ -127,11 +126,11 @@
};
if (t == -1)
- pr_debug("OMAP PM: remove max DMA latency constraint: "
- "dev %s\n", dev_name(dev));
+ pr_debug("OMAP PM: remove max DMA latency constraint: dev %s\n",
+ dev_name(dev));
else
- pr_debug("OMAP PM: add max DMA latency constraint: "
- "dev %s, t = %ld usec\n", dev_name(dev), t);
+ pr_debug("OMAP PM: add max DMA latency constraint: dev %s, t = %ld usec\n",
+ dev_name(dev), t);
/*
* For current Linux PM QOS params, this code should scan the
@@ -156,11 +155,11 @@
}
if (r == 0)
- pr_debug("OMAP PM: remove min clk rate constraint: "
- "dev %s\n", dev_name(dev));
+ pr_debug("OMAP PM: remove min clk rate constraint: dev %s\n",
+ dev_name(dev));
else
- pr_debug("OMAP PM: add min clk rate constraint: "
- "dev %s, rate = %ld Hz\n", dev_name(dev), r);
+ pr_debug("OMAP PM: add min clk rate constraint: dev %s, rate = %ld Hz\n",
+ dev_name(dev), r);
/*
* Code in a real implementation should keep track of these
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index c490240..b59edb0 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -1,4 +1,3 @@
-
/*
* omap_device implementation
*
@@ -153,21 +152,19 @@
act_lat = timespec_to_ns(&c);
dev_dbg(&od->pdev->dev,
- "omap_device: pm_lat %d: activate: elapsed time "
- "%llu nsec\n", od->pm_lat_level, act_lat);
+ "omap_device: pm_lat %d: activate: elapsed time %llu nsec\n",
+ od->pm_lat_level, act_lat);
if (act_lat > odpl->activate_lat) {
odpl->activate_lat_worst = act_lat;
if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
odpl->activate_lat = act_lat;
dev_dbg(&od->pdev->dev,
- "new worst case activate latency "
- "%d: %llu\n",
+ "new worst case activate latency %d: %llu\n",
od->pm_lat_level, act_lat);
} else
dev_warn(&od->pdev->dev,
- "activate latency %d "
- "higher than exptected. (%llu > %d)\n",
+ "activate latency %d higher than expected. (%llu > %d)\n",
od->pm_lat_level, act_lat,
odpl->activate_lat);
}
@@ -220,21 +217,19 @@
deact_lat = timespec_to_ns(&c);
dev_dbg(&od->pdev->dev,
- "omap_device: pm_lat %d: deactivate: elapsed time "
- "%llu nsec\n", od->pm_lat_level, deact_lat);
+ "omap_device: pm_lat %d: deactivate: elapsed time %llu nsec\n",
+ od->pm_lat_level, deact_lat);
if (deact_lat > odpl->deactivate_lat) {
odpl->deactivate_lat_worst = deact_lat;
if (odpl->flags & OMAP_DEVICE_LATENCY_AUTO_ADJUST) {
odpl->deactivate_lat = deact_lat;
dev_dbg(&od->pdev->dev,
- "new worst case deactivate latency "
- "%d: %llu\n",
+ "new worst case deactivate latency %d: %llu\n",
od->pm_lat_level, deact_lat);
} else
dev_warn(&od->pdev->dev,
- "deactivate latency %d "
- "higher than exptected. (%llu > %d)\n",
+ "deactivate latency %d higher than expected. (%llu > %d)\n",
od->pm_lat_level, deact_lat,
odpl->deactivate_lat);
}
@@ -449,8 +444,8 @@
for (i = 0; i < od->hwmods_cnt; i++)
c += omap_hwmod_count_resources(od->hwmods[i]);
- pr_debug("omap_device: %s: counted %d total resources across %d "
- "hwmods\n", od->pdev->name, c, od->hwmods_cnt);
+ pr_debug("omap_device: %s: counted %d total resources across %d hwmods\n",
+ od->pdev->name, c, od->hwmods_cnt);
return c;
}
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index fc49f3d..6ff45d5 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -35,7 +35,6 @@
#include <media/s5p_hdmi.h>
#include <asm/irq.h>
-#include <asm/pmu.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
@@ -1132,7 +1131,7 @@
static struct platform_device s5p_device_pmu = {
.name = "arm-pmu",
- .id = ARM_PMU_DEVICE_CPU,
+ .id = -1,
.num_resources = ARRAY_SIZE(s5p_pmu_resource),
.resource = s5p_pmu_resource,
};
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 2997e56..7bc7948 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -158,7 +158,6 @@
stargate2 MACH_STARGATE2 STARGATE2 774
intelmote2 MACH_INTELMOTE2 INTELMOTE2 775
trizeps4 MACH_TRIZEPS4 TRIZEPS4 776
-pnx4008 MACH_PNX4008 PNX4008 782
cpuat91 MACH_CPUAT91 CPUAT91 787
iq81340sc MACH_IQ81340SC IQ81340SC 799
iq81340mc MACH_IQ81340MC IQ81340MC 801
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 5869ea3..d4c7253 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -10,6 +10,7 @@
obj-$(CONFIG_PLAT_SPEAR) += spear/
obj-$(CONFIG_ARCH_U300) += clk-u300.o
obj-$(CONFIG_ARCH_INTEGRATOR) += versatile/
+obj-$(CONFIG_ARCH_PRIMA2) += clk-prima2.o
# Chip specific
obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
diff --git a/drivers/clk/clk-prima2.c b/drivers/clk/clk-prima2.c
new file mode 100644
index 0000000..517874fa
--- /dev/null
+++ b/drivers/clk/clk-prima2.c
@@ -0,0 +1,1171 @@
+/*
+ * Clock tree for CSR SiRFprimaII
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/module.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+#include <linux/syscore_ops.h>
+
+#define SIRFSOC_CLKC_CLK_EN0 0x0000
+#define SIRFSOC_CLKC_CLK_EN1 0x0004
+#define SIRFSOC_CLKC_REF_CFG 0x0014
+#define SIRFSOC_CLKC_CPU_CFG 0x0018
+#define SIRFSOC_CLKC_MEM_CFG 0x001c
+#define SIRFSOC_CLKC_SYS_CFG 0x0020
+#define SIRFSOC_CLKC_IO_CFG 0x0024
+#define SIRFSOC_CLKC_DSP_CFG 0x0028
+#define SIRFSOC_CLKC_GFX_CFG 0x002c
+#define SIRFSOC_CLKC_MM_CFG 0x0030
+#define SIRFSOC_CLKC_LCD_CFG 0x0034
+#define SIRFSOC_CLKC_MMC_CFG 0x0038
+#define SIRFSOC_CLKC_PLL1_CFG0 0x0040
+#define SIRFSOC_CLKC_PLL2_CFG0 0x0044
+#define SIRFSOC_CLKC_PLL3_CFG0 0x0048
+#define SIRFSOC_CLKC_PLL1_CFG1 0x004c
+#define SIRFSOC_CLKC_PLL2_CFG1 0x0050
+#define SIRFSOC_CLKC_PLL3_CFG1 0x0054
+#define SIRFSOC_CLKC_PLL1_CFG2 0x0058
+#define SIRFSOC_CLKC_PLL2_CFG2 0x005c
+#define SIRFSOC_CLKC_PLL3_CFG2 0x0060
+#define SIRFSOC_USBPHY_PLL_CTRL 0x0008
+#define SIRFSOC_USBPHY_PLL_POWERDOWN BIT(1)
+#define SIRFSOC_USBPHY_PLL_BYPASS BIT(2)
+#define SIRFSOC_USBPHY_PLL_LOCK BIT(3)
+
+static void *sirfsoc_clk_vbase, *sirfsoc_rsc_vbase;
+
+#define KHZ 1000
+#define MHZ (KHZ * KHZ)
+
+/*
+ * SiRFprimaII clock controller
+ * - 2 oscillators: osc-26MHz, rtc-32.768KHz
+ * - 3 standard configurable plls: pll1, pll2 & pll3
+ * - 2 exclusive plls: usb phy pll and sata phy pll
+ * - 8 clock domains: cpu/cpudiv, mem/memdiv, sys/io, dsp, graphic, multimedia,
+ * display and sdphy.
+ * Each clock domain can select its own clock source from five clock sources,
+ * X_XIN, X_XINW, PLL1, PLL2 and PLL3. The domain clock is used as the source
+ * clock of the group clock.
+ * - dsp domain: gps, mf
+ * - io domain: dmac, nand, audio, uart, i2c, spi, usp, pwm, pulse
+ * - sys domain: security
+ */
+
+struct clk_pll {
+ struct clk_hw hw;
+ unsigned short regofs; /* register offset */
+};
+
+#define to_pllclk(_hw) container_of(_hw, struct clk_pll, hw)
+
+struct clk_dmn {
+ struct clk_hw hw;
+ signed char enable_bit; /* enable bit: 0 ~ 63 */
+ unsigned short regofs; /* register offset */
+};
+
+#define to_dmnclk(_hw) container_of(_hw, struct clk_dmn, hw)
+
+struct clk_std {
+ struct clk_hw hw;
+ signed char enable_bit; /* enable bit: 0 ~ 63 */
+};
+
+#define to_stdclk(_hw) container_of(_hw, struct clk_std, hw)
+
+static int std_clk_is_enabled(struct clk_hw *hw);
+static int std_clk_enable(struct clk_hw *hw);
+static void std_clk_disable(struct clk_hw *hw);
+
+static inline unsigned long clkc_readl(unsigned reg)
+{
+ return readl(sirfsoc_clk_vbase + reg);
+}
+
+static inline void clkc_writel(u32 val, unsigned reg)
+{
+ writel(val, sirfsoc_clk_vbase + reg);
+}
+
+/*
+ * std pll
+ */
+
+static unsigned long pll_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ unsigned long fin = parent_rate;
+ struct clk_pll *clk = to_pllclk(hw);
+ u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 -
+ SIRFSOC_CLKC_PLL1_CFG0;
+
+ if (clkc_readl(regcfg2) & BIT(2)) {
+ /* pll bypass mode */
+ return fin;
+ } else {
+ /* fout = fin * nf / nr / od */
+ u32 cfg0 = clkc_readl(clk->regofs);
+ u32 nf = (cfg0 & (BIT(13) - 1)) + 1;
+ u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1;
+ u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1;
+ WARN_ON(fin % MHZ);
+ return fin / MHZ * nf / nr / od * MHZ;
+ }
+}
+
+static long pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ unsigned long fin, nf, nr, od;
+
+ /*
+ * fout = fin * nf / (nr * od);
+ * set od = 1, nr = fin/MHz, so fout = nf * MHz
+ */
+ rate = rate - rate % MHZ;
+
+ nf = rate / MHZ;
+ if (nf > BIT(13))
+ nf = BIT(13);
+ if (nf < 1)
+ nf = 1;
+
+ fin = *parent_rate;
+
+ nr = fin / MHZ;
+ if (nr > BIT(6))
+ nr = BIT(6);
+ od = 1;
+
+ return fin * nf / (nr * od);
+}
+
+static int pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_pll *clk = to_pllclk(hw);
+ unsigned long fin, nf, nr, od, reg;
+
+ /*
+ * fout = fin * nf / (nr * od);
+ * set od = 1, nr = fin/MHz, so fout = nf * MHz
+ */
+
+ nf = rate / MHZ;
+ if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1))
+ return -EINVAL;
+
+ fin = parent_rate;
+ BUG_ON(fin < MHZ);
+
+ nr = fin / MHZ;
+ BUG_ON((fin % MHZ) || nr > BIT(6));
+
+ od = 1;
+
+ reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19);
+ clkc_writel(reg, clk->regofs);
+
+ reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0;
+ clkc_writel((nf >> 1) - 1, reg);
+
+ reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0;
+ while (!(clkc_readl(reg) & BIT(6)))
+ cpu_relax();
+
+ return 0;
+}
+
+static struct clk_ops std_pll_ops = {
+ .recalc_rate = pll_clk_recalc_rate,
+ .round_rate = pll_clk_round_rate,
+ .set_rate = pll_clk_set_rate,
+};
+
+static const char *pll_clk_parents[] = {
+ "osc",
+};
+
+static struct clk_init_data clk_pll1_init = {
+ .name = "pll1",
+ .ops = &std_pll_ops,
+ .parent_names = pll_clk_parents,
+ .num_parents = ARRAY_SIZE(pll_clk_parents),
+};
+
+static struct clk_init_data clk_pll2_init = {
+ .name = "pll2",
+ .ops = &std_pll_ops,
+ .parent_names = pll_clk_parents,
+ .num_parents = ARRAY_SIZE(pll_clk_parents),
+};
+
+static struct clk_init_data clk_pll3_init = {
+ .name = "pll3",
+ .ops = &std_pll_ops,
+ .parent_names = pll_clk_parents,
+ .num_parents = ARRAY_SIZE(pll_clk_parents),
+};
+
+static struct clk_pll clk_pll1 = {
+ .regofs = SIRFSOC_CLKC_PLL1_CFG0,
+ .hw = {
+ .init = &clk_pll1_init,
+ },
+};
+
+static struct clk_pll clk_pll2 = {
+ .regofs = SIRFSOC_CLKC_PLL2_CFG0,
+ .hw = {
+ .init = &clk_pll2_init,
+ },
+};
+
+static struct clk_pll clk_pll3 = {
+ .regofs = SIRFSOC_CLKC_PLL3_CFG0,
+ .hw = {
+ .init = &clk_pll3_init,
+ },
+};
+
+/*
+ * usb uses specified pll
+ */
+
+static int usb_pll_clk_enable(struct clk_hw *hw)
+{
+ u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
+ reg &= ~(SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS);
+ writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
+ while (!(readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL) &
+ SIRFSOC_USBPHY_PLL_LOCK))
+ cpu_relax();
+
+ return 0;
+}
+
+static void usb_pll_clk_disable(struct clk_hw *clk)
+{
+ u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
+ reg |= (SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS);
+ writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
+}
+
+static unsigned long usb_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+ u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
+ return (reg & SIRFSOC_USBPHY_PLL_BYPASS) ? parent_rate : 48*MHZ;
+}
+
+static struct clk_ops usb_pll_ops = {
+ .enable = usb_pll_clk_enable,
+ .disable = usb_pll_clk_disable,
+ .recalc_rate = usb_pll_clk_recalc_rate,
+};
+
+static struct clk_init_data clk_usb_pll_init = {
+ .name = "usb_pll",
+ .ops = &usb_pll_ops,
+ .parent_names = pll_clk_parents,
+ .num_parents = ARRAY_SIZE(pll_clk_parents),
+};
+
+static struct clk_hw usb_pll_clk_hw = {
+ .init = &clk_usb_pll_init,
+};
+
+/*
+ * clock domains - cpu, mem, sys/io, dsp, gfx
+ */
+
+static const char *dmn_clk_parents[] = {
+ "rtc",
+ "osc",
+ "pll1",
+ "pll2",
+ "pll3",
+};
+
+static u8 dmn_clk_get_parent(struct clk_hw *hw)
+{
+ struct clk_dmn *clk = to_dmnclk(hw);
+ u32 cfg = clkc_readl(clk->regofs);
+
+ /* parent of io domain can only be pll3 */
+ if (strcmp(hw->init->name, "io") == 0)
+ return 4;
+
+ WARN_ON((cfg & (BIT(3) - 1)) > 4);
+
+ return cfg & (BIT(3) - 1);
+}
+
+static int dmn_clk_set_parent(struct clk_hw *hw, u8 parent)
+{
+ struct clk_dmn *clk = to_dmnclk(hw);
+ u32 cfg = clkc_readl(clk->regofs);
+
+ /* parent of io domain can only be pll3 */
+ if (strcmp(hw->init->name, "io") == 0)
+ return -EINVAL;
+
+ cfg &= ~(BIT(3) - 1);
+ clkc_writel(cfg | parent, clk->regofs);
+ /* BIT(3) - switching status: 1 - busy, 0 - done */
+ while (clkc_readl(clk->regofs) & BIT(3))
+ cpu_relax();
+
+ return 0;
+}
+
+static unsigned long dmn_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+
+{
+ unsigned long fin = parent_rate;
+ struct clk_dmn *clk = to_dmnclk(hw);
+
+ u32 cfg = clkc_readl(clk->regofs);
+
+ if (cfg & BIT(24)) {
+ /* fcd bypass mode */
+ return fin;
+ } else {
+ /*
+ * wait count: bit[19:16], hold count: bit[23:20]
+ */
+ u32 wait = (cfg >> 16) & (BIT(4) - 1);
+ u32 hold = (cfg >> 20) & (BIT(4) - 1);
+
+ return fin / (wait + hold + 2);
+ }
+}
+
+static long dmn_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ unsigned long fin;
+ unsigned ratio, wait, hold;
+ unsigned bits = (strcmp(hw->init->name, "mem") == 0) ? 3 : 4;
+
+ fin = *parent_rate;
+ ratio = fin / rate;
+
+ if (ratio < 2)
+ ratio = 2;
+ if (ratio > BIT(bits + 1))
+ ratio = BIT(bits + 1);
+
+ wait = (ratio >> 1) - 1;
+ hold = ratio - wait - 2;
+
+ return fin / (wait + hold + 2);
+}
+
+static int dmn_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_dmn *clk = to_dmnclk(hw);
+ unsigned long fin;
+ unsigned ratio, wait, hold, reg;
+ unsigned bits = (strcmp(hw->init->name, "mem") == 0) ? 3 : 4;
+
+ fin = parent_rate;
+ ratio = fin / rate;
+
+ if (unlikely(ratio < 2 || ratio > BIT(bits + 1)))
+ return -EINVAL;
+
+ WARN_ON(fin % rate);
+
+ wait = (ratio >> 1) - 1;
+ hold = ratio - wait - 2;
+
+ reg = clkc_readl(clk->regofs);
+ reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20));
+ reg |= (wait << 16) | (hold << 20) | BIT(25);
+ clkc_writel(reg, clk->regofs);
+
+ /* waiting FCD been effective */
+ while (clkc_readl(clk->regofs) & BIT(25))
+ cpu_relax();
+
+ return 0;
+}
+
+static struct clk_ops msi_ops = {
+ .set_rate = dmn_clk_set_rate,
+ .round_rate = dmn_clk_round_rate,
+ .recalc_rate = dmn_clk_recalc_rate,
+ .set_parent = dmn_clk_set_parent,
+ .get_parent = dmn_clk_get_parent,
+};
+
+static struct clk_init_data clk_mem_init = {
+ .name = "mem",
+ .ops = &msi_ops,
+ .parent_names = dmn_clk_parents,
+ .num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
+
+static struct clk_dmn clk_mem = {
+ .regofs = SIRFSOC_CLKC_MEM_CFG,
+ .hw = {
+ .init = &clk_mem_init,
+ },
+};
+
+static struct clk_init_data clk_sys_init = {
+ .name = "sys",
+ .ops = &msi_ops,
+ .parent_names = dmn_clk_parents,
+ .num_parents = ARRAY_SIZE(dmn_clk_parents),
+ .flags = CLK_SET_RATE_GATE,
+};
+
+static struct clk_dmn clk_sys = {
+ .regofs = SIRFSOC_CLKC_SYS_CFG,
+ .hw = {
+ .init = &clk_sys_init,
+ },
+};
+
+static struct clk_init_data clk_io_init = {
+ .name = "io",
+ .ops = &msi_ops,
+ .parent_names = dmn_clk_parents,
+ .num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
+
+static struct clk_dmn clk_io = {
+ .regofs = SIRFSOC_CLKC_IO_CFG,
+ .hw = {
+ .init = &clk_io_init,
+ },
+};
+
+static struct clk_ops cpu_ops = {
+ .set_parent = dmn_clk_set_parent,
+ .get_parent = dmn_clk_get_parent,
+};
+
+static struct clk_init_data clk_cpu_init = {
+ .name = "cpu",
+ .ops = &cpu_ops,
+ .parent_names = dmn_clk_parents,
+ .num_parents = ARRAY_SIZE(dmn_clk_parents),
+ .flags = CLK_SET_RATE_PARENT,
+};
+
+static struct clk_dmn clk_cpu = {
+ .regofs = SIRFSOC_CLKC_CPU_CFG,
+ .hw = {
+ .init = &clk_cpu_init,
+ },
+};
+
+static struct clk_ops dmn_ops = {
+ .is_enabled = std_clk_is_enabled,
+ .enable = std_clk_enable,
+ .disable = std_clk_disable,
+ .set_rate = dmn_clk_set_rate,
+ .round_rate = dmn_clk_round_rate,
+ .recalc_rate = dmn_clk_recalc_rate,
+ .set_parent = dmn_clk_set_parent,
+ .get_parent = dmn_clk_get_parent,
+};
+
+/* dsp, gfx, mm, lcd and vpp domain */
+
+static struct clk_init_data clk_dsp_init = {
+ .name = "dsp",
+ .ops = &dmn_ops,
+ .parent_names = dmn_clk_parents,
+ .num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
+
+static struct clk_dmn clk_dsp = {
+ .regofs = SIRFSOC_CLKC_DSP_CFG,
+ .enable_bit = 0,
+ .hw = {
+ .init = &clk_dsp_init,
+ },
+};
+
+static struct clk_init_data clk_gfx_init = {
+ .name = "gfx",
+ .ops = &dmn_ops,
+ .parent_names = dmn_clk_parents,
+ .num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
+
+static struct clk_dmn clk_gfx = {
+ .regofs = SIRFSOC_CLKC_GFX_CFG,
+ .enable_bit = 8,
+ .hw = {
+ .init = &clk_gfx_init,
+ },
+};
+
+static struct clk_init_data clk_mm_init = {
+ .name = "mm",
+ .ops = &dmn_ops,
+ .parent_names = dmn_clk_parents,
+ .num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
+
+static struct clk_dmn clk_mm = {
+ .regofs = SIRFSOC_CLKC_MM_CFG,
+ .enable_bit = 9,
+ .hw = {
+ .init = &clk_mm_init,
+ },
+};
+
+static struct clk_init_data clk_lcd_init = {
+ .name = "lcd",
+ .ops = &dmn_ops,
+ .parent_names = dmn_clk_parents,
+ .num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
+
+static struct clk_dmn clk_lcd = {
+ .regofs = SIRFSOC_CLKC_LCD_CFG,
+ .enable_bit = 10,
+ .hw = {
+ .init = &clk_lcd_init,
+ },
+};
+
+static struct clk_init_data clk_vpp_init = {
+ .name = "vpp",
+ .ops = &dmn_ops,
+ .parent_names = dmn_clk_parents,
+ .num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
+
+static struct clk_dmn clk_vpp = {
+ .regofs = SIRFSOC_CLKC_LCD_CFG,
+ .enable_bit = 11,
+ .hw = {
+ .init = &clk_vpp_init,
+ },
+};
+
+static struct clk_init_data clk_mmc01_init = {
+ .name = "mmc01",
+ .ops = &dmn_ops,
+ .parent_names = dmn_clk_parents,
+ .num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
+
+static struct clk_dmn clk_mmc01 = {
+ .regofs = SIRFSOC_CLKC_MMC_CFG,
+ .enable_bit = 59,
+ .hw = {
+ .init = &clk_mmc01_init,
+ },
+};
+
+static struct clk_init_data clk_mmc23_init = {
+ .name = "mmc23",
+ .ops = &dmn_ops,
+ .parent_names = dmn_clk_parents,
+ .num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
+
+static struct clk_dmn clk_mmc23 = {
+ .regofs = SIRFSOC_CLKC_MMC_CFG,
+ .enable_bit = 60,
+ .hw = {
+ .init = &clk_mmc23_init,
+ },
+};
+
+static struct clk_init_data clk_mmc45_init = {
+ .name = "mmc45",
+ .ops = &dmn_ops,
+ .parent_names = dmn_clk_parents,
+ .num_parents = ARRAY_SIZE(dmn_clk_parents),
+};
+
+static struct clk_dmn clk_mmc45 = {
+ .regofs = SIRFSOC_CLKC_MMC_CFG,
+ .enable_bit = 61,
+ .hw = {
+ .init = &clk_mmc45_init,
+ },
+};
+
+/*
+ * peripheral controllers in io domain
+ */
+
+static int std_clk_is_enabled(struct clk_hw *hw)
+{
+ u32 reg;
+ int bit;
+ struct clk_std *clk = to_stdclk(hw);
+
+ bit = clk->enable_bit % 32;
+ reg = clk->enable_bit / 32;
+ reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
+
+ return !!(clkc_readl(reg) & BIT(bit));
+}
+
+static int std_clk_enable(struct clk_hw *hw)
+{
+ u32 val, reg;
+ int bit;
+ struct clk_std *clk = to_stdclk(hw);
+
+ BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63);
+
+ bit = clk->enable_bit % 32;
+ reg = clk->enable_bit / 32;
+ reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
+
+ val = clkc_readl(reg) | BIT(bit);
+ clkc_writel(val, reg);
+ return 0;
+}
+
+static void std_clk_disable(struct clk_hw *hw)
+{
+ u32 val, reg;
+ int bit;
+ struct clk_std *clk = to_stdclk(hw);
+
+ BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63);
+
+ bit = clk->enable_bit % 32;
+ reg = clk->enable_bit / 32;
+ reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
+
+ val = clkc_readl(reg) & ~BIT(bit);
+ clkc_writel(val, reg);
+}
+
+static const char *std_clk_io_parents[] = {
+ "io",
+};
+
+static struct clk_ops ios_ops = {
+ .is_enabled = std_clk_is_enabled,
+ .enable = std_clk_enable,
+ .disable = std_clk_disable,
+};
+
+static struct clk_init_data clk_dmac0_init = {
+ .name = "dmac0",
+ .ops = &ios_ops,
+ .parent_names = std_clk_io_parents,
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_dmac0 = {
+ .enable_bit = 32,
+ .hw = {
+ .init = &clk_dmac0_init,
+ },
+};
+
+static struct clk_init_data clk_dmac1_init = {
+ .name = "dmac1",
+ .ops = &ios_ops,
+ .parent_names = std_clk_io_parents,
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_dmac1 = {
+ .enable_bit = 33,
+ .hw = {
+ .init = &clk_dmac1_init,
+ },
+};
+
+static struct clk_init_data clk_nand_init = {
+ .name = "nand",
+ .ops = &ios_ops,
+ .parent_names = std_clk_io_parents,
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_nand = {
+ .enable_bit = 34,
+ .hw = {
+ .init = &clk_nand_init,
+ },
+};
+
+static struct clk_init_data clk_audio_init = {
+ .name = "audio",
+ .ops = &ios_ops,
+ .parent_names = std_clk_io_parents,
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_audio = {
+ .enable_bit = 35,
+ .hw = {
+ .init = &clk_audio_init,
+ },
+};
+
+static struct clk_init_data clk_uart0_init = {
+ .name = "uart0",
+ .ops = &ios_ops,
+ .parent_names = std_clk_io_parents,
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_uart0 = {
+ .enable_bit = 36,
+ .hw = {
+ .init = &clk_uart0_init,
+ },
+};
+
+static struct clk_init_data clk_uart1_init = {
+ .name = "uart1",
+ .ops = &ios_ops,
+ .parent_names = std_clk_io_parents,
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_uart1 = {
+ .enable_bit = 37,
+ .hw = {
+ .init = &clk_uart1_init,
+ },
+};
+
+static struct clk_init_data clk_uart2_init = {
+ .name = "uart2",
+ .ops = &ios_ops,
+ .parent_names = std_clk_io_parents,
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_uart2 = {
+ .enable_bit = 38,
+ .hw = {
+ .init = &clk_uart2_init,
+ },
+};
+
+static struct clk_init_data clk_usp0_init = {
+ .name = "usp0",
+ .ops = &ios_ops,
+ .parent_names = std_clk_io_parents,
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_usp0 = {
+ .enable_bit = 39,
+ .hw = {
+ .init = &clk_usp0_init,
+ },
+};
+
+static struct clk_init_data clk_usp1_init = {
+ .name = "usp1",
+ .ops = &ios_ops,
+ .parent_names = std_clk_io_parents,
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_usp1 = {
+ .enable_bit = 40,
+ .hw = {
+ .init = &clk_usp1_init,
+ },
+};
+
+static struct clk_init_data clk_usp2_init = {
+ .name = "usp2",
+ .ops = &ios_ops,
+ .parent_names = std_clk_io_parents,
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_usp2 = {
+ .enable_bit = 41,
+ .hw = {
+ .init = &clk_usp2_init,
+ },
+};
+
+static struct clk_init_data clk_vip_init = {
+ .name = "vip",
+ .ops = &ios_ops,
+ .parent_names = std_clk_io_parents,
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_vip = {
+ .enable_bit = 42,
+ .hw = {
+ .init = &clk_vip_init,
+ },
+};
+
+static struct clk_init_data clk_spi0_init = {
+ .name = "spi0",
+ .ops = &ios_ops,
+ .parent_names = std_clk_io_parents,
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_spi0 = {
+ .enable_bit = 43,
+ .hw = {
+ .init = &clk_spi0_init,
+ },
+};
+
+static struct clk_init_data clk_spi1_init = {
+ .name = "spi1",
+ .ops = &ios_ops,
+ .parent_names = std_clk_io_parents,
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_spi1 = {
+ .enable_bit = 44,
+ .hw = {
+ .init = &clk_spi1_init,
+ },
+};
+
+static struct clk_init_data clk_tsc_init = {
+ .name = "tsc",
+ .ops = &ios_ops,
+ .parent_names = std_clk_io_parents,
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_tsc = {
+ .enable_bit = 45,
+ .hw = {
+ .init = &clk_tsc_init,
+ },
+};
+
+static struct clk_init_data clk_i2c0_init = {
+ .name = "i2c0",
+ .ops = &ios_ops,
+ .parent_names = std_clk_io_parents,
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_i2c0 = {
+ .enable_bit = 46,
+ .hw = {
+ .init = &clk_i2c0_init,
+ },
+};
+
+static struct clk_init_data clk_i2c1_init = {
+ .name = "i2c1",
+ .ops = &ios_ops,
+ .parent_names = std_clk_io_parents,
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_i2c1 = {
+ .enable_bit = 47,
+ .hw = {
+ .init = &clk_i2c1_init,
+ },
+};
+
+static struct clk_init_data clk_pwmc_init = {
+ .name = "pwmc",
+ .ops = &ios_ops,
+ .parent_names = std_clk_io_parents,
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_pwmc = {
+ .enable_bit = 48,
+ .hw = {
+ .init = &clk_pwmc_init,
+ },
+};
+
+static struct clk_init_data clk_efuse_init = {
+ .name = "efuse",
+ .ops = &ios_ops,
+ .parent_names = std_clk_io_parents,
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_efuse = {
+ .enable_bit = 49,
+ .hw = {
+ .init = &clk_efuse_init,
+ },
+};
+
+static struct clk_init_data clk_pulse_init = {
+ .name = "pulse",
+ .ops = &ios_ops,
+ .parent_names = std_clk_io_parents,
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_pulse = {
+ .enable_bit = 50,
+ .hw = {
+ .init = &clk_pulse_init,
+ },
+};
+
+static const char *std_clk_dsp_parents[] = {
+ "dsp",
+};
+
+static struct clk_init_data clk_gps_init = {
+ .name = "gps",
+ .ops = &ios_ops,
+ .parent_names = std_clk_dsp_parents,
+ .num_parents = ARRAY_SIZE(std_clk_dsp_parents),
+};
+
+static struct clk_std clk_gps = {
+ .enable_bit = 1,
+ .hw = {
+ .init = &clk_gps_init,
+ },
+};
+
+static struct clk_init_data clk_mf_init = {
+ .name = "mf",
+ .ops = &ios_ops,
+ .parent_names = std_clk_io_parents,
+ .num_parents = ARRAY_SIZE(std_clk_io_parents),
+};
+
+static struct clk_std clk_mf = {
+ .enable_bit = 2,
+ .hw = {
+ .init = &clk_mf_init,
+ },
+};
+
+static const char *std_clk_sys_parents[] = {
+ "sys",
+};
+
+static struct clk_init_data clk_security_init = {
+ .name = "mf",
+ .ops = &ios_ops,
+ .parent_names = std_clk_sys_parents,
+ .num_parents = ARRAY_SIZE(std_clk_sys_parents),
+};
+
+static struct clk_std clk_security = {
+ .enable_bit = 19,
+ .hw = {
+ .init = &clk_security_init,
+ },
+};
+
+static const char *std_clk_usb_parents[] = {
+ "usb_pll",
+};
+
+static struct clk_init_data clk_usb0_init = {
+ .name = "usb0",
+ .ops = &ios_ops,
+ .parent_names = std_clk_usb_parents,
+ .num_parents = ARRAY_SIZE(std_clk_usb_parents),
+};
+
+static struct clk_std clk_usb0 = {
+ .enable_bit = 16,
+ .hw = {
+ .init = &clk_usb0_init,
+ },
+};
+
+static struct clk_init_data clk_usb1_init = {
+ .name = "usb1",
+ .ops = &ios_ops,
+ .parent_names = std_clk_usb_parents,
+ .num_parents = ARRAY_SIZE(std_clk_usb_parents),
+};
+
+static struct clk_std clk_usb1 = {
+ .enable_bit = 17,
+ .hw = {
+ .init = &clk_usb1_init,
+ },
+};
+
+static struct of_device_id clkc_ids[] = {
+ { .compatible = "sirf,prima2-clkc" },
+ {},
+};
+
+static struct of_device_id rsc_ids[] = {
+ { .compatible = "sirf,prima2-rsc" },
+ {},
+};
+
+void __init sirfsoc_of_clk_init(void)
+{
+ struct clk *clk;
+ struct device_node *np;
+
+ np = of_find_matching_node(NULL, clkc_ids);
+ if (!np)
+ panic("unable to find compatible clkc node in dtb\n");
+
+ sirfsoc_clk_vbase = of_iomap(np, 0);
+ if (!sirfsoc_clk_vbase)
+ panic("unable to map clkc registers\n");
+
+ of_node_put(np);
+
+ np = of_find_matching_node(NULL, rsc_ids);
+ if (!np)
+ panic("unable to find compatible rsc node in dtb\n");
+
+ sirfsoc_rsc_vbase = of_iomap(np, 0);
+ if (!sirfsoc_rsc_vbase)
+ panic("unable to map rsc registers\n");
+
+ of_node_put(np);
+
+
+ /* These are always available (RTC and 26MHz OSC)*/
+ clk = clk_register_fixed_rate(NULL, "rtc", NULL,
+ CLK_IS_ROOT, 32768);
+ BUG_ON(!clk);
+ clk = clk_register_fixed_rate(NULL, "osc", NULL,
+ CLK_IS_ROOT, 26000000);
+ BUG_ON(!clk);
+
+ clk = clk_register(NULL, &clk_pll1.hw);
+ BUG_ON(!clk);
+ clk = clk_register(NULL, &clk_pll2.hw);
+ BUG_ON(!clk);
+ clk = clk_register(NULL, &clk_pll3.hw);
+ BUG_ON(!clk);
+ clk = clk_register(NULL, &clk_mem.hw);
+ BUG_ON(!clk);
+ clk = clk_register(NULL, &clk_sys.hw);
+ BUG_ON(!clk);
+ clk = clk_register(NULL, &clk_security.hw);
+ BUG_ON(!clk);
+ clk_register_clkdev(clk, NULL, "b8030000.security");
+ clk = clk_register(NULL, &clk_dsp.hw);
+ BUG_ON(!clk);
+ clk = clk_register(NULL, &clk_gps.hw);
+ BUG_ON(!clk);
+ clk_register_clkdev(clk, NULL, "a8010000.gps");
+ clk = clk_register(NULL, &clk_mf.hw);
+ BUG_ON(!clk);
+ clk = clk_register(NULL, &clk_io.hw);
+ BUG_ON(!clk);
+ clk_register_clkdev(clk, NULL, "io");
+ clk = clk_register(NULL, &clk_cpu.hw);
+ BUG_ON(!clk);
+ clk_register_clkdev(clk, NULL, "cpu");
+ clk = clk_register(NULL, &clk_uart0.hw);
+ BUG_ON(!clk);
+ clk_register_clkdev(clk, NULL, "b0050000.uart");
+ clk = clk_register(NULL, &clk_uart1.hw);
+ BUG_ON(!clk);
+ clk_register_clkdev(clk, NULL, "b0060000.uart");
+ clk = clk_register(NULL, &clk_uart2.hw);
+ BUG_ON(!clk);
+ clk_register_clkdev(clk, NULL, "b0070000.uart");
+ clk = clk_register(NULL, &clk_tsc.hw);
+ BUG_ON(!clk);
+ clk_register_clkdev(clk, NULL, "b0110000.tsc");
+ clk = clk_register(NULL, &clk_i2c0.hw);
+ BUG_ON(!clk);
+ clk_register_clkdev(clk, NULL, "b00e0000.i2c");
+ clk = clk_register(NULL, &clk_i2c1.hw);
+ BUG_ON(!clk);
+ clk_register_clkdev(clk, NULL, "b00f0000.i2c");
+ clk = clk_register(NULL, &clk_spi0.hw);
+ BUG_ON(!clk);
+ clk_register_clkdev(clk, NULL, "b00d0000.spi");
+ clk = clk_register(NULL, &clk_spi1.hw);
+ BUG_ON(!clk);
+ clk_register_clkdev(clk, NULL, "b0170000.spi");
+ clk = clk_register(NULL, &clk_pwmc.hw);
+ BUG_ON(!clk);
+ clk_register_clkdev(clk, NULL, "b0130000.pwm");
+ clk = clk_register(NULL, &clk_efuse.hw);
+ BUG_ON(!clk);
+ clk_register_clkdev(clk, NULL, "b0140000.efusesys");
+ clk = clk_register(NULL, &clk_pulse.hw);
+ BUG_ON(!clk);
+ clk_register_clkdev(clk, NULL, "b0150000.pulsec");
+ clk = clk_register(NULL, &clk_dmac0.hw);
+ BUG_ON(!clk);
+ clk_register_clkdev(clk, NULL, "b00b0000.dma-controller");
+ clk = clk_register(NULL, &clk_dmac1.hw);
+ BUG_ON(!clk);
+ clk_register_clkdev(clk, NULL, "b0160000.dma-controller");
+ clk = clk_register(NULL, &clk_nand.hw);
+ BUG_ON(!clk);
+ clk_register_clkdev(clk, NULL, "b0030000.nand");
+ clk = clk_register(NULL, &clk_audio.hw);
+ BUG_ON(!clk);
+ clk_register_clkdev(clk, NULL, "b0040000.audio");
+ clk = clk_register(NULL, &clk_usp0.hw);
+ BUG_ON(!clk);
+ clk_register_clkdev(clk, NULL, "b0080000.usp");
+ clk = clk_register(NULL, &clk_usp1.hw);
+ BUG_ON(!clk);
+ clk_register_clkdev(clk, NULL, "b0090000.usp");
+ clk = clk_register(NULL, &clk_usp2.hw);
+ BUG_ON(!clk);
+ clk_register_clkdev(clk, NULL, "b00a0000.usp");
+ clk = clk_register(NULL, &clk_vip.hw);
+ BUG_ON(!clk);
+ clk_register_clkdev(clk, NULL, "b00c0000.vip");
+ clk = clk_register(NULL, &clk_gfx.hw);
+ BUG_ON(!clk);
+ clk_register_clkdev(clk, NULL, "98000000.graphics");
+ clk = clk_register(NULL, &clk_mm.hw);
+ BUG_ON(!clk);
+ clk_register_clkdev(clk, NULL, "a0000000.multimedia");
+ clk = clk_register(NULL, &clk_lcd.hw);
+ BUG_ON(!clk);
+ clk_register_clkdev(clk, NULL, "90010000.display");
+ clk = clk_register(NULL, &clk_vpp.hw);
+ BUG_ON(!clk);
+ clk_register_clkdev(clk, NULL, "90020000.vpp");
+ clk = clk_register(NULL, &clk_mmc01.hw);
+ BUG_ON(!clk);
+ clk = clk_register(NULL, &clk_mmc23.hw);
+ BUG_ON(!clk);
+ clk = clk_register(NULL, &clk_mmc45.hw);
+ BUG_ON(!clk);
+ clk = clk_register(NULL, &usb_pll_clk_hw);
+ BUG_ON(!clk);
+ clk = clk_register(NULL, &clk_usb0.hw);
+ BUG_ON(!clk);
+ clk_register_clkdev(clk, NULL, "b00e0000.usb");
+ clk = clk_register(NULL, &clk_usb1.hw);
+ BUG_ON(!clk);
+ clk_register_clkdev(clk, NULL, "b00f0000.usb");
+}
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index dc5184d..d982593 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -30,9 +30,6 @@
#include <asm/mach/irq.h>
-#include <mach/iomap.h>
-#include <mach/suspend.h>
-
#define GPIO_BANK(x) ((x) >> 5)
#define GPIO_PORT(x) (((x) >> 3) & 0x3)
#define GPIO_BIT(x) ((x) & 0x7)
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index b4aaa1b..2025adf 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -545,7 +545,7 @@
config I2C_PNX
tristate "I2C bus support for Philips PNX and NXP LPC targets"
- depends on ARCH_PNX4008 || ARCH_LPC32XX
+ depends on ARCH_LPC32XX
help
This driver supports the Philips IP3204 I2C IP block master and/or
slave controller
diff --git a/drivers/i2c/busses/i2c-iop3xx.c b/drivers/i2c/busses/i2c-iop3xx.c
index 93f147a..2f99613 100644
--- a/drivers/i2c/busses/i2c-iop3xx.c
+++ b/drivers/i2c/busses/i2c-iop3xx.c
@@ -4,13 +4,13 @@
/* Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd
* <Peter dot Milne at D hyphen TACQ dot com>
*
- * With acknowledgements to i2c-algo-ibm_ocp.c by
+ * With acknowledgements to i2c-algo-ibm_ocp.c by
* Ian DaSilva, MontaVista Software, Inc. idasilva@mvista.com
*
* And i2c-algo-pcf.c, which was created by Simon G. Vogl and Hans Berglund:
*
* Copyright (C) 1995-1997 Simon G. Vogl, 1998-2000 Hans Berglund
- *
+ *
* And which acknowledged Kyösti Mälkki <kmalkki@cc.hut.fi>,
* Frodo Looijaard <frodol@dds.nl>, Martin Bailey<mbailey@littlefeet-inc.com>
*
@@ -39,14 +39,15 @@
#include <linux/platform_device.h>
#include <linux/i2c.h>
#include <linux/io.h>
+#include <linux/gpio.h>
#include "i2c-iop3xx.h"
/* global unit counter */
static int i2c_id;
-static inline unsigned char
-iic_cook_addr(struct i2c_msg *msg)
+static inline unsigned char
+iic_cook_addr(struct i2c_msg *msg)
{
unsigned char addr;
@@ -55,38 +56,38 @@
if (msg->flags & I2C_M_RD)
addr |= 1;
- return addr;
+ return addr;
}
-static void
+static void
iop3xx_i2c_reset(struct i2c_algo_iop3xx_data *iop3xx_adap)
{
/* Follows devman 9.3 */
__raw_writel(IOP3XX_ICR_UNIT_RESET, iop3xx_adap->ioaddr + CR_OFFSET);
__raw_writel(IOP3XX_ISR_CLEARBITS, iop3xx_adap->ioaddr + SR_OFFSET);
__raw_writel(0, iop3xx_adap->ioaddr + CR_OFFSET);
-}
+}
-static void
+static void
iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap)
{
u32 cr = IOP3XX_ICR_GCD | IOP3XX_ICR_SCLEN | IOP3XX_ICR_UE;
- /*
+ /*
* Every time unit enable is asserted, GPOD needs to be cleared
* on IOP3XX to avoid data corruption on the bus.
*/
#if defined(CONFIG_ARCH_IOP32X) || defined(CONFIG_ARCH_IOP33X)
if (iop3xx_adap->id == 0) {
- gpio_line_set(IOP3XX_GPIO_LINE(7), GPIO_LOW);
- gpio_line_set(IOP3XX_GPIO_LINE(6), GPIO_LOW);
+ gpio_set_value(7, 0);
+ gpio_set_value(6, 0);
} else {
- gpio_line_set(IOP3XX_GPIO_LINE(5), GPIO_LOW);
- gpio_line_set(IOP3XX_GPIO_LINE(4), GPIO_LOW);
+ gpio_set_value(5, 0);
+ gpio_set_value(4, 0);
}
#endif
/* NB SR bits not same position as CR IE bits :-( */
- iop3xx_adap->SR_enabled =
+ iop3xx_adap->SR_enabled =
IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD |
IOP3XX_ISR_RXFULL | IOP3XX_ISR_TXEMPTY;
@@ -96,23 +97,23 @@
__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
}
-static void
+static void
iop3xx_i2c_transaction_cleanup(struct i2c_algo_iop3xx_data *iop3xx_adap)
{
unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
-
- cr &= ~(IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE |
+
+ cr &= ~(IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE |
IOP3XX_ICR_MSTOP | IOP3XX_ICR_SCLEN);
__raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
}
-/*
- * NB: the handler has to clear the source of the interrupt!
+/*
+ * NB: the handler has to clear the source of the interrupt!
* Then it passes the SR flags of interest to BH via adap data
*/
-static irqreturn_t
-iop3xx_i2c_irq_handler(int this_irq, void *dev_id)
+static irqreturn_t
+iop3xx_i2c_irq_handler(int this_irq, void *dev_id)
{
struct i2c_algo_iop3xx_data *iop3xx_adap = dev_id;
u32 sr = __raw_readl(iop3xx_adap->ioaddr + SR_OFFSET);
@@ -126,7 +127,7 @@
}
/* check all error conditions, clear them , report most important */
-static int
+static int
iop3xx_i2c_error(u32 sr)
{
int rc = 0;
@@ -135,12 +136,12 @@
if ( !rc ) rc = -I2C_ERR_BERR;
}
if ((sr & IOP3XX_ISR_ALD)) {
- if ( !rc ) rc = -I2C_ERR_ALD;
+ if ( !rc ) rc = -I2C_ERR_ALD;
}
- return rc;
+ return rc;
}
-static inline u32
+static inline u32
iop3xx_i2c_get_srstat(struct i2c_algo_iop3xx_data *iop3xx_adap)
{
unsigned long flags;
@@ -161,8 +162,8 @@
typedef int (* compare_func)(unsigned test, unsigned mask);
/* returns 1 on correct comparison */
-static int
-iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap,
+static int
+iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap,
unsigned flags, unsigned* status,
compare_func compare)
{
@@ -192,47 +193,47 @@
}
/*
- * Concrete compare_funcs
+ * Concrete compare_funcs
*/
-static int
+static int
all_bits_clear(unsigned test, unsigned mask)
{
return (test & mask) == 0;
}
-static int
+static int
any_bits_set(unsigned test, unsigned mask)
{
return (test & mask) != 0;
}
-static int
+static int
iop3xx_i2c_wait_tx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
{
- return iop3xx_i2c_wait_event(
- iop3xx_adap,
+ return iop3xx_i2c_wait_event(
+ iop3xx_adap,
IOP3XX_ISR_TXEMPTY | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD,
status, any_bits_set);
}
-static int
+static int
iop3xx_i2c_wait_rx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
{
- return iop3xx_i2c_wait_event(
- iop3xx_adap,
+ return iop3xx_i2c_wait_event(
+ iop3xx_adap,
IOP3XX_ISR_RXFULL | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD,
status, any_bits_set);
}
-static int
+static int
iop3xx_i2c_wait_idle(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
{
- return iop3xx_i2c_wait_event(
+ return iop3xx_i2c_wait_event(
iop3xx_adap, IOP3XX_ISR_UNITBUSY, status, all_bits_clear);
}
-static int
-iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap,
+static int
+iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap,
struct i2c_msg* msg)
{
unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
@@ -247,7 +248,7 @@
}
__raw_writel(iic_cook_addr(msg), iop3xx_adap->ioaddr + DBR_OFFSET);
-
+
cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK);
cr |= IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE;
@@ -257,8 +258,8 @@
return rc;
}
-static int
-iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte,
+static int
+iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte,
int stop)
{
unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
@@ -277,10 +278,10 @@
rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status);
return rc;
-}
+}
-static int
-iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char* byte,
+static int
+iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char* byte,
int stop)
{
unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
@@ -304,19 +305,19 @@
return rc;
}
-static int
+static int
iop3xx_i2c_writebytes(struct i2c_adapter *i2c_adap, const char *buf, int count)
{
struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
int ii;
int rc = 0;
- for (ii = 0; rc == 0 && ii != count; ++ii)
+ for (ii = 0; rc == 0 && ii != count; ++ii)
rc = iop3xx_i2c_write_byte(iop3xx_adap, buf[ii], ii==count-1);
return rc;
}
-static int
+static int
iop3xx_i2c_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count)
{
struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
@@ -325,7 +326,7 @@
for (ii = 0; rc == 0 && ii != count; ++ii)
rc = iop3xx_i2c_read_byte(iop3xx_adap, &buf[ii], ii==count-1);
-
+
return rc;
}
@@ -336,8 +337,8 @@
* Each transfer (i.e. a read or a write) is separated by a repeated start
* condition.
*/
-static int
-iop3xx_i2c_handle_msg(struct i2c_adapter *i2c_adap, struct i2c_msg* pmsg)
+static int
+iop3xx_i2c_handle_msg(struct i2c_adapter *i2c_adap, struct i2c_msg* pmsg)
{
struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
int rc;
@@ -357,8 +358,8 @@
/*
* master_xfer() - main read/write entry
*/
-static int
-iop3xx_i2c_master_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
+static int
+iop3xx_i2c_master_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
int num)
{
struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
@@ -375,14 +376,14 @@
}
iop3xx_i2c_transaction_cleanup(iop3xx_adap);
-
+
if(ret)
return ret;
- return im;
+ return im;
}
-static u32
+static u32
iop3xx_i2c_func(struct i2c_adapter *adap)
{
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
@@ -393,11 +394,11 @@
.functionality = iop3xx_i2c_func,
};
-static int
+static int
iop3xx_i2c_remove(struct platform_device *pdev)
{
struct i2c_adapter *padapter = platform_get_drvdata(pdev);
- struct i2c_algo_iop3xx_data *adapter_data =
+ struct i2c_algo_iop3xx_data *adapter_data =
(struct i2c_algo_iop3xx_data *)padapter->algo_data;
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
unsigned long cr = __raw_readl(adapter_data->ioaddr + CR_OFFSET);
@@ -419,7 +420,7 @@
return 0;
}
-static int
+static int
iop3xx_i2c_probe(struct platform_device *pdev)
{
struct resource *res;
diff --git a/drivers/mfd/tps6586x.c b/drivers/mfd/tps6586x.c
index 353c348..380a3c8 100644
--- a/drivers/mfd/tps6586x.c
+++ b/drivers/mfd/tps6586x.c
@@ -25,6 +25,7 @@
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/regulator/of_regulator.h>
+#include <linux/regulator/machine.h>
#include <linux/mfd/core.h>
#include <linux/mfd/tps6586x.h>
@@ -346,6 +347,7 @@
#ifdef CONFIG_OF
static struct of_regulator_match tps6586x_matches[] = {
+ { .name = "sys", .driver_data = (void *)TPS6586X_ID_SYS },
{ .name = "sm0", .driver_data = (void *)TPS6586X_ID_SM_0 },
{ .name = "sm1", .driver_data = (void *)TPS6586X_ID_SM_1 },
{ .name = "sm2", .driver_data = (void *)TPS6586X_ID_SM_2 },
@@ -369,6 +371,7 @@
struct tps6586x_platform_data *pdata;
struct tps6586x_subdev_info *devs;
struct device_node *regs;
+ const char *sys_rail_name = NULL;
unsigned int count;
unsigned int i, j;
int err;
@@ -391,12 +394,22 @@
return NULL;
for (i = 0, j = 0; i < num && j < count; i++) {
+ struct regulator_init_data *reg_idata;
+
if (!tps6586x_matches[i].init_data)
continue;
+ reg_idata = tps6586x_matches[i].init_data;
devs[j].name = "tps6586x-regulator";
devs[j].platform_data = tps6586x_matches[i].init_data;
devs[j].id = (int)tps6586x_matches[i].driver_data;
+ if (devs[j].id == TPS6586X_ID_SYS)
+ sys_rail_name = reg_idata->constraints.name;
+
+ if ((devs[j].id == TPS6586X_ID_LDO_5) ||
+ (devs[j].id == TPS6586X_ID_LDO_RTC))
+ reg_idata->supply_regulator = sys_rail_name;
+
devs[j].of_node = tps6586x_matches[i].of_node;
j++;
}
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index 0810ccc..5393c64 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -27,7 +27,6 @@
#include <asm/gpio.h>
-#include <mach/gpio-tegra.h>
#include <mach/sdhci.h>
#include "sdhci-pltfm.h"
diff --git a/drivers/mtd/nand/bcm_umi_nand.c b/drivers/mtd/nand/bcm_umi_nand.c
index c855e7c..d0d1bd4 100644
--- a/drivers/mtd/nand/bcm_umi_nand.c
+++ b/drivers/mtd/nand/bcm_umi_nand.c
@@ -249,20 +249,20 @@
int bcm_umi_nand_inithw(void)
{
/* Configure nand timing parameters */
- REG_UMI_NAND_TCR &= ~0x7ffff;
- REG_UMI_NAND_TCR |= HW_CFG_NAND_TCR;
+ writel(readl(®_UMI_NAND_TCR) & ~0x7ffff, ®_UMI_NAND_TCR);
+ writel(readl(®_UMI_NAND_TCR) | HW_CFG_NAND_TCR, ®_UMI_NAND_TCR);
#if !defined(CONFIG_MTD_NAND_BCM_UMI_HWCS)
/* enable software control of CS */
- REG_UMI_NAND_TCR |= REG_UMI_NAND_TCR_CS_SWCTRL;
+ writel(readl(®_UMI_NAND_TCR) | REG_UMI_NAND_TCR_CS_SWCTRL, ®_UMI_NAND_TCR);
#endif
/* keep NAND chip select asserted */
- REG_UMI_NAND_RCSR |= REG_UMI_NAND_RCSR_CS_ASSERTED;
+ writel(readl(®_UMI_NAND_RCSR) | REG_UMI_NAND_RCSR_CS_ASSERTED, ®_UMI_NAND_RCSR);
- REG_UMI_NAND_TCR &= ~REG_UMI_NAND_TCR_WORD16;
+ writel(readl(®_UMI_NAND_TCR) & ~REG_UMI_NAND_TCR_WORD16, ®_UMI_NAND_TCR);
/* enable writes to flash */
- REG_UMI_MMD_ICR |= REG_UMI_MMD_ICR_FLASH_WP;
+ writel(readl(®_UMI_MMD_ICR) | REG_UMI_MMD_ICR_FLASH_WP, ®_UMI_MMD_ICR);
writel(NAND_CMD_RESET, bcm_umi_io_base + REG_NAND_CMD_OFFSET);
nand_bcm_umi_wait_till_ready();
diff --git a/drivers/mtd/nand/nand_bcm_umi.h b/drivers/mtd/nand/nand_bcm_umi.h
index 198b304..d901866 100644
--- a/drivers/mtd/nand/nand_bcm_umi.h
+++ b/drivers/mtd/nand/nand_bcm_umi.h
@@ -17,7 +17,7 @@
/* ---- Include Files ---------------------------------------------------- */
#include <mach/reg_umi.h>
#include <mach/reg_nand.h>
-#include <cfg_global.h>
+#include <mach/cfg_global.h>
/* ---- Constants and Types ---------------------------------------------- */
#if (CFG_GLOBAL_CHIP_FAMILY == CFG_GLOBAL_CHIP_FAMILY_BCMRING)
@@ -48,7 +48,7 @@
/* Check in device is ready */
static inline int nand_bcm_umi_dev_ready(void)
{
- return REG_UMI_NAND_RCSR & REG_UMI_NAND_RCSR_RDY;
+ return readl(®_UMI_NAND_RCSR) & REG_UMI_NAND_RCSR_RDY;
}
/* Wait until device is ready */
@@ -62,10 +62,11 @@
static inline void nand_bcm_umi_hamming_enable_hwecc(void)
{
/* disable and reset ECC, 512 byte page */
- REG_UMI_NAND_ECC_CSR &= ~(REG_UMI_NAND_ECC_CSR_ECC_ENABLE |
- REG_UMI_NAND_ECC_CSR_256BYTE);
+ writel(readl(®_UMI_NAND_ECC_CSR) & ~(REG_UMI_NAND_ECC_CSR_ECC_ENABLE |
+ REG_UMI_NAND_ECC_CSR_256BYTE), ®_UMI_NAND_ECC_CSR);
/* enable ECC */
- REG_UMI_NAND_ECC_CSR |= REG_UMI_NAND_ECC_CSR_ECC_ENABLE;
+ writel(readl(®_UMI_NAND_ECC_CSR) | REG_UMI_NAND_ECC_CSR_ECC_ENABLE,
+ ®_UMI_NAND_ECC_CSR);
}
#if NAND_ECC_BCH
@@ -76,18 +77,18 @@
static inline void nand_bcm_umi_bch_enable_read_hwecc(void)
{
/* disable and reset ECC */
- REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID;
+ writel(REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID, ®_UMI_BCH_CTRL_STATUS);
/* Turn on ECC */
- REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN;
+ writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN, ®_UMI_BCH_CTRL_STATUS);
}
/* Enable BCH Write ECC */
static inline void nand_bcm_umi_bch_enable_write_hwecc(void)
{
/* disable and reset ECC */
- REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID;
+ writel(REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID, ®_UMI_BCH_CTRL_STATUS);
/* Turn on ECC */
- REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN;
+ writel(REG_UMI_BCH_CTRL_STATUS_ECC_WR_EN, ®_UMI_BCH_CTRL_STATUS);
}
/* Config number of BCH ECC bytes */
@@ -99,9 +100,9 @@
uint32_t numBits = numEccBytes * 8;
/* disable and reset ECC */
- REG_UMI_BCH_CTRL_STATUS =
- REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID |
- REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID;
+ writel(REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID |
+ REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID,
+ ®_UMI_BCH_CTRL_STATUS);
/* Every correctible bit requires 13 ECC bits */
tValue = (uint32_t) (numBits / ECC_BITS_PER_CORRECTABLE_BIT);
@@ -113,23 +114,21 @@
kValue = nValue - (tValue * ECC_BITS_PER_CORRECTABLE_BIT);
/* Write the settings */
- REG_UMI_BCH_N = nValue;
- REG_UMI_BCH_T = tValue;
- REG_UMI_BCH_K = kValue;
+ writel(nValue, ®_UMI_BCH_N);
+ writel(tValue, ®_UMI_BCH_T);
+ writel(kValue, ®_UMI_BCH_K);
}
/* Pause during ECC read calculation to skip bytes in OOB */
static inline void nand_bcm_umi_bch_pause_read_ecc_calc(void)
{
- REG_UMI_BCH_CTRL_STATUS =
- REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN |
- REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC;
+ writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN | REG_UMI_BCH_CTRL_STATUS_PAUSE_ECC_DEC, ®_UMI_BCH_CTRL_STATUS);
}
/* Resume during ECC read calculation after skipping bytes in OOB */
static inline void nand_bcm_umi_bch_resume_read_ecc_calc(void)
{
- REG_UMI_BCH_CTRL_STATUS = REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN;
+ writel(REG_UMI_BCH_CTRL_STATUS_ECC_RD_EN, ®_UMI_BCH_CTRL_STATUS);
}
/* Poll read ECC calc to check when hardware completes */
@@ -139,7 +138,7 @@
do {
/* wait for ECC to be valid */
- regVal = REG_UMI_BCH_CTRL_STATUS;
+ regVal = readl(®_UMI_BCH_CTRL_STATUS);
} while ((regVal & REG_UMI_BCH_CTRL_STATUS_RD_ECC_VALID) == 0);
return regVal;
@@ -149,7 +148,7 @@
static inline void nand_bcm_umi_bch_poll_write_ecc_calc(void)
{
/* wait for ECC to be valid */
- while ((REG_UMI_BCH_CTRL_STATUS & REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID)
+ while ((readl(®_UMI_BCH_CTRL_STATUS) & REG_UMI_BCH_CTRL_STATUS_WR_ECC_VALID)
== 0)
;
}
@@ -170,9 +169,9 @@
if (pageSize != NAND_DATA_ACCESS_SIZE) {
/* skip BI */
#if defined(__KERNEL__) && !defined(STANDALONE)
- *oobp++ = REG_NAND_DATA8;
+ *oobp++ = readb(®_NAND_DATA8);
#else
- REG_NAND_DATA8;
+ readb(®_NAND_DATA8);
#endif
numToRead--;
}
@@ -180,9 +179,9 @@
while (numToRead > numEccBytes) {
/* skip free oob region */
#if defined(__KERNEL__) && !defined(STANDALONE)
- *oobp++ = REG_NAND_DATA8;
+ *oobp++ = readb(®_NAND_DATA8);
#else
- REG_NAND_DATA8;
+ readb(®_NAND_DATA8);
#endif
numToRead--;
}
@@ -193,11 +192,11 @@
while (numToRead > 11) {
#if defined(__KERNEL__) && !defined(STANDALONE)
- *oobp = REG_NAND_DATA8;
+ *oobp = readb(®_NAND_DATA8);
eccCalc[eccPos++] = *oobp;
oobp++;
#else
- eccCalc[eccPos++] = REG_NAND_DATA8;
+ eccCalc[eccPos++] = readb(®_NAND_DATA8);
#endif
numToRead--;
}
@@ -207,9 +206,9 @@
if (numToRead == 11) {
/* read BI */
#if defined(__KERNEL__) && !defined(STANDALONE)
- *oobp++ = REG_NAND_DATA8;
+ *oobp++ = readb(®_NAND_DATA8);
#else
- REG_NAND_DATA8;
+ readb(®_NAND_DATA8);
#endif
numToRead--;
}
@@ -219,11 +218,11 @@
nand_bcm_umi_bch_resume_read_ecc_calc();
while (numToRead) {
#if defined(__KERNEL__) && !defined(STANDALONE)
- *oobp = REG_NAND_DATA8;
+ *oobp = readb(®_NAND_DATA8);
eccCalc[eccPos++] = *oobp;
oobp++;
#else
- eccCalc[eccPos++] = REG_NAND_DATA8;
+ eccCalc[eccPos++] = readb(®_NAND_DATA8);
#endif
numToRead--;
}
@@ -255,7 +254,7 @@
if (pageSize == NAND_DATA_ACCESS_SIZE) {
/* Now fill in the ECC bytes */
if (numEccBytes >= 13)
- eccVal = REG_UMI_BCH_WR_ECC_3;
+ eccVal = readl(®_UMI_BCH_WR_ECC_3);
/* Usually we skip CM in oob[0,1] */
NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[0],
@@ -268,7 +267,7 @@
eccVal & 0xff); /* ECC 12 */
if (numEccBytes >= 9)
- eccVal = REG_UMI_BCH_WR_ECC_2;
+ eccVal = readl(®_UMI_BCH_WR_ECC_2);
NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[3],
(eccVal >> 24) & 0xff); /* ECC11 */
@@ -281,7 +280,7 @@
/* Now fill in the ECC bytes */
if (numEccBytes >= 13)
- eccVal = REG_UMI_BCH_WR_ECC_3;
+ eccVal = readl(®_UMI_BCH_WR_ECC_3);
/* Usually skip CM in oob[1,2] */
NAND_BCM_UMI_ECC_WRITE(numEccBytes, 15, &oobp[1],
@@ -294,7 +293,7 @@
eccVal & 0xff); /* ECC12 */
if (numEccBytes >= 9)
- eccVal = REG_UMI_BCH_WR_ECC_2;
+ eccVal = readl(®_UMI_BCH_WR_ECC_2);
NAND_BCM_UMI_ECC_WRITE(numEccBytes, 12, &oobp[4],
(eccVal >> 24) & 0xff); /* ECC11 */
@@ -309,7 +308,7 @@
eccVal & 0xff); /* ECC8 */
if (numEccBytes >= 5)
- eccVal = REG_UMI_BCH_WR_ECC_1;
+ eccVal = readl(®_UMI_BCH_WR_ECC_1);
NAND_BCM_UMI_ECC_WRITE(numEccBytes, 8, &oobp[8],
(eccVal >> 24) & 0xff); /* ECC7 */
@@ -321,7 +320,7 @@
eccVal & 0xff); /* ECC4 */
if (numEccBytes >= 1)
- eccVal = REG_UMI_BCH_WR_ECC_0;
+ eccVal = readl(®_UMI_BCH_WR_ECC_0);
NAND_BCM_UMI_ECC_WRITE(numEccBytes, 4, &oobp[12],
(eccVal >> 24) & 0xff); /* ECC3 */
diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c
index cc0f00d..b446c96 100644
--- a/drivers/pinctrl/pinctrl-coh901.c
+++ b/drivers/pinctrl/pinctrl-coh901.c
@@ -1,11 +1,8 @@
/*
* U300 GPIO module.
*
- * Copyright (C) 2007-2011 ST-Ericsson AB
+ * Copyright (C) 2007-2012 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
- * This can driver either of the two basic GPIO cores
- * available in the U300 platforms:
- * COH 901 335 - Used in DB3150 (U300 1.0) and DB3200 (U330 1.0)
* COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
* Author: Linus Walleij <linus.walleij@linaro.org>
* Author: Jonas Aaberg <jonas.aberg@stericsson.com>
@@ -24,19 +21,22 @@
#include <linux/slab.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/pinconf-generic.h>
-#include <mach/gpio-u300.h>
+#include <linux/platform_data/pinctrl-coh901.h>
#include "pinctrl-coh901.h"
+#define U300_GPIO_PORT_STRIDE (0x30)
/*
- * Register definitions for COH 901 335 variant
+ * Control Register 32bit (R/W)
+ * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
+ * gives the number of GPIO pins.
+ * bit 8-2 (mask 0x000001FC) contains the core version ID.
*/
-#define U300_335_PORT_STRIDE (0x1C)
-/* Port X Pin Data Register 32bit, this is both input and output (R/W) */
-#define U300_335_PXPDIR (0x00)
-#define U300_335_PXPDOR (0x00)
-/* Port X Pin Config Register 32bit (R/W) */
-#define U300_335_PXPCR (0x04)
-/* This register layout is the same in both blocks */
+#define U300_GPIO_CR (0x00)
+#define U300_GPIO_CR_SYNC_SEL_ENABLE (0x00000002UL)
+#define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL)
+#define U300_GPIO_PXPDIR (0x04)
+#define U300_GPIO_PXPDOR (0x08)
+#define U300_GPIO_PXPCR (0x0C)
#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL)
#define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL)
#define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL)
@@ -44,53 +44,17 @@
#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL)
#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL)
#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL)
-/* Port X Interrupt Event Register 32bit (R/W) */
-#define U300_335_PXIEV (0x08)
-/* Port X Interrupt Enable Register 32bit (R/W) */
-#define U300_335_PXIEN (0x0C)
-/* Port X Interrupt Force Register 32bit (R/W) */
-#define U300_335_PXIFR (0x10)
-/* Port X Interrupt Config Register 32bit (R/W) */
-#define U300_335_PXICR (0x14)
-/* This register layout is the same in both blocks */
+#define U300_GPIO_PXPER (0x10)
+#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
+#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
+#define U300_GPIO_PXIEV (0x14)
+#define U300_GPIO_PXIEN (0x18)
+#define U300_GPIO_PXIFR (0x1C)
+#define U300_GPIO_PXICR (0x20)
#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL)
#define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL)
#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL)
#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
-/* Port X Pull-up Enable Register 32bit (R/W) */
-#define U300_335_PXPER (0x18)
-/* This register layout is the same in both blocks */
-#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
-#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
-/* Control Register 32bit (R/W) */
-#define U300_335_CR (0x54)
-#define U300_335_CR_BLOCK_CLOCK_ENABLE (0x00000001UL)
-
-/*
- * Register definitions for COH 901 571 / 3 variant
- */
-#define U300_571_PORT_STRIDE (0x30)
-/*
- * Control Register 32bit (R/W)
- * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
- * gives the number of GPIO pins.
- * bit 8-2 (mask 0x000001FC) contains the core version ID.
- */
-#define U300_571_CR (0x00)
-#define U300_571_CR_SYNC_SEL_ENABLE (0x00000002UL)
-#define U300_571_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL)
-/*
- * These registers have the same layout and function as the corresponding
- * COH 901 335 registers, just at different offset.
- */
-#define U300_571_PXPDIR (0x04)
-#define U300_571_PXPDOR (0x08)
-#define U300_571_PXPCR (0x0C)
-#define U300_571_PXPER (0x10)
-#define U300_571_PXIEV (0x14)
-#define U300_571_PXIEN (0x18)
-#define U300_571_PXIFR (0x1C)
-#define U300_571_PXICR (0x20)
/* 8 bits per port, no version has more than 7 ports */
#define U300_GPIO_PINS_PER_PORT 8
@@ -149,8 +113,6 @@
/* BS335 has seven ports of 8 bits each = GPIO pins 0..55 */
#define BS335_GPIO_NUM_PORTS 7
-/* BS365 has five ports of 8 bits each = GPIO pins 0..39 */
-#define BS365_GPIO_NUM_PORTS 5
#define U300_FLOATING_INPUT { \
.bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \
@@ -172,7 +134,6 @@
.outval = 1, \
}
-
/* Initial configuration */
static const struct __initconst u300_gpio_confdata
bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
@@ -255,66 +216,6 @@
}
};
-static const struct __initconst u300_gpio_confdata
-bs365_gpio_config[BS365_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
- /* Port 0, pins 0-7 */
- {
- U300_FLOATING_INPUT,
- U300_OUTPUT_LOW,
- U300_FLOATING_INPUT,
- U300_OUTPUT_LOW,
- U300_OUTPUT_LOW,
- U300_OUTPUT_LOW,
- U300_PULL_UP_INPUT,
- U300_FLOATING_INPUT,
- },
- /* Port 1, pins 0-7 */
- {
- U300_OUTPUT_LOW,
- U300_FLOATING_INPUT,
- U300_OUTPUT_LOW,
- U300_FLOATING_INPUT,
- U300_FLOATING_INPUT,
- U300_OUTPUT_HIGH,
- U300_OUTPUT_LOW,
- U300_OUTPUT_LOW,
- },
- /* Port 2, pins 0-7 */
- {
- U300_FLOATING_INPUT,
- U300_PULL_UP_INPUT,
- U300_OUTPUT_LOW,
- U300_OUTPUT_LOW,
- U300_PULL_UP_INPUT,
- U300_PULL_UP_INPUT,
- U300_PULL_UP_INPUT,
- U300_PULL_UP_INPUT,
- },
- /* Port 3, pins 0-7 */
- {
- U300_PULL_UP_INPUT,
- U300_PULL_UP_INPUT,
- U300_PULL_UP_INPUT,
- U300_PULL_UP_INPUT,
- U300_PULL_UP_INPUT,
- U300_PULL_UP_INPUT,
- U300_PULL_UP_INPUT,
- U300_PULL_UP_INPUT,
- },
- /* Port 4, pins 0-7 */
- {
- U300_PULL_UP_INPUT,
- U300_PULL_UP_INPUT,
- U300_PULL_UP_INPUT,
- U300_PULL_UP_INPUT,
- /* These 4 pins doesn't exist on DB3210 */
- U300_OUTPUT_LOW,
- U300_OUTPUT_LOW,
- U300_OUTPUT_LOW,
- U300_OUTPUT_LOW,
- }
-};
-
/**
* to_u300_gpio() - get the pointer to u300_gpio
* @chip: the gpio chip member of the structure u300_gpio
@@ -716,13 +617,7 @@
const struct u300_gpio_confdata *conf;
int offset = (i*8) + j;
- if (plat->variant == U300_GPIO_COH901571_3_BS335)
- conf = &bs335_gpio_config[i][j];
- else if (plat->variant == U300_GPIO_COH901571_3_BS365)
- conf = &bs365_gpio_config[i][j];
- else
- break;
-
+ conf = &bs335_gpio_config[i][j];
u300_gpio_init_pin(gpio, offset, conf);
}
}
@@ -796,50 +691,27 @@
goto err_no_ioremap;
}
- if (plat->variant == U300_GPIO_COH901335) {
- dev_info(gpio->dev,
- "initializing GPIO Controller COH 901 335\n");
- gpio->stride = U300_335_PORT_STRIDE;
- gpio->pcr = U300_335_PXPCR;
- gpio->dor = U300_335_PXPDOR;
- gpio->dir = U300_335_PXPDIR;
- gpio->per = U300_335_PXPER;
- gpio->icr = U300_335_PXICR;
- gpio->ien = U300_335_PXIEN;
- gpio->iev = U300_335_PXIEV;
- ifr = U300_335_PXIFR;
+ dev_info(gpio->dev,
+ "initializing GPIO Controller COH 901 571/3\n");
+ gpio->stride = U300_GPIO_PORT_STRIDE;
+ gpio->pcr = U300_GPIO_PXPCR;
+ gpio->dor = U300_GPIO_PXPDOR;
+ gpio->dir = U300_GPIO_PXPDIR;
+ gpio->per = U300_GPIO_PXPER;
+ gpio->icr = U300_GPIO_PXICR;
+ gpio->ien = U300_GPIO_PXIEN;
+ gpio->iev = U300_GPIO_PXIEV;
+ ifr = U300_GPIO_PXIFR;
- /* Turn on the GPIO block */
- writel(U300_335_CR_BLOCK_CLOCK_ENABLE,
- gpio->base + U300_335_CR);
- } else if (plat->variant == U300_GPIO_COH901571_3_BS335 ||
- plat->variant == U300_GPIO_COH901571_3_BS365) {
- dev_info(gpio->dev,
- "initializing GPIO Controller COH 901 571/3\n");
- gpio->stride = U300_571_PORT_STRIDE;
- gpio->pcr = U300_571_PXPCR;
- gpio->dor = U300_571_PXPDOR;
- gpio->dir = U300_571_PXPDIR;
- gpio->per = U300_571_PXPER;
- gpio->icr = U300_571_PXICR;
- gpio->ien = U300_571_PXIEN;
- gpio->iev = U300_571_PXIEV;
- ifr = U300_571_PXIFR;
-
- val = readl(gpio->base + U300_571_CR);
- dev_info(gpio->dev, "COH901571/3 block version: %d, " \
- "number of cores: %d totalling %d pins\n",
- ((val & 0x000001FC) >> 2),
- ((val & 0x0000FE00) >> 9),
- ((val & 0x0000FE00) >> 9) * 8);
- writel(U300_571_CR_BLOCK_CLKRQ_ENABLE,
- gpio->base + U300_571_CR);
- u300_gpio_init_coh901571(gpio, plat);
- } else {
- dev_err(gpio->dev, "unknown block variant\n");
- err = -ENODEV;
- goto err_unknown_variant;
- }
+ val = readl(gpio->base + U300_GPIO_CR);
+ dev_info(gpio->dev, "COH901571/3 block version: %d, " \
+ "number of cores: %d totalling %d pins\n",
+ ((val & 0x000001FC) >> 2),
+ ((val & 0x0000FE00) >> 9),
+ ((val & 0x0000FE00) >> 9) * 8);
+ writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE,
+ gpio->base + U300_GPIO_CR);
+ u300_gpio_init_coh901571(gpio, plat);
/* Add each port with its IRQ separately */
INIT_LIST_HEAD(&gpio->port_list);
@@ -906,7 +778,6 @@
err_no_chip:
err_no_port:
u300_gpio_free_ports(gpio);
-err_unknown_variant:
iounmap(gpio->base);
err_no_ioremap:
release_mem_region(gpio->memres->start, resource_size(gpio->memres));
@@ -923,16 +794,11 @@
static int __exit u300_gpio_remove(struct platform_device *pdev)
{
- struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev);
struct u300_gpio *gpio = platform_get_drvdata(pdev);
int err;
/* Turn off the GPIO block */
- if (plat->variant == U300_GPIO_COH901335)
- writel(0x00000000U, gpio->base + U300_335_CR);
- if (plat->variant == U300_GPIO_COH901571_3_BS335 ||
- plat->variant == U300_GPIO_COH901571_3_BS365)
- writel(0x00000000U, gpio->base + U300_571_CR);
+ writel(0x00000000U, gpio->base + U300_GPIO_CR);
err = gpiochip_remove(&gpio->chip);
if (err < 0) {
diff --git a/drivers/regulator/tps6586x-regulator.c b/drivers/regulator/tps6586x-regulator.c
index 19241fc..8212526 100644
--- a/drivers/regulator/tps6586x-regulator.c
+++ b/drivers/regulator/tps6586x-regulator.c
@@ -162,6 +162,9 @@
.disable = tps6586x_regulator_disable,
};
+static struct regulator_ops tps6586x_sys_regulator_ops = {
+};
+
static const unsigned int tps6586x_ldo0_voltages[] = {
1200000, 1500000, 1800000, 2500000, 2700000, 2850000, 3100000, 3300000,
};
@@ -230,15 +233,28 @@
TPS6586X_REGULATOR_DVM_GOREG(goreg, gobit) \
}
+#define TPS6586X_SYS_REGULATOR() \
+{ \
+ .desc = { \
+ .supply_name = "sys", \
+ .name = "REG-SYS", \
+ .ops = &tps6586x_sys_regulator_ops, \
+ .type = REGULATOR_VOLTAGE, \
+ .id = TPS6586X_ID_SYS, \
+ .owner = THIS_MODULE, \
+ }, \
+}
+
static struct tps6586x_regulator tps6586x_regulator[] = {
+ TPS6586X_SYS_REGULATOR(),
TPS6586X_LDO(LDO_0, "vinldo01", ldo0, SUPPLYV1, 5, 3, ENC, 0, END, 0),
TPS6586X_LDO(LDO_3, "vinldo23", ldo, SUPPLYV4, 0, 3, ENC, 2, END, 2),
- TPS6586X_LDO(LDO_5, NULL, ldo, SUPPLYV6, 0, 3, ENE, 6, ENE, 6),
+ TPS6586X_LDO(LDO_5, "REG-SYS", ldo, SUPPLYV6, 0, 3, ENE, 6, ENE, 6),
TPS6586X_LDO(LDO_6, "vinldo678", ldo, SUPPLYV3, 0, 3, ENC, 4, END, 4),
TPS6586X_LDO(LDO_7, "vinldo678", ldo, SUPPLYV3, 3, 3, ENC, 5, END, 5),
TPS6586X_LDO(LDO_8, "vinldo678", ldo, SUPPLYV2, 5, 3, ENC, 6, END, 6),
TPS6586X_LDO(LDO_9, "vinldo9", ldo, SUPPLYV6, 3, 3, ENE, 7, ENE, 7),
- TPS6586X_LDO(LDO_RTC, NULL, ldo, SUPPLYV4, 3, 3, V4, 7, V4, 7),
+ TPS6586X_LDO(LDO_RTC, "REG-SYS", ldo, SUPPLYV4, 3, 3, V4, 7, V4, 7),
TPS6586X_LDO(LDO_1, "vinldo01", dvm, SUPPLYV1, 0, 5, ENC, 1, END, 1),
TPS6586X_LDO(SM_2, "vin-sm2", sm2, SUPPLYV2, 0, 5, ENC, 7, END, 7),
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index 7065df6..7de2285 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -13,7 +13,6 @@
default y if PXA3xx
default y if ARCH_EP93XX
default y if ARCH_AT91
- default y if ARCH_PNX4008
default y if MFD_TC6393XB
default y if ARCH_W90X900
default y if ARCH_DAVINCI_DA8XX
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 075d2ec..276add2 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -292,7 +292,7 @@
depends on USB && USB_ARCH_HAS_OHCI
select ISP1301_OMAP if MACH_OMAP_H2 || MACH_OMAP_H3
select USB_OTG_UTILS if ARCH_OMAP
- select USB_ISP1301 if ARCH_LPC32XX || ARCH_PNX4008
+ select USB_ISP1301 if ARCH_LPC32XX
---help---
The Open Host Controller Interface (OHCI) is a standard for accessing
USB 1.1 host controller hardware. It does more in hardware than Intel's
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 2b1e8d8..6780010 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -1049,7 +1049,7 @@
#define PLATFORM_DRIVER ohci_hcd_at91_driver
#endif
-#if defined(CONFIG_ARCH_PNX4008) || defined(CONFIG_ARCH_LPC32XX)
+#ifdef CONFIG_ARCH_LPC32XX
#include "ohci-nxp.c"
#define PLATFORM_DRIVER usb_hcd_nxp_driver
#endif
diff --git a/drivers/usb/host/ohci-nxp.c b/drivers/usb/host/ohci-nxp.c
index a446386..1199666 100644
--- a/drivers/usb/host/ohci-nxp.c
+++ b/drivers/usb/host/ohci-nxp.c
@@ -2,7 +2,6 @@
* driver for NXP USB Host devices
*
* Currently supported OHCI host devices:
- * - Philips PNX4008
* - NXP LPC32xx
*
* Authors: Dmitry Chigirev <source@mvista.com>
@@ -66,38 +65,6 @@
static struct clk *usb_dev_clk;
static struct clk *usb_otg_clk;
-static void isp1301_configure_pnx4008(void)
-{
- /* PNX4008 only supports DAT_SE0 USB mode */
- /* PNX4008 R2A requires setting the MAX603 to output 3.6V */
- /* Power up externel charge-pump */
-
- i2c_smbus_write_byte_data(isp1301_i2c_client,
- ISP1301_I2C_MODE_CONTROL_1, MC1_DAT_SE0 | MC1_SPEED_REG);
- i2c_smbus_write_byte_data(isp1301_i2c_client,
- ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
- ~(MC1_DAT_SE0 | MC1_SPEED_REG));
- i2c_smbus_write_byte_data(isp1301_i2c_client,
- ISP1301_I2C_MODE_CONTROL_2,
- MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL);
- i2c_smbus_write_byte_data(isp1301_i2c_client,
- ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR,
- ~(MC2_BI_DI | MC2_PSW_EN | MC2_SPD_SUSP_CTRL));
- i2c_smbus_write_byte_data(isp1301_i2c_client,
- ISP1301_I2C_OTG_CONTROL_1, OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN);
- i2c_smbus_write_byte_data(isp1301_i2c_client,
- ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
- ~(OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN));
- i2c_smbus_write_byte_data(isp1301_i2c_client,
- ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, 0xFF);
- i2c_smbus_write_byte_data(isp1301_i2c_client,
- ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR,
- 0xFF);
- i2c_smbus_write_byte_data(isp1301_i2c_client,
- ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR,
- 0xFF);
-}
-
static void isp1301_configure_lpc32xx(void)
{
/* LPC32XX only supports DAT_SE0 USB mode */
@@ -149,10 +116,7 @@
static void isp1301_configure(void)
{
- if (machine_is_pnx4008())
- isp1301_configure_pnx4008();
- else
- isp1301_configure_lpc32xx();
+ isp1301_configure_lpc32xx();
}
static inline void isp1301_vbus_on(void)
@@ -241,47 +205,6 @@
.start_port_reset = ohci_start_port_reset,
};
-static void nxp_set_usb_bits(void)
-{
- if (machine_is_pnx4008()) {
- start_int_set_falling_edge(SE_USB_OTG_ATX_INT_N);
- start_int_ack(SE_USB_OTG_ATX_INT_N);
- start_int_umask(SE_USB_OTG_ATX_INT_N);
-
- start_int_set_rising_edge(SE_USB_OTG_TIMER_INT);
- start_int_ack(SE_USB_OTG_TIMER_INT);
- start_int_umask(SE_USB_OTG_TIMER_INT);
-
- start_int_set_rising_edge(SE_USB_I2C_INT);
- start_int_ack(SE_USB_I2C_INT);
- start_int_umask(SE_USB_I2C_INT);
-
- start_int_set_rising_edge(SE_USB_INT);
- start_int_ack(SE_USB_INT);
- start_int_umask(SE_USB_INT);
-
- start_int_set_rising_edge(SE_USB_NEED_CLK_INT);
- start_int_ack(SE_USB_NEED_CLK_INT);
- start_int_umask(SE_USB_NEED_CLK_INT);
-
- start_int_set_rising_edge(SE_USB_AHB_NEED_CLK_INT);
- start_int_ack(SE_USB_AHB_NEED_CLK_INT);
- start_int_umask(SE_USB_AHB_NEED_CLK_INT);
- }
-}
-
-static void nxp_unset_usb_bits(void)
-{
- if (machine_is_pnx4008()) {
- start_int_mask(SE_USB_OTG_ATX_INT_N);
- start_int_mask(SE_USB_OTG_TIMER_INT);
- start_int_mask(SE_USB_I2C_INT);
- start_int_mask(SE_USB_INT);
- start_int_mask(SE_USB_NEED_CLK_INT);
- start_int_mask(SE_USB_AHB_NEED_CLK_INT);
- }
-}
-
static int __devinit usb_hcd_nxp_probe(struct platform_device *pdev)
{
struct usb_hcd *hcd = 0;
@@ -376,9 +299,6 @@
goto out8;
}
- /* Set all USB bits in the Start Enable register */
- nxp_set_usb_bits();
-
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "Failed to get MEM resource\n");
@@ -413,7 +333,6 @@
nxp_stop_hc();
out8:
- nxp_unset_usb_bits();
usb_put_hcd(hcd);
out7:
clk_disable(usb_otg_clk);
@@ -441,7 +360,6 @@
nxp_stop_hc();
release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
usb_put_hcd(hcd);
- nxp_unset_usb_bits();
clk_disable(usb_pll_clk);
clk_put(usb_pll_clk);
clk_disable(usb_dev_clk);
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 53d7571..ad1bb938 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -237,12 +237,12 @@
here to enable the OMAP1610/OMAP1710/OMAP2420/OMAP3430/OMAP4430 watchdog timer.
config PNX4008_WATCHDOG
- tristate "PNX4008 and LPC32XX Watchdog"
- depends on ARCH_PNX4008 || ARCH_LPC32XX
+ tristate "LPC32XX Watchdog"
+ depends on ARCH_LPC32XX
select WATCHDOG_CORE
help
Say Y here if to include support for the watchdog timer
- in the PNX4008 or LPC32XX processor.
+ in the LPC32XX processor.
This driver can be built as a module by choosing M. The module
will be called pnx4008_wdt.
diff --git a/drivers/watchdog/ks8695_wdt.c b/drivers/watchdog/ks8695_wdt.c
index 59e75d9..c1a4d3b 100644
--- a/drivers/watchdog/ks8695_wdt.c
+++ b/drivers/watchdog/ks8695_wdt.c
@@ -24,7 +24,19 @@
#include <linux/io.h>
#include <linux/uaccess.h>
#include <mach/hardware.h>
-#include <mach/regs-timer.h>
+
+#define KS8695_TMR_OFFSET (0xF0000 + 0xE400)
+#define KS8695_TMR_VA (KS8695_IO_VA + KS8695_TMR_OFFSET)
+
+/*
+ * Timer registers
+ */
+#define KS8695_TMCON (0x00) /* Timer Control Register */
+#define KS8695_T0TC (0x08) /* Timer 0 Timeout Count Register */
+#define TMCON_T0EN (1 << 0) /* Timer 0 Enable */
+
+/* Timer0 Timeout Counter Register */
+#define T0TC_WATCHDOG (0xff) /* Enable watchdog mode */
#define WDT_DEFAULT_TIME 5 /* seconds */
#define WDT_MAX_TIME 171 /* seconds */
diff --git a/include/linux/mfd/tps6586x.h b/include/linux/mfd/tps6586x.h
index f350fd0..9451471 100644
--- a/include/linux/mfd/tps6586x.h
+++ b/include/linux/mfd/tps6586x.h
@@ -14,6 +14,7 @@
#define TPS6586X_SLEW_RATE_MASK 0x07
enum {
+ TPS6586X_ID_SYS,
TPS6586X_ID_SM_0,
TPS6586X_ID_SM_1,
TPS6586X_ID_SM_2,
diff --git a/arch/arm/mach-u300/include/mach/gpio-u300.h b/include/linux/platform_data/pinctrl-coh901.h
similarity index 71%
rename from arch/arm/mach-u300/include/mach/gpio-u300.h
rename to include/linux/platform_data/pinctrl-coh901.h
index e81400c..30dea25 100644
--- a/arch/arm/mach-u300/include/mach/gpio-u300.h
+++ b/include/linux/platform_data/pinctrl-coh901.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2007-2011 ST-Ericsson AB
+ * Copyright (C) 2007-2012 ST-Ericsson AB
* License terms: GNU General Public License (GPL) version 2
* GPIO block resgister definitions and inline macros for
* U300 GPIO COH 901 335 or COH 901 571/3
@@ -10,24 +10,13 @@
#define __MACH_U300_GPIO_U300_H
/**
- * enum u300_gpio_variant - the type of U300 GPIO employed
- */
-enum u300_gpio_variant {
- U300_GPIO_COH901335,
- U300_GPIO_COH901571_3_BS335,
- U300_GPIO_COH901571_3_BS365,
-};
-
-/**
* struct u300_gpio_platform - U300 GPIO platform data
- * @variant: IP block variant
* @ports: number of GPIO block ports
* @gpio_base: first GPIO number for this block (use a free range)
* @gpio_irq_base: first GPIO IRQ number for this block (use a free range)
* @pinctrl_device: pin control device to spawn as child
*/
struct u300_gpio_platform {
- enum u300_gpio_variant variant;
u8 ports;
int gpio_base;
int gpio_irq_base;
